2 * Synopsys DesignWare I2C adapter driver (master only).
4 * Based on the TI DAVINCI I2C adapter driver.
6 * Copyright (C) 2006 Texas Instruments.
7 * Copyright (C) 2007 MontaVista Software Inc.
8 * Copyright (C) 2009 Provigent Ltd.
10 * ----------------------------------------------------------------------------
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 * ----------------------------------------------------------------------------
24 #include <linux/export.h>
25 #include <linux/errno.h>
26 #include <linux/err.h>
27 #include <linux/i2c.h>
28 #include <linux/interrupt.h>
30 #include <linux/pm_runtime.h>
31 #include <linux/delay.h>
32 #include <linux/module.h>
33 #include "i2c-designware-core.h"
40 #define DW_IC_DATA_CMD 0x10
41 #define DW_IC_SS_SCL_HCNT 0x14
42 #define DW_IC_SS_SCL_LCNT 0x18
43 #define DW_IC_FS_SCL_HCNT 0x1c
44 #define DW_IC_FS_SCL_LCNT 0x20
45 #define DW_IC_HS_SCL_HCNT 0x24
46 #define DW_IC_HS_SCL_LCNT 0x28
47 #define DW_IC_INTR_STAT 0x2c
48 #define DW_IC_INTR_MASK 0x30
49 #define DW_IC_RAW_INTR_STAT 0x34
50 #define DW_IC_RX_TL 0x38
51 #define DW_IC_TX_TL 0x3c
52 #define DW_IC_CLR_INTR 0x40
53 #define DW_IC_CLR_RX_UNDER 0x44
54 #define DW_IC_CLR_RX_OVER 0x48
55 #define DW_IC_CLR_TX_OVER 0x4c
56 #define DW_IC_CLR_RD_REQ 0x50
57 #define DW_IC_CLR_TX_ABRT 0x54
58 #define DW_IC_CLR_RX_DONE 0x58
59 #define DW_IC_CLR_ACTIVITY 0x5c
60 #define DW_IC_CLR_STOP_DET 0x60
61 #define DW_IC_CLR_START_DET 0x64
62 #define DW_IC_CLR_GEN_CALL 0x68
63 #define DW_IC_ENABLE 0x6c
64 #define DW_IC_STATUS 0x70
65 #define DW_IC_TXFLR 0x74
66 #define DW_IC_RXFLR 0x78
67 #define DW_IC_SDA_HOLD 0x7c
68 #define DW_IC_TX_ABRT_SOURCE 0x80
69 #define DW_IC_ENABLE_STATUS 0x9c
70 #define DW_IC_COMP_PARAM_1 0xf4
71 #define DW_IC_COMP_VERSION 0xf8
72 #define DW_IC_SDA_HOLD_MIN_VERS 0x3131312A
73 #define DW_IC_COMP_TYPE 0xfc
74 #define DW_IC_COMP_TYPE_VALUE 0x44570140
76 #define DW_IC_INTR_RX_UNDER 0x001
77 #define DW_IC_INTR_RX_OVER 0x002
78 #define DW_IC_INTR_RX_FULL 0x004
79 #define DW_IC_INTR_TX_OVER 0x008
80 #define DW_IC_INTR_TX_EMPTY 0x010
81 #define DW_IC_INTR_RD_REQ 0x020
82 #define DW_IC_INTR_TX_ABRT 0x040
83 #define DW_IC_INTR_RX_DONE 0x080
84 #define DW_IC_INTR_ACTIVITY 0x100
85 #define DW_IC_INTR_STOP_DET 0x200
86 #define DW_IC_INTR_START_DET 0x400
87 #define DW_IC_INTR_GEN_CALL 0x800
89 #define DW_IC_INTR_DEFAULT_MASK (DW_IC_INTR_RX_FULL | \
90 DW_IC_INTR_TX_EMPTY | \
91 DW_IC_INTR_TX_ABRT | \
94 #define DW_IC_STATUS_ACTIVITY 0x1
96 #define DW_IC_SDA_HOLD_RX_SHIFT 16
97 #define DW_IC_SDA_HOLD_RX_MASK GENMASK(23, DW_IC_SDA_HOLD_RX_SHIFT)
99 #define DW_IC_ERR_TX_ABRT 0x1
101 #define DW_IC_TAR_10BITADDR_MASTER BIT(12)
103 #define DW_IC_COMP_PARAM_1_SPEED_MODE_HIGH (BIT(2) | BIT(3))
104 #define DW_IC_COMP_PARAM_1_SPEED_MODE_MASK GENMASK(3, 2)
109 #define STATUS_IDLE 0x0
110 #define STATUS_WRITE_IN_PROGRESS 0x1
111 #define STATUS_READ_IN_PROGRESS 0x2
113 #define TIMEOUT 20 /* ms */
116 * hardware abort codes from the DW_IC_TX_ABRT_SOURCE register
118 * only expected abort codes are listed here
119 * refer to the datasheet for the full list
121 #define ABRT_7B_ADDR_NOACK 0
122 #define ABRT_10ADDR1_NOACK 1
123 #define ABRT_10ADDR2_NOACK 2
124 #define ABRT_TXDATA_NOACK 3
125 #define ABRT_GCALL_NOACK 4
126 #define ABRT_GCALL_READ 5
127 #define ABRT_SBYTE_ACKDET 7
128 #define ABRT_SBYTE_NORSTRT 9
129 #define ABRT_10B_RD_NORSTRT 10
130 #define ABRT_MASTER_DIS 11
133 #define DW_IC_TX_ABRT_7B_ADDR_NOACK (1UL << ABRT_7B_ADDR_NOACK)
134 #define DW_IC_TX_ABRT_10ADDR1_NOACK (1UL << ABRT_10ADDR1_NOACK)
135 #define DW_IC_TX_ABRT_10ADDR2_NOACK (1UL << ABRT_10ADDR2_NOACK)
136 #define DW_IC_TX_ABRT_TXDATA_NOACK (1UL << ABRT_TXDATA_NOACK)
137 #define DW_IC_TX_ABRT_GCALL_NOACK (1UL << ABRT_GCALL_NOACK)
138 #define DW_IC_TX_ABRT_GCALL_READ (1UL << ABRT_GCALL_READ)
139 #define DW_IC_TX_ABRT_SBYTE_ACKDET (1UL << ABRT_SBYTE_ACKDET)
140 #define DW_IC_TX_ABRT_SBYTE_NORSTRT (1UL << ABRT_SBYTE_NORSTRT)
141 #define DW_IC_TX_ABRT_10B_RD_NORSTRT (1UL << ABRT_10B_RD_NORSTRT)
142 #define DW_IC_TX_ABRT_MASTER_DIS (1UL << ABRT_MASTER_DIS)
143 #define DW_IC_TX_ARB_LOST (1UL << ARB_LOST)
145 #define DW_IC_TX_ABRT_NOACK (DW_IC_TX_ABRT_7B_ADDR_NOACK | \
146 DW_IC_TX_ABRT_10ADDR1_NOACK | \
147 DW_IC_TX_ABRT_10ADDR2_NOACK | \
148 DW_IC_TX_ABRT_TXDATA_NOACK | \
149 DW_IC_TX_ABRT_GCALL_NOACK)
151 static char *abort_sources
[] = {
152 [ABRT_7B_ADDR_NOACK
] =
153 "slave address not acknowledged (7bit mode)",
154 [ABRT_10ADDR1_NOACK
] =
155 "first address byte not acknowledged (10bit mode)",
156 [ABRT_10ADDR2_NOACK
] =
157 "second address byte not acknowledged (10bit mode)",
158 [ABRT_TXDATA_NOACK
] =
159 "data not acknowledged",
161 "no acknowledgement for a general call",
163 "read after general call",
164 [ABRT_SBYTE_ACKDET
] =
165 "start byte acknowledged",
166 [ABRT_SBYTE_NORSTRT
] =
167 "trying to send start byte when restart is disabled",
168 [ABRT_10B_RD_NORSTRT
] =
169 "trying to read when restart is disabled (10bit mode)",
171 "trying to use disabled adapter",
176 static u32
dw_readl(struct dw_i2c_dev
*dev
, int offset
)
180 if (dev
->accessor_flags
& ACCESS_16BIT
)
181 value
= readw_relaxed(dev
->base
+ offset
) |
182 (readw_relaxed(dev
->base
+ offset
+ 2) << 16);
184 value
= readl_relaxed(dev
->base
+ offset
);
186 if (dev
->accessor_flags
& ACCESS_SWAP
)
187 return swab32(value
);
192 static void dw_writel(struct dw_i2c_dev
*dev
, u32 b
, int offset
)
194 if (dev
->accessor_flags
& ACCESS_SWAP
)
197 if (dev
->accessor_flags
& ACCESS_16BIT
) {
198 writew_relaxed((u16
)b
, dev
->base
+ offset
);
199 writew_relaxed((u16
)(b
>> 16), dev
->base
+ offset
+ 2);
201 writel_relaxed(b
, dev
->base
+ offset
);
206 i2c_dw_scl_hcnt(u32 ic_clk
, u32 tSYMBOL
, u32 tf
, int cond
, int offset
)
209 * DesignWare I2C core doesn't seem to have solid strategy to meet
210 * the tHD;STA timing spec. Configuring _HCNT based on tHIGH spec
211 * will result in violation of the tHD;STA spec.
215 * Conditional expression:
217 * IC_[FS]S_SCL_HCNT + (1+4+3) >= IC_CLK * tHIGH
219 * This is based on the DW manuals, and represents an ideal
220 * configuration. The resulting I2C bus speed will be
221 * faster than any of the others.
223 * If your hardware is free from tHD;STA issue, try this one.
225 return (ic_clk
* tSYMBOL
+ 500000) / 1000000 - 8 + offset
;
228 * Conditional expression:
230 * IC_[FS]S_SCL_HCNT + 3 >= IC_CLK * (tHD;STA + tf)
232 * This is just experimental rule; the tHD;STA period turned
233 * out to be proportinal to (_HCNT + 3). With this setting,
234 * we could meet both tHIGH and tHD;STA timing specs.
236 * If unsure, you'd better to take this alternative.
238 * The reason why we need to take into account "tf" here,
239 * is the same as described in i2c_dw_scl_lcnt().
241 return (ic_clk
* (tSYMBOL
+ tf
) + 500000) / 1000000
245 static u32
i2c_dw_scl_lcnt(u32 ic_clk
, u32 tLOW
, u32 tf
, int offset
)
248 * Conditional expression:
250 * IC_[FS]S_SCL_LCNT + 1 >= IC_CLK * (tLOW + tf)
252 * DW I2C core starts counting the SCL CNTs for the LOW period
253 * of the SCL clock (tLOW) as soon as it pulls the SCL line.
254 * In order to meet the tLOW timing spec, we need to take into
255 * account the fall time of SCL signal (tf). Default tf value
256 * should be 0.3 us, for safety.
258 return ((ic_clk
* (tLOW
+ tf
) + 500000) / 1000000) - 1 + offset
;
261 static void __i2c_dw_enable(struct dw_i2c_dev
*dev
, bool enable
)
263 dw_writel(dev
, enable
, DW_IC_ENABLE
);
266 static void __i2c_dw_enable_and_wait(struct dw_i2c_dev
*dev
, bool enable
)
271 __i2c_dw_enable(dev
, enable
);
272 if ((dw_readl(dev
, DW_IC_ENABLE_STATUS
) & 1) == enable
)
276 * Wait 10 times the signaling period of the highest I2C
277 * transfer supported by the driver (for 400KHz this is
278 * 25us) as described in the DesignWare I2C databook.
280 usleep_range(25, 250);
283 dev_warn(dev
->dev
, "timeout in %sabling adapter\n",
284 enable
? "en" : "dis");
287 static unsigned long i2c_dw_clk_rate(struct dw_i2c_dev
*dev
)
290 * Clock is not necessary if we got LCNT/HCNT values directly from
293 if (WARN_ON_ONCE(!dev
->get_clk_rate_khz
))
295 return dev
->get_clk_rate_khz(dev
);
298 static int i2c_dw_acquire_lock(struct dw_i2c_dev
*dev
)
302 if (!dev
->acquire_lock
)
305 ret
= dev
->acquire_lock(dev
);
309 dev_err(dev
->dev
, "couldn't acquire bus ownership\n");
314 static void i2c_dw_release_lock(struct dw_i2c_dev
*dev
)
316 if (dev
->release_lock
)
317 dev
->release_lock(dev
);
321 * i2c_dw_init() - initialize the designware i2c master hardware
322 * @dev: device private data
324 * This functions configures and enables the I2C master.
325 * This function is called during I2C init function, and in case of timeout at
328 int i2c_dw_init(struct dw_i2c_dev
*dev
)
331 u32 reg
, comp_param1
;
332 u32 sda_falling_time
, scl_falling_time
;
335 ret
= i2c_dw_acquire_lock(dev
);
339 reg
= dw_readl(dev
, DW_IC_COMP_TYPE
);
340 if (reg
== ___constant_swab32(DW_IC_COMP_TYPE_VALUE
)) {
341 /* Configure register endianess access */
342 dev
->accessor_flags
|= ACCESS_SWAP
;
343 } else if (reg
== (DW_IC_COMP_TYPE_VALUE
& 0x0000ffff)) {
344 /* Configure register access mode 16bit */
345 dev
->accessor_flags
|= ACCESS_16BIT
;
346 } else if (reg
!= DW_IC_COMP_TYPE_VALUE
) {
347 dev_err(dev
->dev
, "Unknown Synopsys component type: "
349 i2c_dw_release_lock(dev
);
353 comp_param1
= dw_readl(dev
, DW_IC_COMP_PARAM_1
);
355 /* Disable the adapter */
356 __i2c_dw_enable_and_wait(dev
, false);
358 /* set standard and fast speed deviders for high/low periods */
360 sda_falling_time
= dev
->sda_falling_time
?: 300; /* ns */
361 scl_falling_time
= dev
->scl_falling_time
?: 300; /* ns */
363 /* Set SCL timing parameters for standard-mode */
364 if (dev
->ss_hcnt
&& dev
->ss_lcnt
) {
368 hcnt
= i2c_dw_scl_hcnt(i2c_dw_clk_rate(dev
),
369 4000, /* tHD;STA = tHIGH = 4.0 us */
371 0, /* 0: DW default, 1: Ideal */
373 lcnt
= i2c_dw_scl_lcnt(i2c_dw_clk_rate(dev
),
374 4700, /* tLOW = 4.7 us */
378 dw_writel(dev
, hcnt
, DW_IC_SS_SCL_HCNT
);
379 dw_writel(dev
, lcnt
, DW_IC_SS_SCL_LCNT
);
380 dev_dbg(dev
->dev
, "Standard-mode HCNT:LCNT = %d:%d\n", hcnt
, lcnt
);
382 /* Set SCL timing parameters for fast-mode or fast-mode plus */
383 if ((dev
->clk_freq
== 1000000) && dev
->fp_hcnt
&& dev
->fp_lcnt
) {
386 } else if (dev
->fs_hcnt
&& dev
->fs_lcnt
) {
390 hcnt
= i2c_dw_scl_hcnt(i2c_dw_clk_rate(dev
),
391 600, /* tHD;STA = tHIGH = 0.6 us */
393 0, /* 0: DW default, 1: Ideal */
395 lcnt
= i2c_dw_scl_lcnt(i2c_dw_clk_rate(dev
),
396 1300, /* tLOW = 1.3 us */
400 dw_writel(dev
, hcnt
, DW_IC_FS_SCL_HCNT
);
401 dw_writel(dev
, lcnt
, DW_IC_FS_SCL_LCNT
);
402 dev_dbg(dev
->dev
, "Fast-mode HCNT:LCNT = %d:%d\n", hcnt
, lcnt
);
404 if ((dev
->master_cfg
& DW_IC_CON_SPEED_MASK
) ==
405 DW_IC_CON_SPEED_HIGH
) {
406 if ((comp_param1
& DW_IC_COMP_PARAM_1_SPEED_MODE_MASK
)
407 != DW_IC_COMP_PARAM_1_SPEED_MODE_HIGH
) {
408 dev_err(dev
->dev
, "High Speed not supported!\n");
409 dev
->master_cfg
&= ~DW_IC_CON_SPEED_MASK
;
410 dev
->master_cfg
|= DW_IC_CON_SPEED_FAST
;
411 } else if (dev
->hs_hcnt
&& dev
->hs_lcnt
) {
414 dw_writel(dev
, hcnt
, DW_IC_HS_SCL_HCNT
);
415 dw_writel(dev
, lcnt
, DW_IC_HS_SCL_LCNT
);
416 dev_dbg(dev
->dev
, "HighSpeed-mode HCNT:LCNT = %d:%d\n",
421 /* Configure SDA Hold Time if required */
422 reg
= dw_readl(dev
, DW_IC_COMP_VERSION
);
423 if (reg
>= DW_IC_SDA_HOLD_MIN_VERS
) {
424 if (!dev
->sda_hold_time
) {
425 /* Keep previous hold time setting if no one set it */
426 dev
->sda_hold_time
= dw_readl(dev
, DW_IC_SDA_HOLD
);
429 * Workaround for avoiding TX arbitration lost in case I2C
430 * slave pulls SDA down "too quickly" after falling egde of
431 * SCL by enabling non-zero SDA RX hold. Specification says it
432 * extends incoming SDA low to high transition while SCL is
433 * high but it apprears to help also above issue.
435 if (!(dev
->sda_hold_time
& DW_IC_SDA_HOLD_RX_MASK
))
436 dev
->sda_hold_time
|= 1 << DW_IC_SDA_HOLD_RX_SHIFT
;
437 dw_writel(dev
, dev
->sda_hold_time
, DW_IC_SDA_HOLD
);
440 "Hardware too old to adjust SDA hold time.\n");
443 /* Configure Tx/Rx FIFO threshold levels */
444 dw_writel(dev
, dev
->tx_fifo_depth
/ 2, DW_IC_TX_TL
);
445 dw_writel(dev
, 0, DW_IC_RX_TL
);
447 /* configure the i2c master */
448 dw_writel(dev
, dev
->master_cfg
, DW_IC_CON
);
450 i2c_dw_release_lock(dev
);
454 EXPORT_SYMBOL_GPL(i2c_dw_init
);
457 * Waiting for bus not busy
459 static int i2c_dw_wait_bus_not_busy(struct dw_i2c_dev
*dev
)
461 int timeout
= TIMEOUT
;
463 while (dw_readl(dev
, DW_IC_STATUS
) & DW_IC_STATUS_ACTIVITY
) {
465 dev_warn(dev
->dev
, "timeout waiting for bus ready\n");
469 usleep_range(1000, 1100);
475 static void i2c_dw_xfer_init(struct dw_i2c_dev
*dev
)
477 struct i2c_msg
*msgs
= dev
->msgs
;
480 /* Disable the adapter */
481 __i2c_dw_enable_and_wait(dev
, false);
483 /* if the slave address is ten bit address, enable 10BITADDR */
484 if (dev
->dynamic_tar_update_enabled
) {
486 * If I2C_DYNAMIC_TAR_UPDATE is set, the 10-bit addressing
487 * mode has to be enabled via bit 12 of IC_TAR register,
488 * otherwise bit 4 of IC_CON is used.
490 if (msgs
[dev
->msg_write_idx
].flags
& I2C_M_TEN
)
491 ic_tar
= DW_IC_TAR_10BITADDR_MASTER
;
493 u32 ic_con
= dw_readl(dev
, DW_IC_CON
);
495 if (msgs
[dev
->msg_write_idx
].flags
& I2C_M_TEN
)
496 ic_con
|= DW_IC_CON_10BITADDR_MASTER
;
498 ic_con
&= ~DW_IC_CON_10BITADDR_MASTER
;
499 dw_writel(dev
, ic_con
, DW_IC_CON
);
503 * Set the slave (target) address and enable 10-bit addressing mode
506 dw_writel(dev
, msgs
[dev
->msg_write_idx
].addr
| ic_tar
, DW_IC_TAR
);
508 /* enforce disabled interrupts (due to HW issues) */
509 i2c_dw_disable_int(dev
);
511 /* Enable the adapter */
512 __i2c_dw_enable(dev
, true);
514 /* Clear and enable interrupts */
515 dw_readl(dev
, DW_IC_CLR_INTR
);
516 dw_writel(dev
, DW_IC_INTR_DEFAULT_MASK
, DW_IC_INTR_MASK
);
520 * Initiate (and continue) low level master read/write transaction.
521 * This function is only called from i2c_dw_isr, and pumping i2c_msg
522 * messages into the tx buffer. Even if the size of i2c_msg data is
523 * longer than the size of the tx buffer, it handles everything.
526 i2c_dw_xfer_msg(struct dw_i2c_dev
*dev
)
528 struct i2c_msg
*msgs
= dev
->msgs
;
530 int tx_limit
, rx_limit
;
531 u32 addr
= msgs
[dev
->msg_write_idx
].addr
;
532 u32 buf_len
= dev
->tx_buf_len
;
533 u8
*buf
= dev
->tx_buf
;
534 bool need_restart
= false;
536 intr_mask
= DW_IC_INTR_DEFAULT_MASK
;
538 for (; dev
->msg_write_idx
< dev
->msgs_num
; dev
->msg_write_idx
++) {
540 * if target address has changed, we need to
541 * reprogram the target address in the i2c
542 * adapter when we are done with this transfer
544 if (msgs
[dev
->msg_write_idx
].addr
!= addr
) {
546 "%s: invalid target address\n", __func__
);
547 dev
->msg_err
= -EINVAL
;
551 if (msgs
[dev
->msg_write_idx
].len
== 0) {
553 "%s: invalid message length\n", __func__
);
554 dev
->msg_err
= -EINVAL
;
558 if (!(dev
->status
& STATUS_WRITE_IN_PROGRESS
)) {
560 buf
= msgs
[dev
->msg_write_idx
].buf
;
561 buf_len
= msgs
[dev
->msg_write_idx
].len
;
563 /* If both IC_EMPTYFIFO_HOLD_MASTER_EN and
564 * IC_RESTART_EN are set, we must manually
565 * set restart bit between messages.
567 if ((dev
->master_cfg
& DW_IC_CON_RESTART_EN
) &&
568 (dev
->msg_write_idx
> 0))
572 tx_limit
= dev
->tx_fifo_depth
- dw_readl(dev
, DW_IC_TXFLR
);
573 rx_limit
= dev
->rx_fifo_depth
- dw_readl(dev
, DW_IC_RXFLR
);
575 while (buf_len
> 0 && tx_limit
> 0 && rx_limit
> 0) {
579 * If IC_EMPTYFIFO_HOLD_MASTER_EN is set we must
580 * manually set the stop bit. However, it cannot be
581 * detected from the registers so we set it always
582 * when writing/reading the last byte.
584 if (dev
->msg_write_idx
== dev
->msgs_num
- 1 &&
590 need_restart
= false;
593 if (msgs
[dev
->msg_write_idx
].flags
& I2C_M_RD
) {
595 /* avoid rx buffer overrun */
596 if (dev
->rx_outstanding
>= dev
->rx_fifo_depth
)
599 dw_writel(dev
, cmd
| 0x100, DW_IC_DATA_CMD
);
601 dev
->rx_outstanding
++;
603 dw_writel(dev
, cmd
| *buf
++, DW_IC_DATA_CMD
);
604 tx_limit
--; buf_len
--;
608 dev
->tx_buf_len
= buf_len
;
611 /* more bytes to be written */
612 dev
->status
|= STATUS_WRITE_IN_PROGRESS
;
615 dev
->status
&= ~STATUS_WRITE_IN_PROGRESS
;
619 * If i2c_msg index search is completed, we don't need TX_EMPTY
620 * interrupt any more.
622 if (dev
->msg_write_idx
== dev
->msgs_num
)
623 intr_mask
&= ~DW_IC_INTR_TX_EMPTY
;
628 dw_writel(dev
, intr_mask
, DW_IC_INTR_MASK
);
632 i2c_dw_read(struct dw_i2c_dev
*dev
)
634 struct i2c_msg
*msgs
= dev
->msgs
;
637 for (; dev
->msg_read_idx
< dev
->msgs_num
; dev
->msg_read_idx
++) {
641 if (!(msgs
[dev
->msg_read_idx
].flags
& I2C_M_RD
))
644 if (!(dev
->status
& STATUS_READ_IN_PROGRESS
)) {
645 len
= msgs
[dev
->msg_read_idx
].len
;
646 buf
= msgs
[dev
->msg_read_idx
].buf
;
648 len
= dev
->rx_buf_len
;
652 rx_valid
= dw_readl(dev
, DW_IC_RXFLR
);
654 for (; len
> 0 && rx_valid
> 0; len
--, rx_valid
--) {
655 *buf
++ = dw_readl(dev
, DW_IC_DATA_CMD
);
656 dev
->rx_outstanding
--;
660 dev
->status
|= STATUS_READ_IN_PROGRESS
;
661 dev
->rx_buf_len
= len
;
665 dev
->status
&= ~STATUS_READ_IN_PROGRESS
;
669 static int i2c_dw_handle_tx_abort(struct dw_i2c_dev
*dev
)
671 unsigned long abort_source
= dev
->abort_source
;
674 if (abort_source
& DW_IC_TX_ABRT_NOACK
) {
675 for_each_set_bit(i
, &abort_source
, ARRAY_SIZE(abort_sources
))
677 "%s: %s\n", __func__
, abort_sources
[i
]);
681 for_each_set_bit(i
, &abort_source
, ARRAY_SIZE(abort_sources
))
682 dev_err(dev
->dev
, "%s: %s\n", __func__
, abort_sources
[i
]);
684 if (abort_source
& DW_IC_TX_ARB_LOST
)
686 else if (abort_source
& DW_IC_TX_ABRT_GCALL_READ
)
687 return -EINVAL
; /* wrong msgs[] data */
693 * Prepare controller for a transaction and call i2c_dw_xfer_msg
696 i2c_dw_xfer(struct i2c_adapter
*adap
, struct i2c_msg msgs
[], int num
)
698 struct dw_i2c_dev
*dev
= i2c_get_adapdata(adap
);
701 dev_dbg(dev
->dev
, "%s: msgs: %d\n", __func__
, num
);
703 pm_runtime_get_sync(dev
->dev
);
705 reinit_completion(&dev
->cmd_complete
);
709 dev
->msg_write_idx
= 0;
710 dev
->msg_read_idx
= 0;
712 dev
->status
= STATUS_IDLE
;
713 dev
->abort_source
= 0;
714 dev
->rx_outstanding
= 0;
716 ret
= i2c_dw_acquire_lock(dev
);
720 ret
= i2c_dw_wait_bus_not_busy(dev
);
724 /* start the transfers */
725 i2c_dw_xfer_init(dev
);
727 /* wait for tx to complete */
728 if (!wait_for_completion_timeout(&dev
->cmd_complete
, adap
->timeout
)) {
729 dev_err(dev
->dev
, "controller timed out\n");
730 /* i2c_dw_init implicitly disables the adapter */
737 * We must disable the adapter before returning and signaling the end
738 * of the current transfer. Otherwise the hardware might continue
739 * generating interrupts which in turn causes a race condition with
740 * the following transfer. Needs some more investigation if the
741 * additional interrupts are a hardware bug or this driver doesn't
742 * handle them correctly yet.
744 __i2c_dw_enable(dev
, false);
752 if (likely(!dev
->cmd_err
&& !dev
->status
)) {
757 /* We have an error */
758 if (dev
->cmd_err
== DW_IC_ERR_TX_ABRT
) {
759 ret
= i2c_dw_handle_tx_abort(dev
);
765 "transfer terminated early - interrupt latency too high?\n");
770 i2c_dw_release_lock(dev
);
773 pm_runtime_mark_last_busy(dev
->dev
);
774 pm_runtime_put_autosuspend(dev
->dev
);
779 static u32
i2c_dw_func(struct i2c_adapter
*adap
)
781 struct dw_i2c_dev
*dev
= i2c_get_adapdata(adap
);
782 return dev
->functionality
;
785 static struct i2c_algorithm i2c_dw_algo
= {
786 .master_xfer
= i2c_dw_xfer
,
787 .functionality
= i2c_dw_func
,
790 static u32
i2c_dw_read_clear_intrbits(struct dw_i2c_dev
*dev
)
795 * The IC_INTR_STAT register just indicates "enabled" interrupts.
796 * Ths unmasked raw version of interrupt status bits are available
797 * in the IC_RAW_INTR_STAT register.
800 * stat = dw_readl(IC_INTR_STAT);
802 * stat = dw_readl(IC_RAW_INTR_STAT) & dw_readl(IC_INTR_MASK);
804 * The raw version might be useful for debugging purposes.
806 stat
= dw_readl(dev
, DW_IC_INTR_STAT
);
809 * Do not use the IC_CLR_INTR register to clear interrupts, or
810 * you'll miss some interrupts, triggered during the period from
811 * dw_readl(IC_INTR_STAT) to dw_readl(IC_CLR_INTR).
813 * Instead, use the separately-prepared IC_CLR_* registers.
815 if (stat
& DW_IC_INTR_RX_UNDER
)
816 dw_readl(dev
, DW_IC_CLR_RX_UNDER
);
817 if (stat
& DW_IC_INTR_RX_OVER
)
818 dw_readl(dev
, DW_IC_CLR_RX_OVER
);
819 if (stat
& DW_IC_INTR_TX_OVER
)
820 dw_readl(dev
, DW_IC_CLR_TX_OVER
);
821 if (stat
& DW_IC_INTR_RD_REQ
)
822 dw_readl(dev
, DW_IC_CLR_RD_REQ
);
823 if (stat
& DW_IC_INTR_TX_ABRT
) {
825 * The IC_TX_ABRT_SOURCE register is cleared whenever
826 * the IC_CLR_TX_ABRT is read. Preserve it beforehand.
828 dev
->abort_source
= dw_readl(dev
, DW_IC_TX_ABRT_SOURCE
);
829 dw_readl(dev
, DW_IC_CLR_TX_ABRT
);
831 if (stat
& DW_IC_INTR_RX_DONE
)
832 dw_readl(dev
, DW_IC_CLR_RX_DONE
);
833 if (stat
& DW_IC_INTR_ACTIVITY
)
834 dw_readl(dev
, DW_IC_CLR_ACTIVITY
);
835 if (stat
& DW_IC_INTR_STOP_DET
)
836 dw_readl(dev
, DW_IC_CLR_STOP_DET
);
837 if (stat
& DW_IC_INTR_START_DET
)
838 dw_readl(dev
, DW_IC_CLR_START_DET
);
839 if (stat
& DW_IC_INTR_GEN_CALL
)
840 dw_readl(dev
, DW_IC_CLR_GEN_CALL
);
846 * Interrupt service routine. This gets called whenever an I2C interrupt
849 static irqreturn_t
i2c_dw_isr(int this_irq
, void *dev_id
)
851 struct dw_i2c_dev
*dev
= dev_id
;
854 enabled
= dw_readl(dev
, DW_IC_ENABLE
);
855 stat
= dw_readl(dev
, DW_IC_RAW_INTR_STAT
);
856 dev_dbg(dev
->dev
, "%s: enabled=%#x stat=%#x\n", __func__
, enabled
, stat
);
857 if (!enabled
|| !(stat
& ~DW_IC_INTR_ACTIVITY
))
860 stat
= i2c_dw_read_clear_intrbits(dev
);
862 if (stat
& DW_IC_INTR_TX_ABRT
) {
863 dev
->cmd_err
|= DW_IC_ERR_TX_ABRT
;
864 dev
->status
= STATUS_IDLE
;
867 * Anytime TX_ABRT is set, the contents of the tx/rx
868 * buffers are flushed. Make sure to skip them.
870 dw_writel(dev
, 0, DW_IC_INTR_MASK
);
874 if (stat
& DW_IC_INTR_RX_FULL
)
877 if (stat
& DW_IC_INTR_TX_EMPTY
)
878 i2c_dw_xfer_msg(dev
);
881 * No need to modify or disable the interrupt mask here.
882 * i2c_dw_xfer_msg() will take care of it according to
883 * the current transmit status.
887 if ((stat
& (DW_IC_INTR_TX_ABRT
| DW_IC_INTR_STOP_DET
)) || dev
->msg_err
)
888 complete(&dev
->cmd_complete
);
889 else if (unlikely(dev
->accessor_flags
& ACCESS_INTR_MASK
)) {
890 /* workaround to trigger pending interrupt */
891 stat
= dw_readl(dev
, DW_IC_INTR_MASK
);
892 i2c_dw_disable_int(dev
);
893 dw_writel(dev
, stat
, DW_IC_INTR_MASK
);
899 void i2c_dw_disable(struct dw_i2c_dev
*dev
)
901 /* Disable controller */
902 __i2c_dw_enable_and_wait(dev
, false);
904 /* Disable all interupts */
905 dw_writel(dev
, 0, DW_IC_INTR_MASK
);
906 dw_readl(dev
, DW_IC_CLR_INTR
);
908 EXPORT_SYMBOL_GPL(i2c_dw_disable
);
910 void i2c_dw_disable_int(struct dw_i2c_dev
*dev
)
912 dw_writel(dev
, 0, DW_IC_INTR_MASK
);
914 EXPORT_SYMBOL_GPL(i2c_dw_disable_int
);
916 u32
i2c_dw_read_comp_param(struct dw_i2c_dev
*dev
)
918 return dw_readl(dev
, DW_IC_COMP_PARAM_1
);
920 EXPORT_SYMBOL_GPL(i2c_dw_read_comp_param
);
922 int i2c_dw_probe(struct dw_i2c_dev
*dev
)
924 struct i2c_adapter
*adap
= &dev
->adapter
;
928 init_completion(&dev
->cmd_complete
);
930 r
= i2c_dw_init(dev
);
934 r
= i2c_dw_acquire_lock(dev
);
939 * Test if dynamic TAR update is enabled in this controller by writing
940 * to IC_10BITADDR_MASTER field in IC_CON: when it is enabled this
941 * field is read-only so it should not succeed
943 reg
= dw_readl(dev
, DW_IC_CON
);
944 dw_writel(dev
, reg
^ DW_IC_CON_10BITADDR_MASTER
, DW_IC_CON
);
946 if ((dw_readl(dev
, DW_IC_CON
) & DW_IC_CON_10BITADDR_MASTER
) ==
947 (reg
& DW_IC_CON_10BITADDR_MASTER
)) {
948 dev
->dynamic_tar_update_enabled
= true;
949 dev_dbg(dev
->dev
, "Dynamic TAR update enabled");
952 i2c_dw_release_lock(dev
);
954 snprintf(adap
->name
, sizeof(adap
->name
),
955 "Synopsys DesignWare I2C adapter");
957 adap
->algo
= &i2c_dw_algo
;
958 adap
->dev
.parent
= dev
->dev
;
959 i2c_set_adapdata(adap
, dev
);
961 i2c_dw_disable_int(dev
);
962 r
= devm_request_irq(dev
->dev
, dev
->irq
, i2c_dw_isr
,
963 IRQF_SHARED
| IRQF_COND_SUSPEND
,
964 dev_name(dev
->dev
), dev
);
966 dev_err(dev
->dev
, "failure requesting irq %i: %d\n",
972 * Increment PM usage count during adapter registration in order to
973 * avoid possible spurious runtime suspend when adapter device is
974 * registered to the device core and immediate resume in case bus has
975 * registered I2C slaves that do I2C transfers in their probe.
977 pm_runtime_get_noresume(dev
->dev
);
978 r
= i2c_add_numbered_adapter(adap
);
980 dev_err(dev
->dev
, "failure adding adapter: %d\n", r
);
981 pm_runtime_put_noidle(dev
->dev
);
985 EXPORT_SYMBOL_GPL(i2c_dw_probe
);
987 MODULE_DESCRIPTION("Synopsys DesignWare I2C bus adapter core");
988 MODULE_LICENSE("GPL");