drivers/i2c/busses/i2c-designware-master.c

   1 /*
   2  * Synopsys DesignWare I2C adapter driver (master only).
   3  *
   4  * Based on the TI DAVINCI I2C adapter driver.
   5  *
   6  * Copyright (C) 2006 Texas Instruments.
   7  * Copyright (C) 2007 MontaVista Software Inc.
   8  * Copyright (C) 2009 Provigent Ltd.
   9  *
  10  * ----------------------------------------------------------------------------
  11  *
  12  * This program is free software; you can redistribute it and/or modify
  13  * it under the terms of the GNU General Public License as published by
  14  * the Free Software Foundation; either version 2 of the License, or
  15  * (at your option) any later version.
  16  *
  17  * This program is distributed in the hope that it will be useful,
  18  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  20  * GNU General Public License for more details.
  21  * ----------------------------------------------------------------------------
  22  *
  23  */
  24 #include <linux/delay.h>
  25 #include <linux/err.h>
  26 #include <linux/errno.h>
  27 #include <linux/export.h>
  28 #include <linux/i2c.h>
  29 #include <linux/interrupt.h>
  30 #include <linux/io.h>
  31 #include <linux/module.h>
  32 #include <linux/pm_runtime.h>
  33
  34 #include "i2c-designware-core.h"
  35
  36 static void i2c_dw_configure_fifo_master(struct dw_i2c_dev *dev)
  37 {
  38         /* Configure Tx/Rx FIFO threshold levels */
  39         dw_writel(dev, dev->tx_fifo_depth / 2, DW_IC_TX_TL);
  40         dw_writel(dev, 0, DW_IC_RX_TL);
  41
  42         /* Configure the I2C master */
  43         dw_writel(dev, dev->master_cfg, DW_IC_CON);
  44 }
  45
  46 /**
  47  * i2c_dw_init() - Initialize the designware I2C master hardware
  48  * @dev: device private data
  49  *
  50  * This functions configures and enables the I2C master.
  51  * This function is called during I2C init function, and in case of timeout at
  52  * run time.
  53  */
  54 int i2c_dw_init(struct dw_i2c_dev *dev)
  55 {
  56         u32 hcnt, lcnt;
  57         u32 reg, comp_param1;
  58         u32 sda_falling_time, scl_falling_time;
  59         int ret;
  60
  61         ret = i2c_dw_acquire_lock(dev);
  62         if (ret)
  63                 return ret;
  64
  65         reg = dw_readl(dev, DW_IC_COMP_TYPE);
  66         if (reg == ___constant_swab32(DW_IC_COMP_TYPE_VALUE)) {
  67                 /* Configure register endianess access */
  68                 dev->flags |= ACCESS_SWAP;
  69         } else if (reg == (DW_IC_COMP_TYPE_VALUE & 0x0000ffff)) {
  70                 /* Configure register access mode 16bit */
  71                 dev->flags |= ACCESS_16BIT;
  72         } else if (reg != DW_IC_COMP_TYPE_VALUE) {
  73                 dev_err(dev->dev,
  74                         "Unknown Synopsys component type: 0x%08x\n", reg);
  75                 i2c_dw_release_lock(dev);
  76                 return -ENODEV;
  77         }
  78
  79         comp_param1 = dw_readl(dev, DW_IC_COMP_PARAM_1);
  80
  81         /* Disable the adapter */
  82         __i2c_dw_enable_and_wait(dev, false);
  83
  84         /* Set standard and fast speed deviders for high/low periods */
  85
  86         sda_falling_time = dev->sda_falling_time ?: 300; /* ns */
  87         scl_falling_time = dev->scl_falling_time ?: 300; /* ns */
  88
  89         /* Set SCL timing parameters for standard-mode */
  90         if (dev->ss_hcnt && dev->ss_lcnt) {
  91                 hcnt = dev->ss_hcnt;
  92                 lcnt = dev->ss_lcnt;
  93         } else {
  94                 hcnt = i2c_dw_scl_hcnt(i2c_dw_clk_rate(dev),
  95                                         4000,   /* tHD;STA = tHIGH = 4.0 us */
  96                                         sda_falling_time,
  97                                         0,      /* 0: DW default, 1: Ideal */
  98                                         0);     /* No offset */
  99                 lcnt = i2c_dw_scl_lcnt(i2c_dw_clk_rate(dev),
 100                                         4700,   /* tLOW = 4.7 us */
 101                                         scl_falling_time,
 102                                         0);     /* No offset */
 103         }
 104         dw_writel(dev, hcnt, DW_IC_SS_SCL_HCNT);
 105         dw_writel(dev, lcnt, DW_IC_SS_SCL_LCNT);
 106         dev_dbg(dev->dev, "Standard-mode HCNT:LCNT = %d:%d\n", hcnt, lcnt);
 107
 108         /* Set SCL timing parameters for fast-mode or fast-mode plus */
 109         if ((dev->clk_freq == 1000000) && dev->fp_hcnt && dev->fp_lcnt) {
 110                 hcnt = dev->fp_hcnt;
 111                 lcnt = dev->fp_lcnt;
 112         } else if (dev->fs_hcnt && dev->fs_lcnt) {
 113                 hcnt = dev->fs_hcnt;
 114                 lcnt = dev->fs_lcnt;
 115         } else {
 116                 hcnt = i2c_dw_scl_hcnt(i2c_dw_clk_rate(dev),
 117                                         600,    /* tHD;STA = tHIGH = 0.6 us */
 118                                         sda_falling_time,
 119                                         0,      /* 0: DW default, 1: Ideal */
 120                                         0);     /* No offset */
 121                 lcnt = i2c_dw_scl_lcnt(i2c_dw_clk_rate(dev),
 122                                         1300,   /* tLOW = 1.3 us */
 123                                         scl_falling_time,
 124                                         0);     /* No offset */
 125         }
 126         dw_writel(dev, hcnt, DW_IC_FS_SCL_HCNT);
 127         dw_writel(dev, lcnt, DW_IC_FS_SCL_LCNT);
 128         dev_dbg(dev->dev, "Fast-mode HCNT:LCNT = %d:%d\n", hcnt, lcnt);
 129
 130         if ((dev->master_cfg & DW_IC_CON_SPEED_MASK) ==
 131                 DW_IC_CON_SPEED_HIGH) {
 132                 if ((comp_param1 & DW_IC_COMP_PARAM_1_SPEED_MODE_MASK)
 133                         != DW_IC_COMP_PARAM_1_SPEED_MODE_HIGH) {
 134                         dev_err(dev->dev, "High Speed not supported!\n");
 135                         dev->master_cfg &= ~DW_IC_CON_SPEED_MASK;
 136                         dev->master_cfg |= DW_IC_CON_SPEED_FAST;
 137                 } else if (dev->hs_hcnt && dev->hs_lcnt) {
 138                         hcnt = dev->hs_hcnt;
 139                         lcnt = dev->hs_lcnt;
 140                         dw_writel(dev, hcnt, DW_IC_HS_SCL_HCNT);
 141                         dw_writel(dev, lcnt, DW_IC_HS_SCL_LCNT);
 142                         dev_dbg(dev->dev, "HighSpeed-mode HCNT:LCNT = %d:%d\n",
 143                                 hcnt, lcnt);
 144                 }
 145         }
 146
 147         /* Configure SDA Hold Time if required */
 148         reg = dw_readl(dev, DW_IC_COMP_VERSION);
 149         if (reg >= DW_IC_SDA_HOLD_MIN_VERS) {
 150                 if (!dev->sda_hold_time) {
 151                         /* Keep previous hold time setting if no one set it */
 152                         dev->sda_hold_time = dw_readl(dev, DW_IC_SDA_HOLD);
 153                 }
 154                 /*
 155                  * Workaround for avoiding TX arbitration lost in case I2C
 156                  * slave pulls SDA down "too quickly" after falling egde of
 157                  * SCL by enabling non-zero SDA RX hold. Specification says it
 158                  * extends incoming SDA low to high transition while SCL is
 159                  * high but it apprears to help also above issue.
 160                  */
 161                 if (!(dev->sda_hold_time & DW_IC_SDA_HOLD_RX_MASK))
 162                         dev->sda_hold_time |= 1 << DW_IC_SDA_HOLD_RX_SHIFT;
 163                 dw_writel(dev, dev->sda_hold_time, DW_IC_SDA_HOLD);
 164         } else {
 165                 dev_warn(dev->dev,
 166                         "Hardware too old to adjust SDA hold time.\n");
 167         }
 168
 169         i2c_dw_configure_fifo_master(dev);
 170         i2c_dw_release_lock(dev);
 171
 172         return 0;
 173 }
 174 EXPORT_SYMBOL_GPL(i2c_dw_init);
 175
 176 static void i2c_dw_xfer_init(struct dw_i2c_dev *dev)
 177 {
 178         struct i2c_msg *msgs = dev->msgs;
 179         u32 ic_con, ic_tar = 0;
 180
 181         /* Disable the adapter */
 182         __i2c_dw_enable_and_wait(dev, false);
 183
 184         /* If the slave address is ten bit address, enable 10BITADDR */
 185         ic_con = dw_readl(dev, DW_IC_CON);
 186         if (msgs[dev->msg_write_idx].flags & I2C_M_TEN) {
 187                 ic_con |= DW_IC_CON_10BITADDR_MASTER;
 188                 /*
 189                  * If I2C_DYNAMIC_TAR_UPDATE is set, the 10-bit addressing
 190                  * mode has to be enabled via bit 12 of IC_TAR register.
 191                  * We set it always as I2C_DYNAMIC_TAR_UPDATE can't be
 192                  * detected from registers.
 193                  */
 194                 ic_tar = DW_IC_TAR_10BITADDR_MASTER;
 195         } else {
 196                 ic_con &= ~DW_IC_CON_10BITADDR_MASTER;
 197         }
 198
 199         dw_writel(dev, ic_con, DW_IC_CON);
 200
 201         /*
 202          * Set the slave (target) address and enable 10-bit addressing mode
 203          * if applicable.
 204          */
 205         dw_writel(dev, msgs[dev->msg_write_idx].addr | ic_tar, DW_IC_TAR);
 206
 207         /* Enforce disabled interrupts (due to HW issues) */
 208         i2c_dw_disable_int(dev);
 209
 210         /* Enable the adapter */
 211         __i2c_dw_enable(dev, true);
 212
 213         /* Clear and enable interrupts */
 214         dw_readl(dev, DW_IC_CLR_INTR);
 215         dw_writel(dev, DW_IC_INTR_MASTER_MASK, DW_IC_INTR_MASK);
 216 }
 217
 218 /*
 219  * Initiate (and continue) low level master read/write transaction.
 220  * This function is only called from i2c_dw_isr, and pumping i2c_msg
 221  * messages into the tx buffer.  Even if the size of i2c_msg data is
 222  * longer than the size of the tx buffer, it handles everything.
 223  */
 224 static void
 225 i2c_dw_xfer_msg(struct dw_i2c_dev *dev)
 226 {
 227         struct i2c_msg *msgs = dev->msgs;
 228         u32 intr_mask;
 229         int tx_limit, rx_limit;
 230         u32 addr = msgs[dev->msg_write_idx].addr;
 231         u32 buf_len = dev->tx_buf_len;
 232         u8 *buf = dev->tx_buf;
 233         bool need_restart = false;
 234
 235         intr_mask = DW_IC_INTR_MASTER_MASK;
 236
 237         for (; dev->msg_write_idx < dev->msgs_num; dev->msg_write_idx++) {
 238                 u32 flags = msgs[dev->msg_write_idx].flags;
 239
 240                 /*
 241                  * If target address has changed, we need to
 242                  * reprogram the target address in the I2C
 243                  * adapter when we are done with this transfer.
 244                  */
 245                 if (msgs[dev->msg_write_idx].addr != addr) {
 246                         dev_err(dev->dev,
 247                                 "%s: invalid target address\n", __func__);
 248                         dev->msg_err = -EINVAL;
 249                         break;
 250                 }
 251
 252                 if (msgs[dev->msg_write_idx].len == 0) {
 253                         dev_err(dev->dev,
 254                                 "%s: invalid message length\n", __func__);
 255                         dev->msg_err = -EINVAL;
 256                         break;
 257                 }
 258
 259                 if (!(dev->status & STATUS_WRITE_IN_PROGRESS)) {
 260                         /* new i2c_msg */
 261                         buf = msgs[dev->msg_write_idx].buf;
 262                         buf_len = msgs[dev->msg_write_idx].len;
 263
 264                         /* If both IC_EMPTYFIFO_HOLD_MASTER_EN and
 265                          * IC_RESTART_EN are set, we must manually
 266                          * set restart bit between messages.
 267                          */
 268                         if ((dev->master_cfg & DW_IC_CON_RESTART_EN) &&
 269                                         (dev->msg_write_idx > 0))
 270                                 need_restart = true;
 271                 }
 272
 273                 tx_limit = dev->tx_fifo_depth - dw_readl(dev, DW_IC_TXFLR);
 274                 rx_limit = dev->rx_fifo_depth - dw_readl(dev, DW_IC_RXFLR);
 275
 276                 while (buf_len > 0 && tx_limit > 0 && rx_limit > 0) {
 277                         u32 cmd = 0;
 278
 279                         /*
 280                          * If IC_EMPTYFIFO_HOLD_MASTER_EN is set we must
 281                          * manually set the stop bit. However, it cannot be
 282                          * detected from the registers so we set it always
 283                          * when writing/reading the last byte.
 284                          */
 285
 286                         /*
 287                          * i2c-core always sets the buffer length of
 288                          * I2C_FUNC_SMBUS_BLOCK_DATA to 1. The length will
 289                          * be adjusted when receiving the first byte.
 290                          * Thus we can't stop the transaction here.
 291                          */
 292                         if (dev->msg_write_idx == dev->msgs_num - 1 &&
 293                             buf_len == 1 && !(flags & I2C_M_RECV_LEN))
 294                                 cmd |= BIT(9);
 295
 296                         if (need_restart) {
 297                                 cmd |= BIT(10);
 298                                 need_restart = false;
 299                         }
 300
 301                         if (msgs[dev->msg_write_idx].flags & I2C_M_RD) {
 302
 303                                 /* Avoid rx buffer overrun */
 304                                 if (dev->rx_outstanding >= dev->rx_fifo_depth)
 305                                         break;
 306
 307                                 dw_writel(dev, cmd | 0x100, DW_IC_DATA_CMD);
 308                                 rx_limit--;
 309                                 dev->rx_outstanding++;
 310                         } else
 311                                 dw_writel(dev, cmd | *buf++, DW_IC_DATA_CMD);
 312                         tx_limit--; buf_len--;
 313                 }
 314
 315                 dev->tx_buf = buf;
 316                 dev->tx_buf_len = buf_len;
 317
 318                 /*
 319                  * Because we don't know the buffer length in the
 320                  * I2C_FUNC_SMBUS_BLOCK_DATA case, we can't stop
 321                  * the transaction here.
 322                  */
 323                 if (buf_len > 0 || flags & I2C_M_RECV_LEN) {
 324                         /* more bytes to be written */
 325                         dev->status |= STATUS_WRITE_IN_PROGRESS;
 326                         break;
 327                 } else
 328                         dev->status &= ~STATUS_WRITE_IN_PROGRESS;
 329         }
 330
 331         /*
 332          * If i2c_msg index search is completed, we don't need TX_EMPTY
 333          * interrupt any more.
 334          */
 335         if (dev->msg_write_idx == dev->msgs_num)
 336                 intr_mask &= ~DW_IC_INTR_TX_EMPTY;
 337
 338         if (dev->msg_err)
 339                 intr_mask = 0;
 340
 341         dw_writel(dev, intr_mask,  DW_IC_INTR_MASK);
 342 }
 343
 344 static u8
 345 i2c_dw_recv_len(struct dw_i2c_dev *dev, u8 len)
 346 {
 347         struct i2c_msg *msgs = dev->msgs;
 348         u32 flags = msgs[dev->msg_read_idx].flags;
 349
 350         /*
 351          * Adjust the buffer length and mask the flag
 352          * after receiving the first byte.
 353          */
 354         len += (flags & I2C_CLIENT_PEC) ? 2 : 1;
 355         dev->tx_buf_len = len - min_t(u8, len, dev->rx_outstanding);
 356         msgs[dev->msg_read_idx].len = len;
 357         msgs[dev->msg_read_idx].flags &= ~I2C_M_RECV_LEN;
 358
 359         return len;
 360 }
 361
 362 static void
 363 i2c_dw_read(struct dw_i2c_dev *dev)
 364 {
 365         struct i2c_msg *msgs = dev->msgs;
 366         int rx_valid;
 367
 368         for (; dev->msg_read_idx < dev->msgs_num; dev->msg_read_idx++) {
 369                 u32 len;
 370                 u8 *buf;
 371
 372                 if (!(msgs[dev->msg_read_idx].flags & I2C_M_RD))
 373                         continue;
 374
 375                 if (!(dev->status & STATUS_READ_IN_PROGRESS)) {
 376                         len = msgs[dev->msg_read_idx].len;
 377                         buf = msgs[dev->msg_read_idx].buf;
 378                 } else {
 379                         len = dev->rx_buf_len;
 380                         buf = dev->rx_buf;
 381                 }
 382
 383                 rx_valid = dw_readl(dev, DW_IC_RXFLR);
 384
 385                 for (; len > 0 && rx_valid > 0; len--, rx_valid--) {
 386                         u32 flags = msgs[dev->msg_read_idx].flags;
 387
 388                         *buf = dw_readl(dev, DW_IC_DATA_CMD);
 389                         /* Ensure length byte is a valid value */
 390                         if (flags & I2C_M_RECV_LEN &&
 391                                 *buf <= I2C_SMBUS_BLOCK_MAX && *buf > 0) {
 392                                 len = i2c_dw_recv_len(dev, *buf);
 393                         }
 394                         buf++;
 395                         dev->rx_outstanding--;
 396                 }
 397
 398                 if (len > 0) {
 399                         dev->status |= STATUS_READ_IN_PROGRESS;
 400                         dev->rx_buf_len = len;
 401                         dev->rx_buf = buf;
 402                         return;
 403                 } else
 404                         dev->status &= ~STATUS_READ_IN_PROGRESS;
 405         }
 406 }
 407
 408 /*
 409  * Prepare controller for a transaction and call i2c_dw_xfer_msg.
 410  */
 411 static int
 412 i2c_dw_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
 413 {
 414         struct dw_i2c_dev *dev = i2c_get_adapdata(adap);
 415         int ret;
 416
 417         dev_dbg(dev->dev, "%s: msgs: %d\n", __func__, num);
 418
 419         pm_runtime_get_sync(dev->dev);
 420
 421         reinit_completion(&dev->cmd_complete);
 422         dev->msgs = msgs;
 423         dev->msgs_num = num;
 424         dev->cmd_err = 0;
 425         dev->msg_write_idx = 0;
 426         dev->msg_read_idx = 0;
 427         dev->msg_err = 0;
 428         dev->status = STATUS_IDLE;
 429         dev->abort_source = 0;
 430         dev->rx_outstanding = 0;
 431
 432         ret = i2c_dw_acquire_lock(dev);
 433         if (ret)
 434                 goto done_nolock;
 435
 436         ret = i2c_dw_wait_bus_not_busy(dev);
 437         if (ret < 0)
 438                 goto done;
 439
 440         /* Start the transfers */
 441         i2c_dw_xfer_init(dev);
 442
 443         /* Wait for tx to complete */
 444         if (!wait_for_completion_timeout(&dev->cmd_complete, adap->timeout)) {
 445                 dev_err(dev->dev, "controller timed out\n");
 446                 /* i2c_dw_init implicitly disables the adapter */
 447                 i2c_dw_init(dev);
 448                 ret = -ETIMEDOUT;
 449                 goto done;
 450         }
 451
 452         /*
 453          * We must disable the adapter before returning and signaling the end
 454          * of the current transfer. Otherwise the hardware might continue
 455          * generating interrupts which in turn causes a race condition with
 456          * the following transfer.  Needs some more investigation if the
 457          * additional interrupts are a hardware bug or this driver doesn't
 458          * handle them correctly yet.
 459          */
 460         __i2c_dw_enable(dev, false);
 461
 462         if (dev->msg_err) {
 463                 ret = dev->msg_err;
 464                 goto done;
 465         }
 466
 467         /* No error */
 468         if (likely(!dev->cmd_err && !dev->status)) {
 469                 ret = num;
 470                 goto done;
 471         }
 472
 473         /* We have an error */
 474         if (dev->cmd_err == DW_IC_ERR_TX_ABRT) {
 475                 ret = i2c_dw_handle_tx_abort(dev);
 476                 goto done;
 477         }
 478
 479         if (dev->status)
 480                 dev_err(dev->dev,
 481                         "transfer terminated early - interrupt latency too high?\n");
 482
 483         ret = -EIO;
 484
 485 done:
 486         i2c_dw_release_lock(dev);
 487
 488 done_nolock:
 489         pm_runtime_mark_last_busy(dev->dev);
 490         pm_runtime_put_autosuspend(dev->dev);
 491
 492         return ret;
 493 }
 494
 495 static const struct i2c_algorithm i2c_dw_algo = {
 496         .master_xfer = i2c_dw_xfer,
 497         .functionality = i2c_dw_func,
 498 };
 499
 500 static u32 i2c_dw_read_clear_intrbits(struct dw_i2c_dev *dev)
 501 {
 502         u32 stat;
 503
 504         /*
 505          * The IC_INTR_STAT register just indicates "enabled" interrupts.
 506          * Ths unmasked raw version of interrupt status bits are available
 507          * in the IC_RAW_INTR_STAT register.
 508          *
 509          * That is,
 510          *   stat = dw_readl(IC_INTR_STAT);
 511          * equals to,
 512          *   stat = dw_readl(IC_RAW_INTR_STAT) & dw_readl(IC_INTR_MASK);
 513          *
 514          * The raw version might be useful for debugging purposes.
 515          */
 516         stat = dw_readl(dev, DW_IC_INTR_STAT);
 517
 518         /*
 519          * Do not use the IC_CLR_INTR register to clear interrupts, or
 520          * you'll miss some interrupts, triggered during the period from
 521          * dw_readl(IC_INTR_STAT) to dw_readl(IC_CLR_INTR).
 522          *
 523          * Instead, use the separately-prepared IC_CLR_* registers.
 524          */
 525         if (stat & DW_IC_INTR_RX_UNDER)
 526                 dw_readl(dev, DW_IC_CLR_RX_UNDER);
 527         if (stat & DW_IC_INTR_RX_OVER)
 528                 dw_readl(dev, DW_IC_CLR_RX_OVER);
 529         if (stat & DW_IC_INTR_TX_OVER)
 530                 dw_readl(dev, DW_IC_CLR_TX_OVER);
 531         if (stat & DW_IC_INTR_RD_REQ)
 532                 dw_readl(dev, DW_IC_CLR_RD_REQ);
 533         if (stat & DW_IC_INTR_TX_ABRT) {
 534                 /*
 535                  * The IC_TX_ABRT_SOURCE register is cleared whenever
 536                  * the IC_CLR_TX_ABRT is read.  Preserve it beforehand.
 537                  */
 538                 dev->abort_source = dw_readl(dev, DW_IC_TX_ABRT_SOURCE);
 539                 dw_readl(dev, DW_IC_CLR_TX_ABRT);
 540         }
 541         if (stat & DW_IC_INTR_RX_DONE)
 542                 dw_readl(dev, DW_IC_CLR_RX_DONE);
 543         if (stat & DW_IC_INTR_ACTIVITY)
 544                 dw_readl(dev, DW_IC_CLR_ACTIVITY);
 545         if (stat & DW_IC_INTR_STOP_DET)
 546                 dw_readl(dev, DW_IC_CLR_STOP_DET);
 547         if (stat & DW_IC_INTR_START_DET)
 548                 dw_readl(dev, DW_IC_CLR_START_DET);
 549         if (stat & DW_IC_INTR_GEN_CALL)
 550                 dw_readl(dev, DW_IC_CLR_GEN_CALL);
 551
 552         return stat;
 553 }
 554
 555 /*
 556  * Interrupt service routine. This gets called whenever an I2C master interrupt
 557  * occurs.
 558  */
 559 static int i2c_dw_irq_handler_master(struct dw_i2c_dev *dev)
 560 {
 561         u32 stat;
 562
 563         stat = i2c_dw_read_clear_intrbits(dev);
 564         if (stat & DW_IC_INTR_TX_ABRT) {
 565                 dev->cmd_err |= DW_IC_ERR_TX_ABRT;
 566                 dev->status = STATUS_IDLE;
 567
 568                 /*
 569                  * Anytime TX_ABRT is set, the contents of the tx/rx
 570                  * buffers are flushed. Make sure to skip them.
 571                  */
 572                 dw_writel(dev, 0, DW_IC_INTR_MASK);
 573                 goto tx_aborted;
 574         }
 575
 576         if (stat & DW_IC_INTR_RX_FULL)
 577                 i2c_dw_read(dev);
 578
 579         if (stat & DW_IC_INTR_TX_EMPTY)
 580                 i2c_dw_xfer_msg(dev);
 581
 582         /*
 583          * No need to modify or disable the interrupt mask here.
 584          * i2c_dw_xfer_msg() will take care of it according to
 585          * the current transmit status.
 586          */
 587
 588 tx_aborted:
 589         if ((stat & (DW_IC_INTR_TX_ABRT | DW_IC_INTR_STOP_DET)) || dev->msg_err)
 590                 complete(&dev->cmd_complete);
 591         else if (unlikely(dev->flags & ACCESS_INTR_MASK)) {
 592                 /* Workaround to trigger pending interrupt */
 593                 stat = dw_readl(dev, DW_IC_INTR_MASK);
 594                 i2c_dw_disable_int(dev);
 595                 dw_writel(dev, stat, DW_IC_INTR_MASK);
 596         }
 597
 598         return 0;
 599 }
 600
 601 static irqreturn_t i2c_dw_isr(int this_irq, void *dev_id)
 602 {
 603         struct dw_i2c_dev *dev = dev_id;
 604         u32 stat, enabled;
 605
 606         enabled = dw_readl(dev, DW_IC_ENABLE);
 607         stat = dw_readl(dev, DW_IC_RAW_INTR_STAT);
 608         dev_dbg(dev->dev, "enabled=%#x stat=%#x\n", enabled, stat);
 609         if (!enabled || !(stat & ~DW_IC_INTR_ACTIVITY))
 610                 return IRQ_NONE;
 611
 612         i2c_dw_irq_handler_master(dev);
 613
 614         return IRQ_HANDLED;
 615 }
 616
 617 int i2c_dw_probe(struct dw_i2c_dev *dev)
 618 {
 619         struct i2c_adapter *adap = &dev->adapter;
 620         unsigned long irq_flags;
 621         int ret;
 622
 623         init_completion(&dev->cmd_complete);
 624
 625         dev->init = i2c_dw_init;
 626         dev->disable = i2c_dw_disable;
 627         dev->disable_int = i2c_dw_disable_int;
 628
 629         ret = dev->init(dev);
 630         if (ret)
 631                 return ret;
 632
 633         snprintf(adap->name, sizeof(adap->name),
 634                  "Synopsys DesignWare I2C adapter");
 635         adap->retries = 3;
 636         adap->algo = &i2c_dw_algo;
 637         adap->dev.parent = dev->dev;
 638         i2c_set_adapdata(adap, dev);
 639
 640         if (dev->pm_disabled) {
 641                 dev_pm_syscore_device(dev->dev, true);
 642                 irq_flags = IRQF_NO_SUSPEND;
 643         } else {
 644                 irq_flags = IRQF_SHARED | IRQF_COND_SUSPEND;
 645         }
 646
 647         i2c_dw_disable_int(dev);
 648         ret = devm_request_irq(dev->dev, dev->irq, i2c_dw_isr, irq_flags,
 649                                dev_name(dev->dev), dev);
 650         if (ret) {
 651                 dev_err(dev->dev, "failure requesting irq %i: %d\n",
 652                         dev->irq, ret);
 653                 return ret;
 654         }
 655
 656         /*
 657          * Increment PM usage count during adapter registration in order to
 658          * avoid possible spurious runtime suspend when adapter device is
 659          * registered to the device core and immediate resume in case bus has
 660          * registered I2C slaves that do I2C transfers in their probe.
 661          */
 662         pm_runtime_get_noresume(dev->dev);
 663         ret = i2c_add_numbered_adapter(adap);
 664         if (ret)
 665                 dev_err(dev->dev, "failure adding adapter: %d\n", ret);
 666         pm_runtime_put_noidle(dev->dev);
 667
 668         return ret;
 669 }
 670 EXPORT_SYMBOL_GPL(i2c_dw_probe);
 671
 672 MODULE_DESCRIPTION("Synopsys DesignWare I2C bus master adapter");
 673 MODULE_LICENSE("GPL");