drivers/i2c/busses/i2c-designware-pcidrv.c

   1 /*
   2  * Synopsys DesignWare I2C adapter driver (master only).
   3  *
   4  * Based on the TI DAVINCI I2C adapter driver.
   5  *
   6  * Copyright (C) 2006 Texas Instruments.
   7  * Copyright (C) 2007 MontaVista Software Inc.
   8  * Copyright (C) 2009 Provigent Ltd.
   9  * Copyright (C) 2011 Intel corporation.
  10  *
  11  * ----------------------------------------------------------------------------
  12  *
  13  * This program is free software; you can redistribute it and/or modify
  14  * it under the terms of the GNU General Public License as published by
  15  * the Free Software Foundation; either version 2 of the License, or
  16  * (at your option) any later version.
  17  *
  18  * This program is distributed in the hope that it will be useful,
  19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  21  * GNU General Public License for more details.
  22  *
  23  * You should have received a copy of the GNU General Public License
  24  * along with this program; if not, write to the Free Software
  25  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  26  * ----------------------------------------------------------------------------
  27  *
  28  */
  29
  30 #include <linux/kernel.h>
  31 #include <linux/module.h>
  32 #include <linux/delay.h>
  33 #include <linux/i2c.h>
  34 #include <linux/errno.h>
  35 #include <linux/sched.h>
  36 #include <linux/err.h>
  37 #include <linux/interrupt.h>
  38 #include <linux/io.h>
  39 #include <linux/slab.h>
  40 #include <linux/pci.h>
  41 #include <linux/pm_runtime.h>
  42 #include "i2c-designware-core.h"
  43
  44 #define DRIVER_NAME "i2c-designware-pci"
  45
  46 enum dw_pci_ctl_id_t {
  47         moorestown_0,
  48         moorestown_1,
  49         moorestown_2,
  50
  51         medfield_0,
  52         medfield_1,
  53         medfield_2,
  54         medfield_3,
  55         medfield_4,
  56         medfield_5,
  57
  58         baytrail,
  59         haswell,
  60 };
  61
  62 struct dw_scl_sda_cfg {
  63         u32 ss_hcnt;
  64         u32 fs_hcnt;
  65         u32 ss_lcnt;
  66         u32 fs_lcnt;
  67         u32 sda_hold;
  68 };
  69
  70 struct dw_pci_controller {
  71         u32 bus_num;
  72         u32 bus_cfg;
  73         u32 tx_fifo_depth;
  74         u32 rx_fifo_depth;
  75         u32 clk_khz;
  76         u32 functionality;
  77         struct dw_scl_sda_cfg *scl_sda_cfg;
  78 };
  79
  80 #define INTEL_MID_STD_CFG  (DW_IC_CON_MASTER |                  \
  81                                 DW_IC_CON_SLAVE_DISABLE |       \
  82                                 DW_IC_CON_RESTART_EN)
  83
  84 #define DW_DEFAULT_FUNCTIONALITY (I2C_FUNC_I2C |                        \
  85                                         I2C_FUNC_SMBUS_BYTE |           \
  86                                         I2C_FUNC_SMBUS_BYTE_DATA |      \
  87                                         I2C_FUNC_SMBUS_WORD_DATA |      \
  88                                         I2C_FUNC_SMBUS_I2C_BLOCK)
  89
  90 /* BayTrail HCNT/LCNT/SDA hold time */
  91 static struct dw_scl_sda_cfg byt_config = {
  92         .ss_hcnt = 0x200,
  93         .fs_hcnt = 0x55,
  94         .ss_lcnt = 0x200,
  95         .fs_lcnt = 0x99,
  96         .sda_hold = 0x6,
  97 };
  98
  99 /* Haswell HCNT/LCNT/SDA hold time */
 100 static struct dw_scl_sda_cfg hsw_config = {
 101         .ss_hcnt = 0x01b0,
 102         .fs_hcnt = 0x48,
 103         .ss_lcnt = 0x01fb,
 104         .fs_lcnt = 0xa0,
 105         .sda_hold = 0x9,
 106 };
 107
 108 static struct  dw_pci_controller  dw_pci_controllers[] = {
 109         [moorestown_0] = {
 110                 .bus_num     = 0,
 111                 .bus_cfg   = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_FAST,
 112                 .tx_fifo_depth = 32,
 113                 .rx_fifo_depth = 32,
 114                 .clk_khz      = 25000,
 115         },
 116         [moorestown_1] = {
 117                 .bus_num     = 1,
 118                 .bus_cfg   = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_FAST,
 119                 .tx_fifo_depth = 32,
 120                 .rx_fifo_depth = 32,
 121                 .clk_khz      = 25000,
 122         },
 123         [moorestown_2] = {
 124                 .bus_num     = 2,
 125                 .bus_cfg   = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_FAST,
 126                 .tx_fifo_depth = 32,
 127                 .rx_fifo_depth = 32,
 128                 .clk_khz      = 25000,
 129         },
 130         [medfield_0] = {
 131                 .bus_num     = 0,
 132                 .bus_cfg   = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_FAST,
 133                 .tx_fifo_depth = 32,
 134                 .rx_fifo_depth = 32,
 135                 .clk_khz      = 25000,
 136         },
 137         [medfield_1] = {
 138                 .bus_num     = 1,
 139                 .bus_cfg   = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_FAST,
 140                 .tx_fifo_depth = 32,
 141                 .rx_fifo_depth = 32,
 142                 .clk_khz      = 25000,
 143         },
 144         [medfield_2] = {
 145                 .bus_num     = 2,
 146                 .bus_cfg   = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_FAST,
 147                 .tx_fifo_depth = 32,
 148                 .rx_fifo_depth = 32,
 149                 .clk_khz      = 25000,
 150         },
 151         [medfield_3] = {
 152                 .bus_num     = 3,
 153                 .bus_cfg   = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_STD,
 154                 .tx_fifo_depth = 32,
 155                 .rx_fifo_depth = 32,
 156                 .clk_khz      = 25000,
 157         },
 158         [medfield_4] = {
 159                 .bus_num     = 4,
 160                 .bus_cfg   = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_FAST,
 161                 .tx_fifo_depth = 32,
 162                 .rx_fifo_depth = 32,
 163                 .clk_khz      = 25000,
 164         },
 165         [medfield_5] = {
 166                 .bus_num     = 5,
 167                 .bus_cfg   = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_FAST,
 168                 .tx_fifo_depth = 32,
 169                 .rx_fifo_depth = 32,
 170                 .clk_khz      = 25000,
 171         },
 172         [baytrail] = {
 173                 .bus_num = -1,
 174                 .bus_cfg = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_FAST,
 175                 .tx_fifo_depth = 32,
 176                 .rx_fifo_depth = 32,
 177                 .clk_khz = 100000,
 178                 .functionality = I2C_FUNC_10BIT_ADDR,
 179                 .scl_sda_cfg = &byt_config,
 180         },
 181         [haswell] = {
 182                 .bus_num = -1,
 183                 .bus_cfg = INTEL_MID_STD_CFG | DW_IC_CON_SPEED_FAST,
 184                 .tx_fifo_depth = 32,
 185                 .rx_fifo_depth = 32,
 186                 .clk_khz = 100000,
 187                 .functionality = I2C_FUNC_10BIT_ADDR,
 188                 .scl_sda_cfg = &hsw_config,
 189         },
 190 };
 191
 192 static struct i2c_algorithm i2c_dw_algo = {
 193         .master_xfer    = i2c_dw_xfer,
 194         .functionality  = i2c_dw_func,
 195 };
 196
 197 #ifdef CONFIG_PM
 198 static int i2c_dw_pci_suspend(struct device *dev)
 199 {
 200         struct pci_dev *pdev = container_of(dev, struct pci_dev, dev);
 201
 202         i2c_dw_disable(pci_get_drvdata(pdev));
 203         return 0;
 204 }
 205
 206 static int i2c_dw_pci_resume(struct device *dev)
 207 {
 208         struct pci_dev *pdev = container_of(dev, struct pci_dev, dev);
 209
 210         return i2c_dw_init(pci_get_drvdata(pdev));
 211 }
 212 #endif
 213
 214 static UNIVERSAL_DEV_PM_OPS(i2c_dw_pm_ops, i2c_dw_pci_suspend,
 215                             i2c_dw_pci_resume, NULL);
 216
 217 static u32 i2c_dw_get_clk_rate_khz(struct dw_i2c_dev *dev)
 218 {
 219         return dev->controller->clk_khz;
 220 }
 221
 222 static int i2c_dw_pci_probe(struct pci_dev *pdev,
 223                             const struct pci_device_id *id)
 224 {
 225         struct dw_i2c_dev *dev;
 226         struct i2c_adapter *adap;
 227         int r;
 228         struct  dw_pci_controller *controller;
 229         struct dw_scl_sda_cfg *cfg;
 230
 231         if (id->driver_data >= ARRAY_SIZE(dw_pci_controllers)) {
 232                 dev_err(&pdev->dev, "%s: invalid driver data %ld\n", __func__,
 233                         id->driver_data);
 234                 return -EINVAL;
 235         }
 236
 237         controller = &dw_pci_controllers[id->driver_data];
 238
 239         r = pcim_enable_device(pdev);
 240         if (r) {
 241                 dev_err(&pdev->dev, "Failed to enable I2C PCI device (%d)\n",
 242                         r);
 243                 return r;
 244         }
 245
 246         r = pcim_iomap_regions(pdev, 1 << 0, pci_name(pdev));
 247         if (r) {
 248                 dev_err(&pdev->dev, "I/O memory remapping failed\n");
 249                 return r;
 250         }
 251
 252         dev = devm_kzalloc(&pdev->dev, sizeof(struct dw_i2c_dev), GFP_KERNEL);
 253         if (!dev)
 254                 return -ENOMEM;
 255
 256         init_completion(&dev->cmd_complete);
 257         mutex_init(&dev->lock);
 258         dev->clk = NULL;
 259         dev->controller = controller;
 260         dev->get_clk_rate_khz = i2c_dw_get_clk_rate_khz;
 261         dev->base = pcim_iomap_table(pdev)[0];
 262         dev->dev = &pdev->dev;
 263         dev->functionality = controller->functionality |
 264                                 DW_DEFAULT_FUNCTIONALITY;
 265
 266         dev->master_cfg =  controller->bus_cfg;
 267         if (controller->scl_sda_cfg) {
 268                 cfg = controller->scl_sda_cfg;
 269                 dev->ss_hcnt = cfg->ss_hcnt;
 270                 dev->fs_hcnt = cfg->fs_hcnt;
 271                 dev->ss_lcnt = cfg->ss_lcnt;
 272                 dev->fs_lcnt = cfg->fs_lcnt;
 273                 dev->sda_hold_time = cfg->sda_hold;
 274         }
 275
 276         pci_set_drvdata(pdev, dev);
 277
 278         dev->tx_fifo_depth = controller->tx_fifo_depth;
 279         dev->rx_fifo_depth = controller->rx_fifo_depth;
 280         r = i2c_dw_init(dev);
 281         if (r)
 282                 return r;
 283
 284         adap = &dev->adapter;
 285         i2c_set_adapdata(adap, dev);
 286         adap->owner = THIS_MODULE;
 287         adap->class = 0;
 288         adap->algo = &i2c_dw_algo;
 289         adap->dev.parent = &pdev->dev;
 290         adap->nr = controller->bus_num;
 291
 292         snprintf(adap->name, sizeof(adap->name), "i2c-designware-pci");
 293
 294         r = devm_request_irq(&pdev->dev, pdev->irq, i2c_dw_isr, IRQF_SHARED,
 295                         adap->name, dev);
 296         if (r) {
 297                 dev_err(&pdev->dev, "failure requesting irq %i\n", dev->irq);
 298                 return r;
 299         }
 300
 301         i2c_dw_disable_int(dev);
 302         i2c_dw_clear_int(dev);
 303         r = i2c_add_numbered_adapter(adap);
 304         if (r) {
 305                 dev_err(&pdev->dev, "failure adding adapter\n");
 306                 return r;
 307         }
 308
 309         pm_runtime_set_autosuspend_delay(&pdev->dev, 1000);
 310         pm_runtime_use_autosuspend(&pdev->dev);
 311         pm_runtime_put_autosuspend(&pdev->dev);
 312         pm_runtime_allow(&pdev->dev);
 313
 314         return 0;
 315 }
 316
 317 static void i2c_dw_pci_remove(struct pci_dev *pdev)
 318 {
 319         struct dw_i2c_dev *dev = pci_get_drvdata(pdev);
 320
 321         i2c_dw_disable(dev);
 322         pm_runtime_forbid(&pdev->dev);
 323         pm_runtime_get_noresume(&pdev->dev);
 324
 325         i2c_del_adapter(&dev->adapter);
 326 }
 327
 328 /* work with hotplug and coldplug */
 329 MODULE_ALIAS("i2c_designware-pci");
 330
 331 static const struct pci_device_id i2_designware_pci_ids[] = {
 332         /* Moorestown */
 333         { PCI_VDEVICE(INTEL, 0x0802), moorestown_0 },
 334         { PCI_VDEVICE(INTEL, 0x0803), moorestown_1 },
 335         { PCI_VDEVICE(INTEL, 0x0804), moorestown_2 },
 336         /* Medfield */
 337         { PCI_VDEVICE(INTEL, 0x0817), medfield_3,},
 338         { PCI_VDEVICE(INTEL, 0x0818), medfield_4 },
 339         { PCI_VDEVICE(INTEL, 0x0819), medfield_5 },
 340         { PCI_VDEVICE(INTEL, 0x082C), medfield_0 },
 341         { PCI_VDEVICE(INTEL, 0x082D), medfield_1 },
 342         { PCI_VDEVICE(INTEL, 0x082E), medfield_2 },
 343         /* Baytrail */
 344         { PCI_VDEVICE(INTEL, 0x0F41), baytrail },
 345         { PCI_VDEVICE(INTEL, 0x0F42), baytrail },
 346         { PCI_VDEVICE(INTEL, 0x0F43), baytrail },
 347         { PCI_VDEVICE(INTEL, 0x0F44), baytrail },
 348         { PCI_VDEVICE(INTEL, 0x0F45), baytrail },
 349         { PCI_VDEVICE(INTEL, 0x0F46), baytrail },
 350         { PCI_VDEVICE(INTEL, 0x0F47), baytrail },
 351         /* Haswell */
 352         { PCI_VDEVICE(INTEL, 0x9c61), haswell },
 353         { PCI_VDEVICE(INTEL, 0x9c62), haswell },
 354         /* Braswell / Cherrytrail */
 355         { PCI_VDEVICE(INTEL, 0x22C1), baytrail,},
 356         { PCI_VDEVICE(INTEL, 0x22C2), baytrail },
 357         { PCI_VDEVICE(INTEL, 0x22C3), baytrail },
 358         { PCI_VDEVICE(INTEL, 0x22C4), baytrail },
 359         { PCI_VDEVICE(INTEL, 0x22C5), baytrail },
 360         { PCI_VDEVICE(INTEL, 0x22C6), baytrail },
 361         { PCI_VDEVICE(INTEL, 0x22C7), baytrail },
 362         { 0,}
 363 };
 364 MODULE_DEVICE_TABLE(pci, i2_designware_pci_ids);
 365
 366 static struct pci_driver dw_i2c_driver = {
 367         .name           = DRIVER_NAME,
 368         .id_table       = i2_designware_pci_ids,
 369         .probe          = i2c_dw_pci_probe,
 370         .remove         = i2c_dw_pci_remove,
 371         .driver         = {
 372                 .pm     = &i2c_dw_pm_ops,
 373         },
 374 };
 375
 376 module_pci_driver(dw_i2c_driver);
 377
 378 MODULE_AUTHOR("Baruch Siach <baruch@tkos.co.il>");
 379 MODULE_DESCRIPTION("Synopsys DesignWare PCI I2C bus adapter");
 380 MODULE_LICENSE("GPL");