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ASoC: rockchip: add bindings for rk3368 i2s
[mirror_ubuntu-bionic-kernel.git] / drivers / i2c / busses / i2c-exynos5.c
1 /**
2 * i2c-exynos5.c - Samsung Exynos5 I2C Controller Driver
3 *
4 * Copyright (C) 2013 Samsung Electronics Co., Ltd.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11 #include <linux/kernel.h>
12 #include <linux/module.h>
13
14 #include <linux/i2c.h>
15 #include <linux/time.h>
16 #include <linux/interrupt.h>
17 #include <linux/delay.h>
18 #include <linux/errno.h>
19 #include <linux/err.h>
20 #include <linux/platform_device.h>
21 #include <linux/clk.h>
22 #include <linux/slab.h>
23 #include <linux/io.h>
24 #include <linux/of_address.h>
25 #include <linux/of_irq.h>
26 #include <linux/spinlock.h>
27
28 /*
29 * HSI2C controller from Samsung supports 2 modes of operation
30 * 1. Auto mode: Where in master automatically controls the whole transaction
31 * 2. Manual mode: Software controls the transaction by issuing commands
32 * START, READ, WRITE, STOP, RESTART in I2C_MANUAL_CMD register.
33 *
34 * Operation mode can be selected by setting AUTO_MODE bit in I2C_CONF register
35 *
36 * Special bits are available for both modes of operation to set commands
37 * and for checking transfer status
38 */
39
40 /* Register Map */
41 #define HSI2C_CTL 0x00
42 #define HSI2C_FIFO_CTL 0x04
43 #define HSI2C_TRAILIG_CTL 0x08
44 #define HSI2C_CLK_CTL 0x0C
45 #define HSI2C_CLK_SLOT 0x10
46 #define HSI2C_INT_ENABLE 0x20
47 #define HSI2C_INT_STATUS 0x24
48 #define HSI2C_ERR_STATUS 0x2C
49 #define HSI2C_FIFO_STATUS 0x30
50 #define HSI2C_TX_DATA 0x34
51 #define HSI2C_RX_DATA 0x38
52 #define HSI2C_CONF 0x40
53 #define HSI2C_AUTO_CONF 0x44
54 #define HSI2C_TIMEOUT 0x48
55 #define HSI2C_MANUAL_CMD 0x4C
56 #define HSI2C_TRANS_STATUS 0x50
57 #define HSI2C_TIMING_HS1 0x54
58 #define HSI2C_TIMING_HS2 0x58
59 #define HSI2C_TIMING_HS3 0x5C
60 #define HSI2C_TIMING_FS1 0x60
61 #define HSI2C_TIMING_FS2 0x64
62 #define HSI2C_TIMING_FS3 0x68
63 #define HSI2C_TIMING_SLA 0x6C
64 #define HSI2C_ADDR 0x70
65
66 /* I2C_CTL Register bits */
67 #define HSI2C_FUNC_MODE_I2C (1u << 0)
68 #define HSI2C_MASTER (1u << 3)
69 #define HSI2C_RXCHON (1u << 6)
70 #define HSI2C_TXCHON (1u << 7)
71 #define HSI2C_SW_RST (1u << 31)
72
73 /* I2C_FIFO_CTL Register bits */
74 #define HSI2C_RXFIFO_EN (1u << 0)
75 #define HSI2C_TXFIFO_EN (1u << 1)
76 #define HSI2C_RXFIFO_TRIGGER_LEVEL(x) ((x) << 4)
77 #define HSI2C_TXFIFO_TRIGGER_LEVEL(x) ((x) << 16)
78
79 /* I2C_TRAILING_CTL Register bits */
80 #define HSI2C_TRAILING_COUNT (0xf)
81
82 /* I2C_INT_EN Register bits */
83 #define HSI2C_INT_TX_ALMOSTEMPTY_EN (1u << 0)
84 #define HSI2C_INT_RX_ALMOSTFULL_EN (1u << 1)
85 #define HSI2C_INT_TRAILING_EN (1u << 6)
86
87 /* I2C_INT_STAT Register bits */
88 #define HSI2C_INT_TX_ALMOSTEMPTY (1u << 0)
89 #define HSI2C_INT_RX_ALMOSTFULL (1u << 1)
90 #define HSI2C_INT_TX_UNDERRUN (1u << 2)
91 #define HSI2C_INT_TX_OVERRUN (1u << 3)
92 #define HSI2C_INT_RX_UNDERRUN (1u << 4)
93 #define HSI2C_INT_RX_OVERRUN (1u << 5)
94 #define HSI2C_INT_TRAILING (1u << 6)
95 #define HSI2C_INT_I2C (1u << 9)
96
97 #define HSI2C_INT_TRANS_DONE (1u << 7)
98 #define HSI2C_INT_TRANS_ABORT (1u << 8)
99 #define HSI2C_INT_NO_DEV_ACK (1u << 9)
100 #define HSI2C_INT_NO_DEV (1u << 10)
101 #define HSI2C_INT_TIMEOUT (1u << 11)
102 #define HSI2C_INT_I2C_TRANS (HSI2C_INT_TRANS_DONE | \
103 HSI2C_INT_TRANS_ABORT | \
104 HSI2C_INT_NO_DEV_ACK | \
105 HSI2C_INT_NO_DEV | \
106 HSI2C_INT_TIMEOUT)
107
108 /* I2C_FIFO_STAT Register bits */
109 #define HSI2C_RX_FIFO_EMPTY (1u << 24)
110 #define HSI2C_RX_FIFO_FULL (1u << 23)
111 #define HSI2C_RX_FIFO_LVL(x) ((x >> 16) & 0x7f)
112 #define HSI2C_TX_FIFO_EMPTY (1u << 8)
113 #define HSI2C_TX_FIFO_FULL (1u << 7)
114 #define HSI2C_TX_FIFO_LVL(x) ((x >> 0) & 0x7f)
115
116 /* I2C_CONF Register bits */
117 #define HSI2C_AUTO_MODE (1u << 31)
118 #define HSI2C_10BIT_ADDR_MODE (1u << 30)
119 #define HSI2C_HS_MODE (1u << 29)
120
121 /* I2C_AUTO_CONF Register bits */
122 #define HSI2C_READ_WRITE (1u << 16)
123 #define HSI2C_STOP_AFTER_TRANS (1u << 17)
124 #define HSI2C_MASTER_RUN (1u << 31)
125
126 /* I2C_TIMEOUT Register bits */
127 #define HSI2C_TIMEOUT_EN (1u << 31)
128 #define HSI2C_TIMEOUT_MASK 0xff
129
130 /* I2C_TRANS_STATUS register bits */
131 #define HSI2C_MASTER_BUSY (1u << 17)
132 #define HSI2C_SLAVE_BUSY (1u << 16)
133
134 /* I2C_TRANS_STATUS register bits for Exynos5 variant */
135 #define HSI2C_TIMEOUT_AUTO (1u << 4)
136 #define HSI2C_NO_DEV (1u << 3)
137 #define HSI2C_NO_DEV_ACK (1u << 2)
138 #define HSI2C_TRANS_ABORT (1u << 1)
139 #define HSI2C_TRANS_DONE (1u << 0)
140
141 /* I2C_TRANS_STATUS register bits for Exynos7 variant */
142 #define HSI2C_MASTER_ST_MASK 0xf
143 #define HSI2C_MASTER_ST_IDLE 0x0
144 #define HSI2C_MASTER_ST_START 0x1
145 #define HSI2C_MASTER_ST_RESTART 0x2
146 #define HSI2C_MASTER_ST_STOP 0x3
147 #define HSI2C_MASTER_ST_MASTER_ID 0x4
148 #define HSI2C_MASTER_ST_ADDR0 0x5
149 #define HSI2C_MASTER_ST_ADDR1 0x6
150 #define HSI2C_MASTER_ST_ADDR2 0x7
151 #define HSI2C_MASTER_ST_ADDR_SR 0x8
152 #define HSI2C_MASTER_ST_READ 0x9
153 #define HSI2C_MASTER_ST_WRITE 0xa
154 #define HSI2C_MASTER_ST_NO_ACK 0xb
155 #define HSI2C_MASTER_ST_LOSE 0xc
156 #define HSI2C_MASTER_ST_WAIT 0xd
157 #define HSI2C_MASTER_ST_WAIT_CMD 0xe
158
159 /* I2C_ADDR register bits */
160 #define HSI2C_SLV_ADDR_SLV(x) ((x & 0x3ff) << 0)
161 #define HSI2C_SLV_ADDR_MAS(x) ((x & 0x3ff) << 10)
162 #define HSI2C_MASTER_ID(x) ((x & 0xff) << 24)
163 #define MASTER_ID(x) ((x & 0x7) + 0x08)
164
165 /*
166 * Controller operating frequency, timing values for operation
167 * are calculated against this frequency
168 */
169 #define HSI2C_HS_TX_CLOCK 1000000
170 #define HSI2C_FS_TX_CLOCK 100000
171 #define HSI2C_HIGH_SPD 1
172 #define HSI2C_FAST_SPD 0
173
174 #define EXYNOS5_I2C_TIMEOUT (msecs_to_jiffies(1000))
175
176 #define HSI2C_EXYNOS7 BIT(0)
177
178 struct exynos5_i2c {
179 struct i2c_adapter adap;
180 unsigned int suspended:1;
181
182 struct i2c_msg *msg;
183 struct completion msg_complete;
184 unsigned int msg_ptr;
185
186 unsigned int irq;
187
188 void __iomem *regs;
189 struct clk *clk;
190 struct device *dev;
191 int state;
192
193 spinlock_t lock; /* IRQ synchronization */
194
195 /*
196 * Since the TRANS_DONE bit is cleared on read, and we may read it
197 * either during an IRQ or after a transaction, keep track of its
198 * state here.
199 */
200 int trans_done;
201
202 /* Controller operating frequency */
203 unsigned int fs_clock;
204 unsigned int hs_clock;
205
206 /*
207 * HSI2C Controller can operate in
208 * 1. High speed upto 3.4Mbps
209 * 2. Fast speed upto 1Mbps
210 */
211 int speed_mode;
212
213 /* Version of HS-I2C Hardware */
214 struct exynos_hsi2c_variant *variant;
215 };
216
217 /**
218 * struct exynos_hsi2c_variant - platform specific HSI2C driver data
219 * @fifo_depth: the fifo depth supported by the HSI2C module
220 *
221 * Specifies platform specific configuration of HSI2C module.
222 * Note: A structure for driver specific platform data is used for future
223 * expansion of its usage.
224 */
225 struct exynos_hsi2c_variant {
226 unsigned int fifo_depth;
227 unsigned int hw;
228 };
229
230 static const struct exynos_hsi2c_variant exynos5250_hsi2c_data = {
231 .fifo_depth = 64,
232 };
233
234 static const struct exynos_hsi2c_variant exynos5260_hsi2c_data = {
235 .fifo_depth = 16,
236 };
237
238 static const struct exynos_hsi2c_variant exynos7_hsi2c_data = {
239 .fifo_depth = 16,
240 .hw = HSI2C_EXYNOS7,
241 };
242
243 static const struct of_device_id exynos5_i2c_match[] = {
244 {
245 .compatible = "samsung,exynos5-hsi2c",
246 .data = &exynos5250_hsi2c_data
247 }, {
248 .compatible = "samsung,exynos5250-hsi2c",
249 .data = &exynos5250_hsi2c_data
250 }, {
251 .compatible = "samsung,exynos5260-hsi2c",
252 .data = &exynos5260_hsi2c_data
253 }, {
254 .compatible = "samsung,exynos7-hsi2c",
255 .data = &exynos7_hsi2c_data
256 }, {},
257 };
258 MODULE_DEVICE_TABLE(of, exynos5_i2c_match);
259
260 static inline struct exynos_hsi2c_variant *exynos5_i2c_get_variant
261 (struct platform_device *pdev)
262 {
263 const struct of_device_id *match;
264
265 match = of_match_node(exynos5_i2c_match, pdev->dev.of_node);
266 return (struct exynos_hsi2c_variant *)match->data;
267 }
268
269 static void exynos5_i2c_clr_pend_irq(struct exynos5_i2c *i2c)
270 {
271 writel(readl(i2c->regs + HSI2C_INT_STATUS),
272 i2c->regs + HSI2C_INT_STATUS);
273 }
274
275 /*
276 * exynos5_i2c_set_timing: updates the registers with appropriate
277 * timing values calculated
278 *
279 * Returns 0 on success, -EINVAL if the cycle length cannot
280 * be calculated.
281 */
282 static int exynos5_i2c_set_timing(struct exynos5_i2c *i2c, int mode)
283 {
284 u32 i2c_timing_s1;
285 u32 i2c_timing_s2;
286 u32 i2c_timing_s3;
287 u32 i2c_timing_sla;
288 unsigned int t_start_su, t_start_hd;
289 unsigned int t_stop_su;
290 unsigned int t_data_su, t_data_hd;
291 unsigned int t_scl_l, t_scl_h;
292 unsigned int t_sr_release;
293 unsigned int t_ftl_cycle;
294 unsigned int clkin = clk_get_rate(i2c->clk);
295 unsigned int div, utemp0 = 0, utemp1 = 0, clk_cycle;
296 unsigned int op_clk = (mode == HSI2C_HIGH_SPD) ?
297 i2c->hs_clock : i2c->fs_clock;
298
299 /*
300 * In case of HSI2C controller in Exynos5 series
301 * FPCLK / FI2C =
302 * (CLK_DIV + 1) * (TSCLK_L + TSCLK_H + 2) + 8 + 2 * FLT_CYCLE
303 *
304 * In case of HSI2C controllers in Exynos7 series
305 * FPCLK / FI2C =
306 * (CLK_DIV + 1) * (TSCLK_L + TSCLK_H + 2) + 8 + FLT_CYCLE
307 *
308 * utemp0 = (CLK_DIV + 1) * (TSCLK_L + TSCLK_H + 2)
309 * utemp1 = (TSCLK_L + TSCLK_H + 2)
310 */
311 t_ftl_cycle = (readl(i2c->regs + HSI2C_CONF) >> 16) & 0x7;
312 utemp0 = (clkin / op_clk) - 8;
313
314 if (i2c->variant->hw == HSI2C_EXYNOS7)
315 utemp0 -= t_ftl_cycle;
316 else
317 utemp0 -= 2 * t_ftl_cycle;
318
319 /* CLK_DIV max is 256 */
320 for (div = 0; div < 256; div++) {
321 utemp1 = utemp0 / (div + 1);
322
323 /*
324 * SCL_L and SCL_H each has max value of 255
325 * Hence, For the clk_cycle to the have right value
326 * utemp1 has to be less then 512 and more than 4.
327 */
328 if ((utemp1 < 512) && (utemp1 > 4)) {
329 clk_cycle = utemp1 - 2;
330 break;
331 } else if (div == 255) {
332 dev_warn(i2c->dev, "Failed to calculate divisor");
333 return -EINVAL;
334 }
335 }
336
337 t_scl_l = clk_cycle / 2;
338 t_scl_h = clk_cycle / 2;
339 t_start_su = t_scl_l;
340 t_start_hd = t_scl_l;
341 t_stop_su = t_scl_l;
342 t_data_su = t_scl_l / 2;
343 t_data_hd = t_scl_l / 2;
344 t_sr_release = clk_cycle;
345
346 i2c_timing_s1 = t_start_su << 24 | t_start_hd << 16 | t_stop_su << 8;
347 i2c_timing_s2 = t_data_su << 24 | t_scl_l << 8 | t_scl_h << 0;
348 i2c_timing_s3 = div << 16 | t_sr_release << 0;
349 i2c_timing_sla = t_data_hd << 0;
350
351 dev_dbg(i2c->dev, "tSTART_SU: %X, tSTART_HD: %X, tSTOP_SU: %X\n",
352 t_start_su, t_start_hd, t_stop_su);
353 dev_dbg(i2c->dev, "tDATA_SU: %X, tSCL_L: %X, tSCL_H: %X\n",
354 t_data_su, t_scl_l, t_scl_h);
355 dev_dbg(i2c->dev, "nClkDiv: %X, tSR_RELEASE: %X\n",
356 div, t_sr_release);
357 dev_dbg(i2c->dev, "tDATA_HD: %X\n", t_data_hd);
358
359 if (mode == HSI2C_HIGH_SPD) {
360 writel(i2c_timing_s1, i2c->regs + HSI2C_TIMING_HS1);
361 writel(i2c_timing_s2, i2c->regs + HSI2C_TIMING_HS2);
362 writel(i2c_timing_s3, i2c->regs + HSI2C_TIMING_HS3);
363 } else {
364 writel(i2c_timing_s1, i2c->regs + HSI2C_TIMING_FS1);
365 writel(i2c_timing_s2, i2c->regs + HSI2C_TIMING_FS2);
366 writel(i2c_timing_s3, i2c->regs + HSI2C_TIMING_FS3);
367 }
368 writel(i2c_timing_sla, i2c->regs + HSI2C_TIMING_SLA);
369
370 return 0;
371 }
372
373 static int exynos5_hsi2c_clock_setup(struct exynos5_i2c *i2c)
374 {
375 /*
376 * Configure the Fast speed timing values
377 * Even the High Speed mode initially starts with Fast mode
378 */
379 if (exynos5_i2c_set_timing(i2c, HSI2C_FAST_SPD)) {
380 dev_err(i2c->dev, "HSI2C FS Clock set up failed\n");
381 return -EINVAL;
382 }
383
384 /* configure the High speed timing values */
385 if (i2c->speed_mode == HSI2C_HIGH_SPD) {
386 if (exynos5_i2c_set_timing(i2c, HSI2C_HIGH_SPD)) {
387 dev_err(i2c->dev, "HSI2C HS Clock set up failed\n");
388 return -EINVAL;
389 }
390 }
391
392 return 0;
393 }
394
395 /*
396 * exynos5_i2c_init: configures the controller for I2C functionality
397 * Programs I2C controller for Master mode operation
398 */
399 static void exynos5_i2c_init(struct exynos5_i2c *i2c)
400 {
401 u32 i2c_conf = readl(i2c->regs + HSI2C_CONF);
402 u32 i2c_timeout = readl(i2c->regs + HSI2C_TIMEOUT);
403
404 /* Clear to disable Timeout */
405 i2c_timeout &= ~HSI2C_TIMEOUT_EN;
406 writel(i2c_timeout, i2c->regs + HSI2C_TIMEOUT);
407
408 writel((HSI2C_FUNC_MODE_I2C | HSI2C_MASTER),
409 i2c->regs + HSI2C_CTL);
410 writel(HSI2C_TRAILING_COUNT, i2c->regs + HSI2C_TRAILIG_CTL);
411
412 if (i2c->speed_mode == HSI2C_HIGH_SPD) {
413 writel(HSI2C_MASTER_ID(MASTER_ID(i2c->adap.nr)),
414 i2c->regs + HSI2C_ADDR);
415 i2c_conf |= HSI2C_HS_MODE;
416 }
417
418 writel(i2c_conf | HSI2C_AUTO_MODE, i2c->regs + HSI2C_CONF);
419 }
420
421 static void exynos5_i2c_reset(struct exynos5_i2c *i2c)
422 {
423 u32 i2c_ctl;
424
425 /* Set and clear the bit for reset */
426 i2c_ctl = readl(i2c->regs + HSI2C_CTL);
427 i2c_ctl |= HSI2C_SW_RST;
428 writel(i2c_ctl, i2c->regs + HSI2C_CTL);
429
430 i2c_ctl = readl(i2c->regs + HSI2C_CTL);
431 i2c_ctl &= ~HSI2C_SW_RST;
432 writel(i2c_ctl, i2c->regs + HSI2C_CTL);
433
434 /* We don't expect calculations to fail during the run */
435 exynos5_hsi2c_clock_setup(i2c);
436 /* Initialize the configure registers */
437 exynos5_i2c_init(i2c);
438 }
439
440 /*
441 * exynos5_i2c_irq: top level IRQ servicing routine
442 *
443 * INT_STATUS registers gives the interrupt details. Further,
444 * FIFO_STATUS or TRANS_STATUS registers are to be check for detailed
445 * state of the bus.
446 */
447 static irqreturn_t exynos5_i2c_irq(int irqno, void *dev_id)
448 {
449 struct exynos5_i2c *i2c = dev_id;
450 u32 fifo_level, int_status, fifo_status, trans_status;
451 unsigned char byte;
452 int len = 0;
453
454 i2c->state = -EINVAL;
455
456 spin_lock(&i2c->lock);
457
458 int_status = readl(i2c->regs + HSI2C_INT_STATUS);
459 writel(int_status, i2c->regs + HSI2C_INT_STATUS);
460 trans_status = readl(i2c->regs + HSI2C_TRANS_STATUS);
461
462 /* handle interrupt related to the transfer status */
463 if (i2c->variant->hw == HSI2C_EXYNOS7) {
464 if (int_status & HSI2C_INT_TRANS_DONE) {
465 i2c->trans_done = 1;
466 i2c->state = 0;
467 } else if (int_status & HSI2C_INT_TRANS_ABORT) {
468 dev_dbg(i2c->dev, "Deal with arbitration lose\n");
469 i2c->state = -EAGAIN;
470 goto stop;
471 } else if (int_status & HSI2C_INT_NO_DEV_ACK) {
472 dev_dbg(i2c->dev, "No ACK from device\n");
473 i2c->state = -ENXIO;
474 goto stop;
475 } else if (int_status & HSI2C_INT_NO_DEV) {
476 dev_dbg(i2c->dev, "No device\n");
477 i2c->state = -ENXIO;
478 goto stop;
479 } else if (int_status & HSI2C_INT_TIMEOUT) {
480 dev_dbg(i2c->dev, "Accessing device timed out\n");
481 i2c->state = -ETIMEDOUT;
482 goto stop;
483 }
484
485 if ((trans_status & HSI2C_MASTER_ST_MASK) == HSI2C_MASTER_ST_LOSE) {
486 i2c->state = -EAGAIN;
487 goto stop;
488 }
489 } else if (int_status & HSI2C_INT_I2C) {
490 if (trans_status & HSI2C_NO_DEV_ACK) {
491 dev_dbg(i2c->dev, "No ACK from device\n");
492 i2c->state = -ENXIO;
493 goto stop;
494 } else if (trans_status & HSI2C_NO_DEV) {
495 dev_dbg(i2c->dev, "No device\n");
496 i2c->state = -ENXIO;
497 goto stop;
498 } else if (trans_status & HSI2C_TRANS_ABORT) {
499 dev_dbg(i2c->dev, "Deal with arbitration lose\n");
500 i2c->state = -EAGAIN;
501 goto stop;
502 } else if (trans_status & HSI2C_TIMEOUT_AUTO) {
503 dev_dbg(i2c->dev, "Accessing device timed out\n");
504 i2c->state = -ETIMEDOUT;
505 goto stop;
506 } else if (trans_status & HSI2C_TRANS_DONE) {
507 i2c->trans_done = 1;
508 i2c->state = 0;
509 }
510 }
511
512 if ((i2c->msg->flags & I2C_M_RD) && (int_status &
513 (HSI2C_INT_TRAILING | HSI2C_INT_RX_ALMOSTFULL))) {
514 fifo_status = readl(i2c->regs + HSI2C_FIFO_STATUS);
515 fifo_level = HSI2C_RX_FIFO_LVL(fifo_status);
516 len = min(fifo_level, i2c->msg->len - i2c->msg_ptr);
517
518 while (len > 0) {
519 byte = (unsigned char)
520 readl(i2c->regs + HSI2C_RX_DATA);
521 i2c->msg->buf[i2c->msg_ptr++] = byte;
522 len--;
523 }
524 i2c->state = 0;
525 } else if (int_status & HSI2C_INT_TX_ALMOSTEMPTY) {
526 fifo_status = readl(i2c->regs + HSI2C_FIFO_STATUS);
527 fifo_level = HSI2C_TX_FIFO_LVL(fifo_status);
528
529 len = i2c->variant->fifo_depth - fifo_level;
530 if (len > (i2c->msg->len - i2c->msg_ptr)) {
531 u32 int_en = readl(i2c->regs + HSI2C_INT_ENABLE);
532
533 int_en &= ~HSI2C_INT_TX_ALMOSTEMPTY_EN;
534 writel(int_en, i2c->regs + HSI2C_INT_ENABLE);
535 len = i2c->msg->len - i2c->msg_ptr;
536 }
537
538 while (len > 0) {
539 byte = i2c->msg->buf[i2c->msg_ptr++];
540 writel(byte, i2c->regs + HSI2C_TX_DATA);
541 len--;
542 }
543 i2c->state = 0;
544 }
545
546 stop:
547 if ((i2c->trans_done && (i2c->msg->len == i2c->msg_ptr)) ||
548 (i2c->state < 0)) {
549 writel(0, i2c->regs + HSI2C_INT_ENABLE);
550 exynos5_i2c_clr_pend_irq(i2c);
551 complete(&i2c->msg_complete);
552 }
553
554 spin_unlock(&i2c->lock);
555
556 return IRQ_HANDLED;
557 }
558
559 /*
560 * exynos5_i2c_wait_bus_idle
561 *
562 * Wait for the bus to go idle, indicated by the MASTER_BUSY bit being
563 * cleared.
564 *
565 * Returns -EBUSY if the bus cannot be bought to idle
566 */
567 static int exynos5_i2c_wait_bus_idle(struct exynos5_i2c *i2c)
568 {
569 unsigned long stop_time;
570 u32 trans_status;
571
572 /* wait for 100 milli seconds for the bus to be idle */
573 stop_time = jiffies + msecs_to_jiffies(100) + 1;
574 do {
575 trans_status = readl(i2c->regs + HSI2C_TRANS_STATUS);
576 if (!(trans_status & HSI2C_MASTER_BUSY))
577 return 0;
578
579 usleep_range(50, 200);
580 } while (time_before(jiffies, stop_time));
581
582 return -EBUSY;
583 }
584
585 /*
586 * exynos5_i2c_message_start: Configures the bus and starts the xfer
587 * i2c: struct exynos5_i2c pointer for the current bus
588 * stop: Enables stop after transfer if set. Set for last transfer of
589 * in the list of messages.
590 *
591 * Configures the bus for read/write function
592 * Sets chip address to talk to, message length to be sent.
593 * Enables appropriate interrupts and sends start xfer command.
594 */
595 static void exynos5_i2c_message_start(struct exynos5_i2c *i2c, int stop)
596 {
597 u32 i2c_ctl;
598 u32 int_en = 0;
599 u32 i2c_auto_conf = 0;
600 u32 fifo_ctl;
601 unsigned long flags;
602 unsigned short trig_lvl;
603
604 if (i2c->variant->hw == HSI2C_EXYNOS7)
605 int_en |= HSI2C_INT_I2C_TRANS;
606 else
607 int_en |= HSI2C_INT_I2C;
608
609 i2c_ctl = readl(i2c->regs + HSI2C_CTL);
610 i2c_ctl &= ~(HSI2C_TXCHON | HSI2C_RXCHON);
611 fifo_ctl = HSI2C_RXFIFO_EN | HSI2C_TXFIFO_EN;
612
613 if (i2c->msg->flags & I2C_M_RD) {
614 i2c_ctl |= HSI2C_RXCHON;
615
616 i2c_auto_conf |= HSI2C_READ_WRITE;
617
618 trig_lvl = (i2c->msg->len > i2c->variant->fifo_depth) ?
619 (i2c->variant->fifo_depth * 3 / 4) : i2c->msg->len;
620 fifo_ctl |= HSI2C_RXFIFO_TRIGGER_LEVEL(trig_lvl);
621
622 int_en |= (HSI2C_INT_RX_ALMOSTFULL_EN |
623 HSI2C_INT_TRAILING_EN);
624 } else {
625 i2c_ctl |= HSI2C_TXCHON;
626
627 trig_lvl = (i2c->msg->len > i2c->variant->fifo_depth) ?
628 (i2c->variant->fifo_depth * 1 / 4) : i2c->msg->len;
629 fifo_ctl |= HSI2C_TXFIFO_TRIGGER_LEVEL(trig_lvl);
630
631 int_en |= HSI2C_INT_TX_ALMOSTEMPTY_EN;
632 }
633
634 writel(HSI2C_SLV_ADDR_MAS(i2c->msg->addr), i2c->regs + HSI2C_ADDR);
635
636 writel(fifo_ctl, i2c->regs + HSI2C_FIFO_CTL);
637 writel(i2c_ctl, i2c->regs + HSI2C_CTL);
638
639 /*
640 * Enable interrupts before starting the transfer so that we don't
641 * miss any INT_I2C interrupts.
642 */
643 spin_lock_irqsave(&i2c->lock, flags);
644 writel(int_en, i2c->regs + HSI2C_INT_ENABLE);
645
646 if (stop == 1)
647 i2c_auto_conf |= HSI2C_STOP_AFTER_TRANS;
648 i2c_auto_conf |= i2c->msg->len;
649 i2c_auto_conf |= HSI2C_MASTER_RUN;
650 writel(i2c_auto_conf, i2c->regs + HSI2C_AUTO_CONF);
651 spin_unlock_irqrestore(&i2c->lock, flags);
652 }
653
654 static int exynos5_i2c_xfer_msg(struct exynos5_i2c *i2c,
655 struct i2c_msg *msgs, int stop)
656 {
657 unsigned long timeout;
658 int ret;
659
660 i2c->msg = msgs;
661 i2c->msg_ptr = 0;
662 i2c->trans_done = 0;
663
664 reinit_completion(&i2c->msg_complete);
665
666 exynos5_i2c_message_start(i2c, stop);
667
668 timeout = wait_for_completion_timeout(&i2c->msg_complete,
669 EXYNOS5_I2C_TIMEOUT);
670 if (timeout == 0)
671 ret = -ETIMEDOUT;
672 else
673 ret = i2c->state;
674
675 /*
676 * If this is the last message to be transfered (stop == 1)
677 * Then check if the bus can be brought back to idle.
678 */
679 if (ret == 0 && stop)
680 ret = exynos5_i2c_wait_bus_idle(i2c);
681
682 if (ret < 0) {
683 exynos5_i2c_reset(i2c);
684 if (ret == -ETIMEDOUT)
685 dev_warn(i2c->dev, "%s timeout\n",
686 (msgs->flags & I2C_M_RD) ? "rx" : "tx");
687 }
688
689 /* Return the state as in interrupt routine */
690 return ret;
691 }
692
693 static int exynos5_i2c_xfer(struct i2c_adapter *adap,
694 struct i2c_msg *msgs, int num)
695 {
696 struct exynos5_i2c *i2c = adap->algo_data;
697 int i = 0, ret = 0, stop = 0;
698
699 if (i2c->suspended) {
700 dev_err(i2c->dev, "HS-I2C is not initialized.\n");
701 return -EIO;
702 }
703
704 ret = clk_enable(i2c->clk);
705 if (ret)
706 return ret;
707
708 for (i = 0; i < num; i++, msgs++) {
709 stop = (i == num - 1);
710
711 ret = exynos5_i2c_xfer_msg(i2c, msgs, stop);
712
713 if (ret < 0)
714 goto out;
715 }
716
717 if (i == num) {
718 ret = num;
719 } else {
720 /* Only one message, cannot access the device */
721 if (i == 1)
722 ret = -EREMOTEIO;
723 else
724 ret = i;
725
726 dev_warn(i2c->dev, "xfer message failed\n");
727 }
728
729 out:
730 clk_disable(i2c->clk);
731 return ret;
732 }
733
734 static u32 exynos5_i2c_func(struct i2c_adapter *adap)
735 {
736 return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK);
737 }
738
739 static const struct i2c_algorithm exynos5_i2c_algorithm = {
740 .master_xfer = exynos5_i2c_xfer,
741 .functionality = exynos5_i2c_func,
742 };
743
744 static int exynos5_i2c_probe(struct platform_device *pdev)
745 {
746 struct device_node *np = pdev->dev.of_node;
747 struct exynos5_i2c *i2c;
748 struct resource *mem;
749 unsigned int op_clock;
750 int ret;
751
752 i2c = devm_kzalloc(&pdev->dev, sizeof(struct exynos5_i2c), GFP_KERNEL);
753 if (!i2c)
754 return -ENOMEM;
755
756 if (of_property_read_u32(np, "clock-frequency", &op_clock)) {
757 i2c->speed_mode = HSI2C_FAST_SPD;
758 i2c->fs_clock = HSI2C_FS_TX_CLOCK;
759 } else {
760 if (op_clock >= HSI2C_HS_TX_CLOCK) {
761 i2c->speed_mode = HSI2C_HIGH_SPD;
762 i2c->fs_clock = HSI2C_FS_TX_CLOCK;
763 i2c->hs_clock = op_clock;
764 } else {
765 i2c->speed_mode = HSI2C_FAST_SPD;
766 i2c->fs_clock = op_clock;
767 }
768 }
769
770 strlcpy(i2c->adap.name, "exynos5-i2c", sizeof(i2c->adap.name));
771 i2c->adap.owner = THIS_MODULE;
772 i2c->adap.algo = &exynos5_i2c_algorithm;
773 i2c->adap.retries = 3;
774
775 i2c->dev = &pdev->dev;
776 i2c->clk = devm_clk_get(&pdev->dev, "hsi2c");
777 if (IS_ERR(i2c->clk)) {
778 dev_err(&pdev->dev, "cannot get clock\n");
779 return -ENOENT;
780 }
781
782 ret = clk_prepare_enable(i2c->clk);
783 if (ret)
784 return ret;
785
786 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
787 i2c->regs = devm_ioremap_resource(&pdev->dev, mem);
788 if (IS_ERR(i2c->regs)) {
789 ret = PTR_ERR(i2c->regs);
790 goto err_clk;
791 }
792
793 i2c->adap.dev.of_node = np;
794 i2c->adap.algo_data = i2c;
795 i2c->adap.dev.parent = &pdev->dev;
796
797 /* Clear pending interrupts from u-boot or misc causes */
798 exynos5_i2c_clr_pend_irq(i2c);
799
800 spin_lock_init(&i2c->lock);
801 init_completion(&i2c->msg_complete);
802
803 i2c->irq = ret = platform_get_irq(pdev, 0);
804 if (ret <= 0) {
805 dev_err(&pdev->dev, "cannot find HS-I2C IRQ\n");
806 ret = -EINVAL;
807 goto err_clk;
808 }
809
810 ret = devm_request_irq(&pdev->dev, i2c->irq, exynos5_i2c_irq,
811 IRQF_NO_SUSPEND | IRQF_ONESHOT,
812 dev_name(&pdev->dev), i2c);
813
814 if (ret != 0) {
815 dev_err(&pdev->dev, "cannot request HS-I2C IRQ %d\n", i2c->irq);
816 goto err_clk;
817 }
818
819 /* Need to check the variant before setting up. */
820 i2c->variant = exynos5_i2c_get_variant(pdev);
821
822 ret = exynos5_hsi2c_clock_setup(i2c);
823 if (ret)
824 goto err_clk;
825
826 exynos5_i2c_reset(i2c);
827
828 ret = i2c_add_adapter(&i2c->adap);
829 if (ret < 0)
830 goto err_clk;
831
832 platform_set_drvdata(pdev, i2c);
833
834 clk_disable(i2c->clk);
835
836 return 0;
837
838 err_clk:
839 clk_disable_unprepare(i2c->clk);
840 return ret;
841 }
842
843 static int exynos5_i2c_remove(struct platform_device *pdev)
844 {
845 struct exynos5_i2c *i2c = platform_get_drvdata(pdev);
846
847 i2c_del_adapter(&i2c->adap);
848
849 clk_unprepare(i2c->clk);
850
851 return 0;
852 }
853
854 #ifdef CONFIG_PM_SLEEP
855 static int exynos5_i2c_suspend_noirq(struct device *dev)
856 {
857 struct platform_device *pdev = to_platform_device(dev);
858 struct exynos5_i2c *i2c = platform_get_drvdata(pdev);
859
860 i2c->suspended = 1;
861
862 clk_unprepare(i2c->clk);
863
864 return 0;
865 }
866
867 static int exynos5_i2c_resume_noirq(struct device *dev)
868 {
869 struct platform_device *pdev = to_platform_device(dev);
870 struct exynos5_i2c *i2c = platform_get_drvdata(pdev);
871 int ret = 0;
872
873 ret = clk_prepare_enable(i2c->clk);
874 if (ret)
875 return ret;
876
877 ret = exynos5_hsi2c_clock_setup(i2c);
878 if (ret) {
879 clk_disable_unprepare(i2c->clk);
880 return ret;
881 }
882
883 exynos5_i2c_init(i2c);
884 clk_disable(i2c->clk);
885 i2c->suspended = 0;
886
887 return 0;
888 }
889 #endif
890
891 static const struct dev_pm_ops exynos5_i2c_dev_pm_ops = {
892 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(exynos5_i2c_suspend_noirq,
893 exynos5_i2c_resume_noirq)
894 };
895
896 static struct platform_driver exynos5_i2c_driver = {
897 .probe = exynos5_i2c_probe,
898 .remove = exynos5_i2c_remove,
899 .driver = {
900 .name = "exynos5-hsi2c",
901 .pm = &exynos5_i2c_dev_pm_ops,
902 .of_match_table = exynos5_i2c_match,
903 },
904 };
905
906 module_platform_driver(exynos5_i2c_driver);
907
908 MODULE_DESCRIPTION("Exynos5 HS-I2C Bus driver");
909 MODULE_AUTHOR("Naveen Krishna Chatradhi, <ch.naveen@samsung.com>");
910 MODULE_AUTHOR("Taekgyun Ko, <taeggyun.ko@samsung.com>");
911 MODULE_LICENSE("GPL v2");
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