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1 /*
2 Copyright (c) 1998 - 2002 Frodo Looijaard <frodol@dds.nl>,
3 Philip Edelbrock <phil@netroedge.com>, and Mark D. Studebaker
4 <mdsxyz123@yahoo.com>
5 Copyright (C) 2007 - 2012 Jean Delvare <jdelvare@suse.de>
6 Copyright (C) 2010 Intel Corporation,
7 David Woodhouse <dwmw2@infradead.org>
8
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2 of the License, or
12 (at your option) any later version.
13
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
18
19 You should have received a copy of the GNU General Public License
20 along with this program; if not, write to the Free Software
21 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22 */
23
24 /*
25 Supports the following Intel I/O Controller Hubs (ICH):
26
27 I/O Block I2C
28 region SMBus Block proc. block
29 Chip name PCI ID size PEC buffer call read
30 ----------------------------------------------------------------------
31 82801AA (ICH) 0x2413 16 no no no no
32 82801AB (ICH0) 0x2423 16 no no no no
33 82801BA (ICH2) 0x2443 16 no no no no
34 82801CA (ICH3) 0x2483 32 soft no no no
35 82801DB (ICH4) 0x24c3 32 hard yes no no
36 82801E (ICH5) 0x24d3 32 hard yes yes yes
37 6300ESB 0x25a4 32 hard yes yes yes
38 82801F (ICH6) 0x266a 32 hard yes yes yes
39 6310ESB/6320ESB 0x269b 32 hard yes yes yes
40 82801G (ICH7) 0x27da 32 hard yes yes yes
41 82801H (ICH8) 0x283e 32 hard yes yes yes
42 82801I (ICH9) 0x2930 32 hard yes yes yes
43 EP80579 (Tolapai) 0x5032 32 hard yes yes yes
44 ICH10 0x3a30 32 hard yes yes yes
45 ICH10 0x3a60 32 hard yes yes yes
46 5/3400 Series (PCH) 0x3b30 32 hard yes yes yes
47 6 Series (PCH) 0x1c22 32 hard yes yes yes
48 Patsburg (PCH) 0x1d22 32 hard yes yes yes
49 Patsburg (PCH) IDF 0x1d70 32 hard yes yes yes
50 Patsburg (PCH) IDF 0x1d71 32 hard yes yes yes
51 Patsburg (PCH) IDF 0x1d72 32 hard yes yes yes
52 DH89xxCC (PCH) 0x2330 32 hard yes yes yes
53 Panther Point (PCH) 0x1e22 32 hard yes yes yes
54 Lynx Point (PCH) 0x8c22 32 hard yes yes yes
55 Lynx Point-LP (PCH) 0x9c22 32 hard yes yes yes
56 Avoton (SOC) 0x1f3c 32 hard yes yes yes
57 Wellsburg (PCH) 0x8d22 32 hard yes yes yes
58 Wellsburg (PCH) MS 0x8d7d 32 hard yes yes yes
59 Wellsburg (PCH) MS 0x8d7e 32 hard yes yes yes
60 Wellsburg (PCH) MS 0x8d7f 32 hard yes yes yes
61 Coleto Creek (PCH) 0x23b0 32 hard yes yes yes
62 Wildcat Point-LP (PCH) 0x9ca2 32 hard yes yes yes
63
64 Features supported by this driver:
65 Software PEC no
66 Hardware PEC yes
67 Block buffer yes
68 Block process call transaction no
69 I2C block read transaction yes (doesn't use the block buffer)
70 Slave mode no
71 Interrupt processing yes
72
73 See the file Documentation/i2c/busses/i2c-i801 for details.
74 */
75
76 #include <linux/interrupt.h>
77 #include <linux/module.h>
78 #include <linux/pci.h>
79 #include <linux/kernel.h>
80 #include <linux/stddef.h>
81 #include <linux/delay.h>
82 #include <linux/ioport.h>
83 #include <linux/init.h>
84 #include <linux/i2c.h>
85 #include <linux/acpi.h>
86 #include <linux/io.h>
87 #include <linux/dmi.h>
88 #include <linux/slab.h>
89 #include <linux/wait.h>
90 #include <linux/err.h>
91
92 #if (defined CONFIG_I2C_MUX_GPIO || defined CONFIG_I2C_MUX_GPIO_MODULE) && \
93 defined CONFIG_DMI
94 #include <linux/gpio.h>
95 #include <linux/i2c-mux-gpio.h>
96 #include <linux/platform_device.h>
97 #endif
98
99 /* I801 SMBus address offsets */
100 #define SMBHSTSTS(p) (0 + (p)->smba)
101 #define SMBHSTCNT(p) (2 + (p)->smba)
102 #define SMBHSTCMD(p) (3 + (p)->smba)
103 #define SMBHSTADD(p) (4 + (p)->smba)
104 #define SMBHSTDAT0(p) (5 + (p)->smba)
105 #define SMBHSTDAT1(p) (6 + (p)->smba)
106 #define SMBBLKDAT(p) (7 + (p)->smba)
107 #define SMBPEC(p) (8 + (p)->smba) /* ICH3 and later */
108 #define SMBAUXSTS(p) (12 + (p)->smba) /* ICH4 and later */
109 #define SMBAUXCTL(p) (13 + (p)->smba) /* ICH4 and later */
110
111 /* PCI Address Constants */
112 #define SMBBAR 4
113 #define SMBPCISTS 0x006
114 #define SMBHSTCFG 0x040
115
116 /* Host status bits for SMBPCISTS */
117 #define SMBPCISTS_INTS 0x08
118
119 /* Host configuration bits for SMBHSTCFG */
120 #define SMBHSTCFG_HST_EN 1
121 #define SMBHSTCFG_SMB_SMI_EN 2
122 #define SMBHSTCFG_I2C_EN 4
123
124 /* Auxiliary control register bits, ICH4+ only */
125 #define SMBAUXCTL_CRC 1
126 #define SMBAUXCTL_E32B 2
127
128 /* Other settings */
129 #define MAX_RETRIES 400
130
131 /* I801 command constants */
132 #define I801_QUICK 0x00
133 #define I801_BYTE 0x04
134 #define I801_BYTE_DATA 0x08
135 #define I801_WORD_DATA 0x0C
136 #define I801_PROC_CALL 0x10 /* unimplemented */
137 #define I801_BLOCK_DATA 0x14
138 #define I801_I2C_BLOCK_DATA 0x18 /* ICH5 and later */
139
140 /* I801 Host Control register bits */
141 #define SMBHSTCNT_INTREN 0x01
142 #define SMBHSTCNT_KILL 0x02
143 #define SMBHSTCNT_LAST_BYTE 0x20
144 #define SMBHSTCNT_START 0x40
145 #define SMBHSTCNT_PEC_EN 0x80 /* ICH3 and later */
146
147 /* I801 Hosts Status register bits */
148 #define SMBHSTSTS_BYTE_DONE 0x80
149 #define SMBHSTSTS_INUSE_STS 0x40
150 #define SMBHSTSTS_SMBALERT_STS 0x20
151 #define SMBHSTSTS_FAILED 0x10
152 #define SMBHSTSTS_BUS_ERR 0x08
153 #define SMBHSTSTS_DEV_ERR 0x04
154 #define SMBHSTSTS_INTR 0x02
155 #define SMBHSTSTS_HOST_BUSY 0x01
156
157 #define STATUS_ERROR_FLAGS (SMBHSTSTS_FAILED | SMBHSTSTS_BUS_ERR | \
158 SMBHSTSTS_DEV_ERR)
159
160 #define STATUS_FLAGS (SMBHSTSTS_BYTE_DONE | SMBHSTSTS_INTR | \
161 STATUS_ERROR_FLAGS)
162
163 /* Older devices have their ID defined in <linux/pci_ids.h> */
164 #define PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS 0x1c22
165 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS 0x1d22
166 /* Patsburg also has three 'Integrated Device Function' SMBus controllers */
167 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0 0x1d70
168 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1 0x1d71
169 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2 0x1d72
170 #define PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS 0x1e22
171 #define PCI_DEVICE_ID_INTEL_AVOTON_SMBUS 0x1f3c
172 #define PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS 0x2330
173 #define PCI_DEVICE_ID_INTEL_COLETOCREEK_SMBUS 0x23b0
174 #define PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS 0x3b30
175 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS 0x8c22
176 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS 0x8d22
177 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0 0x8d7d
178 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1 0x8d7e
179 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2 0x8d7f
180 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS 0x9c22
181 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_SMBUS 0x9ca2
182
183 struct i801_mux_config {
184 char *gpio_chip;
185 unsigned values[3];
186 int n_values;
187 unsigned classes[3];
188 unsigned gpios[2]; /* Relative to gpio_chip->base */
189 int n_gpios;
190 };
191
192 struct i801_priv {
193 struct i2c_adapter adapter;
194 unsigned long smba;
195 unsigned char original_hstcfg;
196 struct pci_dev *pci_dev;
197 unsigned int features;
198
199 /* isr processing */
200 wait_queue_head_t waitq;
201 u8 status;
202
203 /* Command state used by isr for byte-by-byte block transactions */
204 u8 cmd;
205 bool is_read;
206 int count;
207 int len;
208 u8 *data;
209
210 #if (defined CONFIG_I2C_MUX_GPIO || defined CONFIG_I2C_MUX_GPIO_MODULE) && \
211 defined CONFIG_DMI
212 const struct i801_mux_config *mux_drvdata;
213 struct platform_device *mux_pdev;
214 #endif
215 };
216
217 static struct pci_driver i801_driver;
218
219 #define FEATURE_SMBUS_PEC (1 << 0)
220 #define FEATURE_BLOCK_BUFFER (1 << 1)
221 #define FEATURE_BLOCK_PROC (1 << 2)
222 #define FEATURE_I2C_BLOCK_READ (1 << 3)
223 #define FEATURE_IRQ (1 << 4)
224 /* Not really a feature, but it's convenient to handle it as such */
225 #define FEATURE_IDF (1 << 15)
226
227 static const char *i801_feature_names[] = {
228 "SMBus PEC",
229 "Block buffer",
230 "Block process call",
231 "I2C block read",
232 "Interrupt",
233 };
234
235 static unsigned int disable_features;
236 module_param(disable_features, uint, S_IRUGO | S_IWUSR);
237 MODULE_PARM_DESC(disable_features, "Disable selected driver features:\n"
238 "\t\t 0x01 disable SMBus PEC\n"
239 "\t\t 0x02 disable the block buffer\n"
240 "\t\t 0x08 disable the I2C block read functionality\n"
241 "\t\t 0x10 don't use interrupts ");
242
243 /* Make sure the SMBus host is ready to start transmitting.
244 Return 0 if it is, -EBUSY if it is not. */
245 static int i801_check_pre(struct i801_priv *priv)
246 {
247 int status;
248
249 status = inb_p(SMBHSTSTS(priv));
250 if (status & SMBHSTSTS_HOST_BUSY) {
251 dev_err(&priv->pci_dev->dev, "SMBus is busy, can't use it!\n");
252 return -EBUSY;
253 }
254
255 status &= STATUS_FLAGS;
256 if (status) {
257 dev_dbg(&priv->pci_dev->dev, "Clearing status flags (%02x)\n",
258 status);
259 outb_p(status, SMBHSTSTS(priv));
260 status = inb_p(SMBHSTSTS(priv)) & STATUS_FLAGS;
261 if (status) {
262 dev_err(&priv->pci_dev->dev,
263 "Failed clearing status flags (%02x)\n",
264 status);
265 return -EBUSY;
266 }
267 }
268
269 return 0;
270 }
271
272 /*
273 * Convert the status register to an error code, and clear it.
274 * Note that status only contains the bits we want to clear, not the
275 * actual register value.
276 */
277 static int i801_check_post(struct i801_priv *priv, int status)
278 {
279 int result = 0;
280
281 /*
282 * If the SMBus is still busy, we give up
283 * Note: This timeout condition only happens when using polling
284 * transactions. For interrupt operation, NAK/timeout is indicated by
285 * DEV_ERR.
286 */
287 if (unlikely(status < 0)) {
288 dev_err(&priv->pci_dev->dev, "Transaction timeout\n");
289 /* try to stop the current command */
290 dev_dbg(&priv->pci_dev->dev, "Terminating the current operation\n");
291 outb_p(inb_p(SMBHSTCNT(priv)) | SMBHSTCNT_KILL,
292 SMBHSTCNT(priv));
293 usleep_range(1000, 2000);
294 outb_p(inb_p(SMBHSTCNT(priv)) & (~SMBHSTCNT_KILL),
295 SMBHSTCNT(priv));
296
297 /* Check if it worked */
298 status = inb_p(SMBHSTSTS(priv));
299 if ((status & SMBHSTSTS_HOST_BUSY) ||
300 !(status & SMBHSTSTS_FAILED))
301 dev_err(&priv->pci_dev->dev,
302 "Failed terminating the transaction\n");
303 outb_p(STATUS_FLAGS, SMBHSTSTS(priv));
304 return -ETIMEDOUT;
305 }
306
307 if (status & SMBHSTSTS_FAILED) {
308 result = -EIO;
309 dev_err(&priv->pci_dev->dev, "Transaction failed\n");
310 }
311 if (status & SMBHSTSTS_DEV_ERR) {
312 result = -ENXIO;
313 dev_dbg(&priv->pci_dev->dev, "No response\n");
314 }
315 if (status & SMBHSTSTS_BUS_ERR) {
316 result = -EAGAIN;
317 dev_dbg(&priv->pci_dev->dev, "Lost arbitration\n");
318 }
319
320 /* Clear status flags except BYTE_DONE, to be cleared by caller */
321 outb_p(status, SMBHSTSTS(priv));
322
323 return result;
324 }
325
326 /* Wait for BUSY being cleared and either INTR or an error flag being set */
327 static int i801_wait_intr(struct i801_priv *priv)
328 {
329 int timeout = 0;
330 int status;
331
332 /* We will always wait for a fraction of a second! */
333 do {
334 usleep_range(250, 500);
335 status = inb_p(SMBHSTSTS(priv));
336 } while (((status & SMBHSTSTS_HOST_BUSY) ||
337 !(status & (STATUS_ERROR_FLAGS | SMBHSTSTS_INTR))) &&
338 (timeout++ < MAX_RETRIES));
339
340 if (timeout > MAX_RETRIES) {
341 dev_dbg(&priv->pci_dev->dev, "INTR Timeout!\n");
342 return -ETIMEDOUT;
343 }
344 return status & (STATUS_ERROR_FLAGS | SMBHSTSTS_INTR);
345 }
346
347 /* Wait for either BYTE_DONE or an error flag being set */
348 static int i801_wait_byte_done(struct i801_priv *priv)
349 {
350 int timeout = 0;
351 int status;
352
353 /* We will always wait for a fraction of a second! */
354 do {
355 usleep_range(250, 500);
356 status = inb_p(SMBHSTSTS(priv));
357 } while (!(status & (STATUS_ERROR_FLAGS | SMBHSTSTS_BYTE_DONE)) &&
358 (timeout++ < MAX_RETRIES));
359
360 if (timeout > MAX_RETRIES) {
361 dev_dbg(&priv->pci_dev->dev, "BYTE_DONE Timeout!\n");
362 return -ETIMEDOUT;
363 }
364 return status & STATUS_ERROR_FLAGS;
365 }
366
367 static int i801_transaction(struct i801_priv *priv, int xact)
368 {
369 int status;
370 int result;
371
372 result = i801_check_pre(priv);
373 if (result < 0)
374 return result;
375
376 if (priv->features & FEATURE_IRQ) {
377 outb_p(xact | SMBHSTCNT_INTREN | SMBHSTCNT_START,
378 SMBHSTCNT(priv));
379 wait_event(priv->waitq, (status = priv->status));
380 priv->status = 0;
381 return i801_check_post(priv, status);
382 }
383
384 /* the current contents of SMBHSTCNT can be overwritten, since PEC,
385 * SMBSCMD are passed in xact */
386 outb_p(xact | SMBHSTCNT_START, SMBHSTCNT(priv));
387
388 status = i801_wait_intr(priv);
389 return i801_check_post(priv, status);
390 }
391
392 static int i801_block_transaction_by_block(struct i801_priv *priv,
393 union i2c_smbus_data *data,
394 char read_write, int hwpec)
395 {
396 int i, len;
397 int status;
398
399 inb_p(SMBHSTCNT(priv)); /* reset the data buffer index */
400
401 /* Use 32-byte buffer to process this transaction */
402 if (read_write == I2C_SMBUS_WRITE) {
403 len = data->block[0];
404 outb_p(len, SMBHSTDAT0(priv));
405 for (i = 0; i < len; i++)
406 outb_p(data->block[i+1], SMBBLKDAT(priv));
407 }
408
409 status = i801_transaction(priv, I801_BLOCK_DATA |
410 (hwpec ? SMBHSTCNT_PEC_EN : 0));
411 if (status)
412 return status;
413
414 if (read_write == I2C_SMBUS_READ) {
415 len = inb_p(SMBHSTDAT0(priv));
416 if (len < 1 || len > I2C_SMBUS_BLOCK_MAX)
417 return -EPROTO;
418
419 data->block[0] = len;
420 for (i = 0; i < len; i++)
421 data->block[i + 1] = inb_p(SMBBLKDAT(priv));
422 }
423 return 0;
424 }
425
426 static void i801_isr_byte_done(struct i801_priv *priv)
427 {
428 if (priv->is_read) {
429 /* For SMBus block reads, length is received with first byte */
430 if (((priv->cmd & 0x1c) == I801_BLOCK_DATA) &&
431 (priv->count == 0)) {
432 priv->len = inb_p(SMBHSTDAT0(priv));
433 if (priv->len < 1 || priv->len > I2C_SMBUS_BLOCK_MAX) {
434 dev_err(&priv->pci_dev->dev,
435 "Illegal SMBus block read size %d\n",
436 priv->len);
437 /* FIXME: Recover */
438 priv->len = I2C_SMBUS_BLOCK_MAX;
439 } else {
440 dev_dbg(&priv->pci_dev->dev,
441 "SMBus block read size is %d\n",
442 priv->len);
443 }
444 priv->data[-1] = priv->len;
445 }
446
447 /* Read next byte */
448 if (priv->count < priv->len)
449 priv->data[priv->count++] = inb(SMBBLKDAT(priv));
450 else
451 dev_dbg(&priv->pci_dev->dev,
452 "Discarding extra byte on block read\n");
453
454 /* Set LAST_BYTE for last byte of read transaction */
455 if (priv->count == priv->len - 1)
456 outb_p(priv->cmd | SMBHSTCNT_LAST_BYTE,
457 SMBHSTCNT(priv));
458 } else if (priv->count < priv->len - 1) {
459 /* Write next byte, except for IRQ after last byte */
460 outb_p(priv->data[++priv->count], SMBBLKDAT(priv));
461 }
462
463 /* Clear BYTE_DONE to continue with next byte */
464 outb_p(SMBHSTSTS_BYTE_DONE, SMBHSTSTS(priv));
465 }
466
467 /*
468 * There are two kinds of interrupts:
469 *
470 * 1) i801 signals transaction completion with one of these interrupts:
471 * INTR - Success
472 * DEV_ERR - Invalid command, NAK or communication timeout
473 * BUS_ERR - SMI# transaction collision
474 * FAILED - transaction was canceled due to a KILL request
475 * When any of these occur, update ->status and wake up the waitq.
476 * ->status must be cleared before kicking off the next transaction.
477 *
478 * 2) For byte-by-byte (I2C read/write) transactions, one BYTE_DONE interrupt
479 * occurs for each byte of a byte-by-byte to prepare the next byte.
480 */
481 static irqreturn_t i801_isr(int irq, void *dev_id)
482 {
483 struct i801_priv *priv = dev_id;
484 u16 pcists;
485 u8 status;
486
487 /* Confirm this is our interrupt */
488 pci_read_config_word(priv->pci_dev, SMBPCISTS, &pcists);
489 if (!(pcists & SMBPCISTS_INTS))
490 return IRQ_NONE;
491
492 status = inb_p(SMBHSTSTS(priv));
493 if (status != 0x42)
494 dev_dbg(&priv->pci_dev->dev, "irq: status = %02x\n", status);
495
496 if (status & SMBHSTSTS_BYTE_DONE)
497 i801_isr_byte_done(priv);
498
499 /*
500 * Clear irq sources and report transaction result.
501 * ->status must be cleared before the next transaction is started.
502 */
503 status &= SMBHSTSTS_INTR | STATUS_ERROR_FLAGS;
504 if (status) {
505 outb_p(status, SMBHSTSTS(priv));
506 priv->status |= status;
507 wake_up(&priv->waitq);
508 }
509
510 return IRQ_HANDLED;
511 }
512
513 /*
514 * For "byte-by-byte" block transactions:
515 * I2C write uses cmd=I801_BLOCK_DATA, I2C_EN=1
516 * I2C read uses cmd=I801_I2C_BLOCK_DATA
517 */
518 static int i801_block_transaction_byte_by_byte(struct i801_priv *priv,
519 union i2c_smbus_data *data,
520 char read_write, int command,
521 int hwpec)
522 {
523 int i, len;
524 int smbcmd;
525 int status;
526 int result;
527
528 result = i801_check_pre(priv);
529 if (result < 0)
530 return result;
531
532 len = data->block[0];
533
534 if (read_write == I2C_SMBUS_WRITE) {
535 outb_p(len, SMBHSTDAT0(priv));
536 outb_p(data->block[1], SMBBLKDAT(priv));
537 }
538
539 if (command == I2C_SMBUS_I2C_BLOCK_DATA &&
540 read_write == I2C_SMBUS_READ)
541 smbcmd = I801_I2C_BLOCK_DATA;
542 else
543 smbcmd = I801_BLOCK_DATA;
544
545 if (priv->features & FEATURE_IRQ) {
546 priv->is_read = (read_write == I2C_SMBUS_READ);
547 if (len == 1 && priv->is_read)
548 smbcmd |= SMBHSTCNT_LAST_BYTE;
549 priv->cmd = smbcmd | SMBHSTCNT_INTREN;
550 priv->len = len;
551 priv->count = 0;
552 priv->data = &data->block[1];
553
554 outb_p(priv->cmd | SMBHSTCNT_START, SMBHSTCNT(priv));
555 wait_event(priv->waitq, (status = priv->status));
556 priv->status = 0;
557 return i801_check_post(priv, status);
558 }
559
560 for (i = 1; i <= len; i++) {
561 if (i == len && read_write == I2C_SMBUS_READ)
562 smbcmd |= SMBHSTCNT_LAST_BYTE;
563 outb_p(smbcmd, SMBHSTCNT(priv));
564
565 if (i == 1)
566 outb_p(inb(SMBHSTCNT(priv)) | SMBHSTCNT_START,
567 SMBHSTCNT(priv));
568
569 status = i801_wait_byte_done(priv);
570 if (status)
571 goto exit;
572
573 if (i == 1 && read_write == I2C_SMBUS_READ
574 && command != I2C_SMBUS_I2C_BLOCK_DATA) {
575 len = inb_p(SMBHSTDAT0(priv));
576 if (len < 1 || len > I2C_SMBUS_BLOCK_MAX) {
577 dev_err(&priv->pci_dev->dev,
578 "Illegal SMBus block read size %d\n",
579 len);
580 /* Recover */
581 while (inb_p(SMBHSTSTS(priv)) &
582 SMBHSTSTS_HOST_BUSY)
583 outb_p(SMBHSTSTS_BYTE_DONE,
584 SMBHSTSTS(priv));
585 outb_p(SMBHSTSTS_INTR, SMBHSTSTS(priv));
586 return -EPROTO;
587 }
588 data->block[0] = len;
589 }
590
591 /* Retrieve/store value in SMBBLKDAT */
592 if (read_write == I2C_SMBUS_READ)
593 data->block[i] = inb_p(SMBBLKDAT(priv));
594 if (read_write == I2C_SMBUS_WRITE && i+1 <= len)
595 outb_p(data->block[i+1], SMBBLKDAT(priv));
596
597 /* signals SMBBLKDAT ready */
598 outb_p(SMBHSTSTS_BYTE_DONE, SMBHSTSTS(priv));
599 }
600
601 status = i801_wait_intr(priv);
602 exit:
603 return i801_check_post(priv, status);
604 }
605
606 static int i801_set_block_buffer_mode(struct i801_priv *priv)
607 {
608 outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_E32B, SMBAUXCTL(priv));
609 if ((inb_p(SMBAUXCTL(priv)) & SMBAUXCTL_E32B) == 0)
610 return -EIO;
611 return 0;
612 }
613
614 /* Block transaction function */
615 static int i801_block_transaction(struct i801_priv *priv,
616 union i2c_smbus_data *data, char read_write,
617 int command, int hwpec)
618 {
619 int result = 0;
620 unsigned char hostc;
621
622 if (command == I2C_SMBUS_I2C_BLOCK_DATA) {
623 if (read_write == I2C_SMBUS_WRITE) {
624 /* set I2C_EN bit in configuration register */
625 pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &hostc);
626 pci_write_config_byte(priv->pci_dev, SMBHSTCFG,
627 hostc | SMBHSTCFG_I2C_EN);
628 } else if (!(priv->features & FEATURE_I2C_BLOCK_READ)) {
629 dev_err(&priv->pci_dev->dev,
630 "I2C block read is unsupported!\n");
631 return -EOPNOTSUPP;
632 }
633 }
634
635 if (read_write == I2C_SMBUS_WRITE
636 || command == I2C_SMBUS_I2C_BLOCK_DATA) {
637 if (data->block[0] < 1)
638 data->block[0] = 1;
639 if (data->block[0] > I2C_SMBUS_BLOCK_MAX)
640 data->block[0] = I2C_SMBUS_BLOCK_MAX;
641 } else {
642 data->block[0] = 32; /* max for SMBus block reads */
643 }
644
645 /* Experience has shown that the block buffer can only be used for
646 SMBus (not I2C) block transactions, even though the datasheet
647 doesn't mention this limitation. */
648 if ((priv->features & FEATURE_BLOCK_BUFFER)
649 && command != I2C_SMBUS_I2C_BLOCK_DATA
650 && i801_set_block_buffer_mode(priv) == 0)
651 result = i801_block_transaction_by_block(priv, data,
652 read_write, hwpec);
653 else
654 result = i801_block_transaction_byte_by_byte(priv, data,
655 read_write,
656 command, hwpec);
657
658 if (command == I2C_SMBUS_I2C_BLOCK_DATA
659 && read_write == I2C_SMBUS_WRITE) {
660 /* restore saved configuration register value */
661 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, hostc);
662 }
663 return result;
664 }
665
666 /* Return negative errno on error. */
667 static s32 i801_access(struct i2c_adapter *adap, u16 addr,
668 unsigned short flags, char read_write, u8 command,
669 int size, union i2c_smbus_data *data)
670 {
671 int hwpec;
672 int block = 0;
673 int ret, xact = 0;
674 struct i801_priv *priv = i2c_get_adapdata(adap);
675
676 hwpec = (priv->features & FEATURE_SMBUS_PEC) && (flags & I2C_CLIENT_PEC)
677 && size != I2C_SMBUS_QUICK
678 && size != I2C_SMBUS_I2C_BLOCK_DATA;
679
680 switch (size) {
681 case I2C_SMBUS_QUICK:
682 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
683 SMBHSTADD(priv));
684 xact = I801_QUICK;
685 break;
686 case I2C_SMBUS_BYTE:
687 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
688 SMBHSTADD(priv));
689 if (read_write == I2C_SMBUS_WRITE)
690 outb_p(command, SMBHSTCMD(priv));
691 xact = I801_BYTE;
692 break;
693 case I2C_SMBUS_BYTE_DATA:
694 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
695 SMBHSTADD(priv));
696 outb_p(command, SMBHSTCMD(priv));
697 if (read_write == I2C_SMBUS_WRITE)
698 outb_p(data->byte, SMBHSTDAT0(priv));
699 xact = I801_BYTE_DATA;
700 break;
701 case I2C_SMBUS_WORD_DATA:
702 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
703 SMBHSTADD(priv));
704 outb_p(command, SMBHSTCMD(priv));
705 if (read_write == I2C_SMBUS_WRITE) {
706 outb_p(data->word & 0xff, SMBHSTDAT0(priv));
707 outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1(priv));
708 }
709 xact = I801_WORD_DATA;
710 break;
711 case I2C_SMBUS_BLOCK_DATA:
712 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
713 SMBHSTADD(priv));
714 outb_p(command, SMBHSTCMD(priv));
715 block = 1;
716 break;
717 case I2C_SMBUS_I2C_BLOCK_DATA:
718 /* NB: page 240 of ICH5 datasheet shows that the R/#W
719 * bit should be cleared here, even when reading */
720 outb_p((addr & 0x7f) << 1, SMBHSTADD(priv));
721 if (read_write == I2C_SMBUS_READ) {
722 /* NB: page 240 of ICH5 datasheet also shows
723 * that DATA1 is the cmd field when reading */
724 outb_p(command, SMBHSTDAT1(priv));
725 } else
726 outb_p(command, SMBHSTCMD(priv));
727 block = 1;
728 break;
729 default:
730 dev_err(&priv->pci_dev->dev, "Unsupported transaction %d\n",
731 size);
732 return -EOPNOTSUPP;
733 }
734
735 if (hwpec) /* enable/disable hardware PEC */
736 outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_CRC, SMBAUXCTL(priv));
737 else
738 outb_p(inb_p(SMBAUXCTL(priv)) & (~SMBAUXCTL_CRC),
739 SMBAUXCTL(priv));
740
741 if (block)
742 ret = i801_block_transaction(priv, data, read_write, size,
743 hwpec);
744 else
745 ret = i801_transaction(priv, xact);
746
747 /* Some BIOSes don't like it when PEC is enabled at reboot or resume
748 time, so we forcibly disable it after every transaction. Turn off
749 E32B for the same reason. */
750 if (hwpec || block)
751 outb_p(inb_p(SMBAUXCTL(priv)) &
752 ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv));
753
754 if (block)
755 return ret;
756 if (ret)
757 return ret;
758 if ((read_write == I2C_SMBUS_WRITE) || (xact == I801_QUICK))
759 return 0;
760
761 switch (xact & 0x7f) {
762 case I801_BYTE: /* Result put in SMBHSTDAT0 */
763 case I801_BYTE_DATA:
764 data->byte = inb_p(SMBHSTDAT0(priv));
765 break;
766 case I801_WORD_DATA:
767 data->word = inb_p(SMBHSTDAT0(priv)) +
768 (inb_p(SMBHSTDAT1(priv)) << 8);
769 break;
770 }
771 return 0;
772 }
773
774
775 static u32 i801_func(struct i2c_adapter *adapter)
776 {
777 struct i801_priv *priv = i2c_get_adapdata(adapter);
778
779 return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
780 I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
781 I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_WRITE_I2C_BLOCK |
782 ((priv->features & FEATURE_SMBUS_PEC) ? I2C_FUNC_SMBUS_PEC : 0) |
783 ((priv->features & FEATURE_I2C_BLOCK_READ) ?
784 I2C_FUNC_SMBUS_READ_I2C_BLOCK : 0);
785 }
786
787 static const struct i2c_algorithm smbus_algorithm = {
788 .smbus_xfer = i801_access,
789 .functionality = i801_func,
790 };
791
792 static DEFINE_PCI_DEVICE_TABLE(i801_ids) = {
793 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_3) },
794 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_3) },
795 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_2) },
796 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_3) },
797 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_3) },
798 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_3) },
799 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_4) },
800 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_16) },
801 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_17) },
802 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_17) },
803 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_5) },
804 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_6) },
805 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EP80579_1) },
806 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_4) },
807 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_5) },
808 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS) },
809 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS) },
810 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS) },
811 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0) },
812 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1) },
813 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2) },
814 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS) },
815 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS) },
816 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS) },
817 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS) },
818 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_AVOTON_SMBUS) },
819 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS) },
820 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0) },
821 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1) },
822 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2) },
823 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COLETOCREEK_SMBUS) },
824 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_SMBUS) },
825 { 0, }
826 };
827
828 MODULE_DEVICE_TABLE(pci, i801_ids);
829
830 #if defined CONFIG_X86 && defined CONFIG_DMI
831 static unsigned char apanel_addr;
832
833 /* Scan the system ROM for the signature "FJKEYINF" */
834 static __init const void __iomem *bios_signature(const void __iomem *bios)
835 {
836 ssize_t offset;
837 const unsigned char signature[] = "FJKEYINF";
838
839 for (offset = 0; offset < 0x10000; offset += 0x10) {
840 if (check_signature(bios + offset, signature,
841 sizeof(signature)-1))
842 return bios + offset;
843 }
844 return NULL;
845 }
846
847 static void __init input_apanel_init(void)
848 {
849 void __iomem *bios;
850 const void __iomem *p;
851
852 bios = ioremap(0xF0000, 0x10000); /* Can't fail */
853 p = bios_signature(bios);
854 if (p) {
855 /* just use the first address */
856 apanel_addr = readb(p + 8 + 3) >> 1;
857 }
858 iounmap(bios);
859 }
860
861 struct dmi_onboard_device_info {
862 const char *name;
863 u8 type;
864 unsigned short i2c_addr;
865 const char *i2c_type;
866 };
867
868 static const struct dmi_onboard_device_info dmi_devices[] = {
869 { "Syleus", DMI_DEV_TYPE_OTHER, 0x73, "fscsyl" },
870 { "Hermes", DMI_DEV_TYPE_OTHER, 0x73, "fscher" },
871 { "Hades", DMI_DEV_TYPE_OTHER, 0x73, "fschds" },
872 };
873
874 static void dmi_check_onboard_device(u8 type, const char *name,
875 struct i2c_adapter *adap)
876 {
877 int i;
878 struct i2c_board_info info;
879
880 for (i = 0; i < ARRAY_SIZE(dmi_devices); i++) {
881 /* & ~0x80, ignore enabled/disabled bit */
882 if ((type & ~0x80) != dmi_devices[i].type)
883 continue;
884 if (strcasecmp(name, dmi_devices[i].name))
885 continue;
886
887 memset(&info, 0, sizeof(struct i2c_board_info));
888 info.addr = dmi_devices[i].i2c_addr;
889 strlcpy(info.type, dmi_devices[i].i2c_type, I2C_NAME_SIZE);
890 i2c_new_device(adap, &info);
891 break;
892 }
893 }
894
895 /* We use our own function to check for onboard devices instead of
896 dmi_find_device() as some buggy BIOS's have the devices we are interested
897 in marked as disabled */
898 static void dmi_check_onboard_devices(const struct dmi_header *dm, void *adap)
899 {
900 int i, count;
901
902 if (dm->type != 10)
903 return;
904
905 count = (dm->length - sizeof(struct dmi_header)) / 2;
906 for (i = 0; i < count; i++) {
907 const u8 *d = (char *)(dm + 1) + (i * 2);
908 const char *name = ((char *) dm) + dm->length;
909 u8 type = d[0];
910 u8 s = d[1];
911
912 if (!s)
913 continue;
914 s--;
915 while (s > 0 && name[0]) {
916 name += strlen(name) + 1;
917 s--;
918 }
919 if (name[0] == 0) /* Bogus string reference */
920 continue;
921
922 dmi_check_onboard_device(type, name, adap);
923 }
924 }
925
926 /* Register optional slaves */
927 static void i801_probe_optional_slaves(struct i801_priv *priv)
928 {
929 /* Only register slaves on main SMBus channel */
930 if (priv->features & FEATURE_IDF)
931 return;
932
933 if (apanel_addr) {
934 struct i2c_board_info info;
935
936 memset(&info, 0, sizeof(struct i2c_board_info));
937 info.addr = apanel_addr;
938 strlcpy(info.type, "fujitsu_apanel", I2C_NAME_SIZE);
939 i2c_new_device(&priv->adapter, &info);
940 }
941
942 if (dmi_name_in_vendors("FUJITSU"))
943 dmi_walk(dmi_check_onboard_devices, &priv->adapter);
944 }
945 #else
946 static void __init input_apanel_init(void) {}
947 static void i801_probe_optional_slaves(struct i801_priv *priv) {}
948 #endif /* CONFIG_X86 && CONFIG_DMI */
949
950 #if (defined CONFIG_I2C_MUX_GPIO || defined CONFIG_I2C_MUX_GPIO_MODULE) && \
951 defined CONFIG_DMI
952 static struct i801_mux_config i801_mux_config_asus_z8_d12 = {
953 .gpio_chip = "gpio_ich",
954 .values = { 0x02, 0x03 },
955 .n_values = 2,
956 .classes = { I2C_CLASS_SPD, I2C_CLASS_SPD },
957 .gpios = { 52, 53 },
958 .n_gpios = 2,
959 };
960
961 static struct i801_mux_config i801_mux_config_asus_z8_d18 = {
962 .gpio_chip = "gpio_ich",
963 .values = { 0x02, 0x03, 0x01 },
964 .n_values = 3,
965 .classes = { I2C_CLASS_SPD, I2C_CLASS_SPD, I2C_CLASS_SPD },
966 .gpios = { 52, 53 },
967 .n_gpios = 2,
968 };
969
970 static const struct dmi_system_id mux_dmi_table[] = {
971 {
972 .matches = {
973 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
974 DMI_MATCH(DMI_BOARD_NAME, "Z8NA-D6(C)"),
975 },
976 .driver_data = &i801_mux_config_asus_z8_d12,
977 },
978 {
979 .matches = {
980 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
981 DMI_MATCH(DMI_BOARD_NAME, "Z8P(N)E-D12(X)"),
982 },
983 .driver_data = &i801_mux_config_asus_z8_d12,
984 },
985 {
986 .matches = {
987 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
988 DMI_MATCH(DMI_BOARD_NAME, "Z8NH-D12"),
989 },
990 .driver_data = &i801_mux_config_asus_z8_d12,
991 },
992 {
993 .matches = {
994 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
995 DMI_MATCH(DMI_BOARD_NAME, "Z8PH-D12/IFB"),
996 },
997 .driver_data = &i801_mux_config_asus_z8_d12,
998 },
999 {
1000 .matches = {
1001 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1002 DMI_MATCH(DMI_BOARD_NAME, "Z8NR-D12"),
1003 },
1004 .driver_data = &i801_mux_config_asus_z8_d12,
1005 },
1006 {
1007 .matches = {
1008 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1009 DMI_MATCH(DMI_BOARD_NAME, "Z8P(N)H-D12"),
1010 },
1011 .driver_data = &i801_mux_config_asus_z8_d12,
1012 },
1013 {
1014 .matches = {
1015 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1016 DMI_MATCH(DMI_BOARD_NAME, "Z8PG-D18"),
1017 },
1018 .driver_data = &i801_mux_config_asus_z8_d18,
1019 },
1020 {
1021 .matches = {
1022 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1023 DMI_MATCH(DMI_BOARD_NAME, "Z8PE-D18"),
1024 },
1025 .driver_data = &i801_mux_config_asus_z8_d18,
1026 },
1027 {
1028 .matches = {
1029 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1030 DMI_MATCH(DMI_BOARD_NAME, "Z8PS-D12"),
1031 },
1032 .driver_data = &i801_mux_config_asus_z8_d12,
1033 },
1034 { }
1035 };
1036
1037 /* Setup multiplexing if needed */
1038 static int i801_add_mux(struct i801_priv *priv)
1039 {
1040 struct device *dev = &priv->adapter.dev;
1041 const struct i801_mux_config *mux_config;
1042 struct i2c_mux_gpio_platform_data gpio_data;
1043 int err;
1044
1045 if (!priv->mux_drvdata)
1046 return 0;
1047 mux_config = priv->mux_drvdata;
1048
1049 /* Prepare the platform data */
1050 memset(&gpio_data, 0, sizeof(struct i2c_mux_gpio_platform_data));
1051 gpio_data.parent = priv->adapter.nr;
1052 gpio_data.values = mux_config->values;
1053 gpio_data.n_values = mux_config->n_values;
1054 gpio_data.classes = mux_config->classes;
1055 gpio_data.gpio_chip = mux_config->gpio_chip;
1056 gpio_data.gpios = mux_config->gpios;
1057 gpio_data.n_gpios = mux_config->n_gpios;
1058 gpio_data.idle = I2C_MUX_GPIO_NO_IDLE;
1059
1060 /* Register the mux device */
1061 priv->mux_pdev = platform_device_register_data(dev, "i2c-mux-gpio",
1062 PLATFORM_DEVID_AUTO, &gpio_data,
1063 sizeof(struct i2c_mux_gpio_platform_data));
1064 if (IS_ERR(priv->mux_pdev)) {
1065 err = PTR_ERR(priv->mux_pdev);
1066 priv->mux_pdev = NULL;
1067 dev_err(dev, "Failed to register i2c-mux-gpio device\n");
1068 return err;
1069 }
1070
1071 return 0;
1072 }
1073
1074 static void i801_del_mux(struct i801_priv *priv)
1075 {
1076 if (priv->mux_pdev)
1077 platform_device_unregister(priv->mux_pdev);
1078 }
1079
1080 static unsigned int i801_get_adapter_class(struct i801_priv *priv)
1081 {
1082 const struct dmi_system_id *id;
1083 const struct i801_mux_config *mux_config;
1084 unsigned int class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
1085 int i;
1086
1087 id = dmi_first_match(mux_dmi_table);
1088 if (id) {
1089 /* Remove branch classes from trunk */
1090 mux_config = id->driver_data;
1091 for (i = 0; i < mux_config->n_values; i++)
1092 class &= ~mux_config->classes[i];
1093
1094 /* Remember for later */
1095 priv->mux_drvdata = mux_config;
1096 }
1097
1098 return class;
1099 }
1100 #else
1101 static inline int i801_add_mux(struct i801_priv *priv) { return 0; }
1102 static inline void i801_del_mux(struct i801_priv *priv) { }
1103
1104 static inline unsigned int i801_get_adapter_class(struct i801_priv *priv)
1105 {
1106 return I2C_CLASS_HWMON | I2C_CLASS_SPD;
1107 }
1108 #endif
1109
1110 static int i801_probe(struct pci_dev *dev, const struct pci_device_id *id)
1111 {
1112 unsigned char temp;
1113 int err, i;
1114 struct i801_priv *priv;
1115
1116 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
1117 if (!priv)
1118 return -ENOMEM;
1119
1120 i2c_set_adapdata(&priv->adapter, priv);
1121 priv->adapter.owner = THIS_MODULE;
1122 priv->adapter.class = i801_get_adapter_class(priv);
1123 priv->adapter.algo = &smbus_algorithm;
1124
1125 priv->pci_dev = dev;
1126 switch (dev->device) {
1127 case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0:
1128 case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1:
1129 case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2:
1130 case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0:
1131 case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1:
1132 case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2:
1133 priv->features |= FEATURE_IDF;
1134 /* fall through */
1135 default:
1136 priv->features |= FEATURE_I2C_BLOCK_READ;
1137 priv->features |= FEATURE_IRQ;
1138 /* fall through */
1139 case PCI_DEVICE_ID_INTEL_82801DB_3:
1140 priv->features |= FEATURE_SMBUS_PEC;
1141 priv->features |= FEATURE_BLOCK_BUFFER;
1142 /* fall through */
1143 case PCI_DEVICE_ID_INTEL_82801CA_3:
1144 case PCI_DEVICE_ID_INTEL_82801BA_2:
1145 case PCI_DEVICE_ID_INTEL_82801AB_3:
1146 case PCI_DEVICE_ID_INTEL_82801AA_3:
1147 break;
1148 }
1149
1150 /* Disable features on user request */
1151 for (i = 0; i < ARRAY_SIZE(i801_feature_names); i++) {
1152 if (priv->features & disable_features & (1 << i))
1153 dev_notice(&dev->dev, "%s disabled by user\n",
1154 i801_feature_names[i]);
1155 }
1156 priv->features &= ~disable_features;
1157
1158 err = pci_enable_device(dev);
1159 if (err) {
1160 dev_err(&dev->dev, "Failed to enable SMBus PCI device (%d)\n",
1161 err);
1162 goto exit;
1163 }
1164
1165 /* Determine the address of the SMBus area */
1166 priv->smba = pci_resource_start(dev, SMBBAR);
1167 if (!priv->smba) {
1168 dev_err(&dev->dev, "SMBus base address uninitialized, "
1169 "upgrade BIOS\n");
1170 err = -ENODEV;
1171 goto exit;
1172 }
1173
1174 err = acpi_check_resource_conflict(&dev->resource[SMBBAR]);
1175 if (err) {
1176 err = -ENODEV;
1177 goto exit;
1178 }
1179
1180 err = pci_request_region(dev, SMBBAR, i801_driver.name);
1181 if (err) {
1182 dev_err(&dev->dev, "Failed to request SMBus region "
1183 "0x%lx-0x%Lx\n", priv->smba,
1184 (unsigned long long)pci_resource_end(dev, SMBBAR));
1185 goto exit;
1186 }
1187
1188 pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &temp);
1189 priv->original_hstcfg = temp;
1190 temp &= ~SMBHSTCFG_I2C_EN; /* SMBus timing */
1191 if (!(temp & SMBHSTCFG_HST_EN)) {
1192 dev_info(&dev->dev, "Enabling SMBus device\n");
1193 temp |= SMBHSTCFG_HST_EN;
1194 }
1195 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, temp);
1196
1197 if (temp & SMBHSTCFG_SMB_SMI_EN) {
1198 dev_dbg(&dev->dev, "SMBus using interrupt SMI#\n");
1199 /* Disable SMBus interrupt feature if SMBus using SMI# */
1200 priv->features &= ~FEATURE_IRQ;
1201 }
1202
1203 /* Clear special mode bits */
1204 if (priv->features & (FEATURE_SMBUS_PEC | FEATURE_BLOCK_BUFFER))
1205 outb_p(inb_p(SMBAUXCTL(priv)) &
1206 ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv));
1207
1208 if (priv->features & FEATURE_IRQ) {
1209 init_waitqueue_head(&priv->waitq);
1210
1211 err = request_irq(dev->irq, i801_isr, IRQF_SHARED,
1212 i801_driver.name, priv);
1213 if (err) {
1214 dev_err(&dev->dev, "Failed to allocate irq %d: %d\n",
1215 dev->irq, err);
1216 goto exit_release;
1217 }
1218 dev_info(&dev->dev, "SMBus using PCI Interrupt\n");
1219 }
1220
1221 /* set up the sysfs linkage to our parent device */
1222 priv->adapter.dev.parent = &dev->dev;
1223
1224 /* Retry up to 3 times on lost arbitration */
1225 priv->adapter.retries = 3;
1226
1227 snprintf(priv->adapter.name, sizeof(priv->adapter.name),
1228 "SMBus I801 adapter at %04lx", priv->smba);
1229 err = i2c_add_adapter(&priv->adapter);
1230 if (err) {
1231 dev_err(&dev->dev, "Failed to add SMBus adapter\n");
1232 goto exit_free_irq;
1233 }
1234
1235 i801_probe_optional_slaves(priv);
1236 /* We ignore errors - multiplexing is optional */
1237 i801_add_mux(priv);
1238
1239 pci_set_drvdata(dev, priv);
1240
1241 return 0;
1242
1243 exit_free_irq:
1244 if (priv->features & FEATURE_IRQ)
1245 free_irq(dev->irq, priv);
1246 exit_release:
1247 pci_release_region(dev, SMBBAR);
1248 exit:
1249 kfree(priv);
1250 return err;
1251 }
1252
1253 static void i801_remove(struct pci_dev *dev)
1254 {
1255 struct i801_priv *priv = pci_get_drvdata(dev);
1256
1257 i801_del_mux(priv);
1258 i2c_del_adapter(&priv->adapter);
1259 pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg);
1260
1261 if (priv->features & FEATURE_IRQ)
1262 free_irq(dev->irq, priv);
1263 pci_release_region(dev, SMBBAR);
1264
1265 kfree(priv);
1266 /*
1267 * do not call pci_disable_device(dev) since it can cause hard hangs on
1268 * some systems during power-off (eg. Fujitsu-Siemens Lifebook E8010)
1269 */
1270 }
1271
1272 #ifdef CONFIG_PM
1273 static int i801_suspend(struct pci_dev *dev, pm_message_t mesg)
1274 {
1275 struct i801_priv *priv = pci_get_drvdata(dev);
1276
1277 pci_save_state(dev);
1278 pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg);
1279 pci_set_power_state(dev, pci_choose_state(dev, mesg));
1280 return 0;
1281 }
1282
1283 static int i801_resume(struct pci_dev *dev)
1284 {
1285 pci_set_power_state(dev, PCI_D0);
1286 pci_restore_state(dev);
1287 return pci_enable_device(dev);
1288 }
1289 #else
1290 #define i801_suspend NULL
1291 #define i801_resume NULL
1292 #endif
1293
1294 static struct pci_driver i801_driver = {
1295 .name = "i801_smbus",
1296 .id_table = i801_ids,
1297 .probe = i801_probe,
1298 .remove = i801_remove,
1299 .suspend = i801_suspend,
1300 .resume = i801_resume,
1301 };
1302
1303 static int __init i2c_i801_init(void)
1304 {
1305 if (dmi_name_in_vendors("FUJITSU"))
1306 input_apanel_init();
1307 return pci_register_driver(&i801_driver);
1308 }
1309
1310 static void __exit i2c_i801_exit(void)
1311 {
1312 pci_unregister_driver(&i801_driver);
1313 }
1314
1315 MODULE_AUTHOR("Mark D. Studebaker <mdsxyz123@yahoo.com>, Jean Delvare <jdelvare@suse.de>");
1316 MODULE_DESCRIPTION("I801 SMBus driver");
1317 MODULE_LICENSE("GPL");
1318
1319 module_init(i2c_i801_init);
1320 module_exit(i2c_i801_exit);
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