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[mirror_ubuntu-artful-kernel.git] / drivers / i2c / busses / i2c-i801.c
1 /*
2 Copyright (c) 1998 - 2002 Frodo Looijaard <frodol@dds.nl>,
3 Philip Edelbrock <phil@netroedge.com>, and Mark D. Studebaker
4 <mdsxyz123@yahoo.com>
5 Copyright (C) 2007 - 2014 Jean Delvare <jdelvare@suse.de>
6 Copyright (C) 2010 Intel Corporation,
7 David Woodhouse <dwmw2@infradead.org>
8
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2 of the License, or
12 (at your option) any later version.
13
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
18 */
19
20 /*
21 * Supports the following Intel I/O Controller Hubs (ICH):
22 *
23 * I/O Block I2C
24 * region SMBus Block proc. block
25 * Chip name PCI ID size PEC buffer call read
26 * ---------------------------------------------------------------------------
27 * 82801AA (ICH) 0x2413 16 no no no no
28 * 82801AB (ICH0) 0x2423 16 no no no no
29 * 82801BA (ICH2) 0x2443 16 no no no no
30 * 82801CA (ICH3) 0x2483 32 soft no no no
31 * 82801DB (ICH4) 0x24c3 32 hard yes no no
32 * 82801E (ICH5) 0x24d3 32 hard yes yes yes
33 * 6300ESB 0x25a4 32 hard yes yes yes
34 * 82801F (ICH6) 0x266a 32 hard yes yes yes
35 * 6310ESB/6320ESB 0x269b 32 hard yes yes yes
36 * 82801G (ICH7) 0x27da 32 hard yes yes yes
37 * 82801H (ICH8) 0x283e 32 hard yes yes yes
38 * 82801I (ICH9) 0x2930 32 hard yes yes yes
39 * EP80579 (Tolapai) 0x5032 32 hard yes yes yes
40 * ICH10 0x3a30 32 hard yes yes yes
41 * ICH10 0x3a60 32 hard yes yes yes
42 * 5/3400 Series (PCH) 0x3b30 32 hard yes yes yes
43 * 6 Series (PCH) 0x1c22 32 hard yes yes yes
44 * Patsburg (PCH) 0x1d22 32 hard yes yes yes
45 * Patsburg (PCH) IDF 0x1d70 32 hard yes yes yes
46 * Patsburg (PCH) IDF 0x1d71 32 hard yes yes yes
47 * Patsburg (PCH) IDF 0x1d72 32 hard yes yes yes
48 * DH89xxCC (PCH) 0x2330 32 hard yes yes yes
49 * Panther Point (PCH) 0x1e22 32 hard yes yes yes
50 * Lynx Point (PCH) 0x8c22 32 hard yes yes yes
51 * Lynx Point-LP (PCH) 0x9c22 32 hard yes yes yes
52 * Avoton (SOC) 0x1f3c 32 hard yes yes yes
53 * Wellsburg (PCH) 0x8d22 32 hard yes yes yes
54 * Wellsburg (PCH) MS 0x8d7d 32 hard yes yes yes
55 * Wellsburg (PCH) MS 0x8d7e 32 hard yes yes yes
56 * Wellsburg (PCH) MS 0x8d7f 32 hard yes yes yes
57 * Coleto Creek (PCH) 0x23b0 32 hard yes yes yes
58 * Wildcat Point (PCH) 0x8ca2 32 hard yes yes yes
59 * Wildcat Point-LP (PCH) 0x9ca2 32 hard yes yes yes
60 * BayTrail (SOC) 0x0f12 32 hard yes yes yes
61 * Sunrise Point-H (PCH) 0xa123 32 hard yes yes yes
62 * Sunrise Point-LP (PCH) 0x9d23 32 hard yes yes yes
63 * DNV (SOC) 0x19df 32 hard yes yes yes
64 * Broxton (SOC) 0x5ad4 32 hard yes yes yes
65 * Lewisburg (PCH) 0xa1a3 32 hard yes yes yes
66 * Lewisburg Supersku (PCH) 0xa223 32 hard yes yes yes
67 * Kaby Lake PCH-H (PCH) 0xa2a3 32 hard yes yes yes
68 * Gemini Lake (SOC) 0x31d4 32 hard yes yes yes
69 *
70 * Features supported by this driver:
71 * Software PEC no
72 * Hardware PEC yes
73 * Block buffer yes
74 * Block process call transaction no
75 * I2C block read transaction yes (doesn't use the block buffer)
76 * Slave mode no
77 * SMBus Host Notify yes
78 * Interrupt processing yes
79 *
80 * See the file Documentation/i2c/busses/i2c-i801 for details.
81 */
82
83 #include <linux/interrupt.h>
84 #include <linux/module.h>
85 #include <linux/pci.h>
86 #include <linux/kernel.h>
87 #include <linux/stddef.h>
88 #include <linux/delay.h>
89 #include <linux/ioport.h>
90 #include <linux/init.h>
91 #include <linux/i2c.h>
92 #include <linux/i2c-smbus.h>
93 #include <linux/acpi.h>
94 #include <linux/io.h>
95 #include <linux/dmi.h>
96 #include <linux/slab.h>
97 #include <linux/wait.h>
98 #include <linux/err.h>
99 #include <linux/platform_device.h>
100 #include <linux/platform_data/itco_wdt.h>
101 #include <linux/pm_runtime.h>
102
103 #if IS_ENABLED(CONFIG_I2C_MUX_GPIO) && defined CONFIG_DMI
104 #include <linux/gpio.h>
105 #include <linux/i2c-mux-gpio.h>
106 #endif
107
108 /* I801 SMBus address offsets */
109 #define SMBHSTSTS(p) (0 + (p)->smba)
110 #define SMBHSTCNT(p) (2 + (p)->smba)
111 #define SMBHSTCMD(p) (3 + (p)->smba)
112 #define SMBHSTADD(p) (4 + (p)->smba)
113 #define SMBHSTDAT0(p) (5 + (p)->smba)
114 #define SMBHSTDAT1(p) (6 + (p)->smba)
115 #define SMBBLKDAT(p) (7 + (p)->smba)
116 #define SMBPEC(p) (8 + (p)->smba) /* ICH3 and later */
117 #define SMBAUXSTS(p) (12 + (p)->smba) /* ICH4 and later */
118 #define SMBAUXCTL(p) (13 + (p)->smba) /* ICH4 and later */
119 #define SMBSLVSTS(p) (16 + (p)->smba) /* ICH3 and later */
120 #define SMBSLVCMD(p) (17 + (p)->smba) /* ICH3 and later */
121 #define SMBNTFDADD(p) (20 + (p)->smba) /* ICH3 and later */
122
123 /* PCI Address Constants */
124 #define SMBBAR 4
125 #define SMBPCICTL 0x004
126 #define SMBPCISTS 0x006
127 #define SMBHSTCFG 0x040
128 #define TCOBASE 0x050
129 #define TCOCTL 0x054
130
131 #define ACPIBASE 0x040
132 #define ACPIBASE_SMI_OFF 0x030
133 #define ACPICTRL 0x044
134 #define ACPICTRL_EN 0x080
135
136 #define SBREG_BAR 0x10
137 #define SBREG_SMBCTRL 0xc6000c
138
139 /* Host status bits for SMBPCISTS */
140 #define SMBPCISTS_INTS BIT(3)
141
142 /* Control bits for SMBPCICTL */
143 #define SMBPCICTL_INTDIS BIT(10)
144
145 /* Host configuration bits for SMBHSTCFG */
146 #define SMBHSTCFG_HST_EN BIT(0)
147 #define SMBHSTCFG_SMB_SMI_EN BIT(1)
148 #define SMBHSTCFG_I2C_EN BIT(2)
149 #define SMBHSTCFG_SPD_WD BIT(4)
150
151 /* TCO configuration bits for TCOCTL */
152 #define TCOCTL_EN BIT(8)
153
154 /* Auxiliary status register bits, ICH4+ only */
155 #define SMBAUXSTS_CRCE BIT(0)
156 #define SMBAUXSTS_STCO BIT(1)
157
158 /* Auxiliary control register bits, ICH4+ only */
159 #define SMBAUXCTL_CRC BIT(0)
160 #define SMBAUXCTL_E32B BIT(1)
161
162 /* Other settings */
163 #define MAX_RETRIES 400
164
165 /* I801 command constants */
166 #define I801_QUICK 0x00
167 #define I801_BYTE 0x04
168 #define I801_BYTE_DATA 0x08
169 #define I801_WORD_DATA 0x0C
170 #define I801_PROC_CALL 0x10 /* unimplemented */
171 #define I801_BLOCK_DATA 0x14
172 #define I801_I2C_BLOCK_DATA 0x18 /* ICH5 and later */
173
174 /* I801 Host Control register bits */
175 #define SMBHSTCNT_INTREN BIT(0)
176 #define SMBHSTCNT_KILL BIT(1)
177 #define SMBHSTCNT_LAST_BYTE BIT(5)
178 #define SMBHSTCNT_START BIT(6)
179 #define SMBHSTCNT_PEC_EN BIT(7) /* ICH3 and later */
180
181 /* I801 Hosts Status register bits */
182 #define SMBHSTSTS_BYTE_DONE BIT(7)
183 #define SMBHSTSTS_INUSE_STS BIT(6)
184 #define SMBHSTSTS_SMBALERT_STS BIT(5)
185 #define SMBHSTSTS_FAILED BIT(4)
186 #define SMBHSTSTS_BUS_ERR BIT(3)
187 #define SMBHSTSTS_DEV_ERR BIT(2)
188 #define SMBHSTSTS_INTR BIT(1)
189 #define SMBHSTSTS_HOST_BUSY BIT(0)
190
191 /* Host Notify Status register bits */
192 #define SMBSLVSTS_HST_NTFY_STS BIT(0)
193
194 /* Host Notify Command register bits */
195 #define SMBSLVCMD_HST_NTFY_INTREN BIT(0)
196
197 #define STATUS_ERROR_FLAGS (SMBHSTSTS_FAILED | SMBHSTSTS_BUS_ERR | \
198 SMBHSTSTS_DEV_ERR)
199
200 #define STATUS_FLAGS (SMBHSTSTS_BYTE_DONE | SMBHSTSTS_INTR | \
201 STATUS_ERROR_FLAGS)
202
203 /* Older devices have their ID defined in <linux/pci_ids.h> */
204 #define PCI_DEVICE_ID_INTEL_BAYTRAIL_SMBUS 0x0f12
205 #define PCI_DEVICE_ID_INTEL_DNV_SMBUS 0x19df
206 #define PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS 0x1c22
207 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS 0x1d22
208 /* Patsburg also has three 'Integrated Device Function' SMBus controllers */
209 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0 0x1d70
210 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1 0x1d71
211 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2 0x1d72
212 #define PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS 0x1e22
213 #define PCI_DEVICE_ID_INTEL_AVOTON_SMBUS 0x1f3c
214 #define PCI_DEVICE_ID_INTEL_BRASWELL_SMBUS 0x2292
215 #define PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS 0x2330
216 #define PCI_DEVICE_ID_INTEL_COLETOCREEK_SMBUS 0x23b0
217 #define PCI_DEVICE_ID_INTEL_GEMINILAKE_SMBUS 0x31d4
218 #define PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS 0x3b30
219 #define PCI_DEVICE_ID_INTEL_BROXTON_SMBUS 0x5ad4
220 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS 0x8c22
221 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_SMBUS 0x8ca2
222 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS 0x8d22
223 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0 0x8d7d
224 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1 0x8d7e
225 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2 0x8d7f
226 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS 0x9c22
227 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_SMBUS 0x9ca2
228 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS 0x9d23
229 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS 0xa123
230 #define PCI_DEVICE_ID_INTEL_LEWISBURG_SMBUS 0xa1a3
231 #define PCI_DEVICE_ID_INTEL_LEWISBURG_SSKU_SMBUS 0xa223
232 #define PCI_DEVICE_ID_INTEL_KABYLAKE_PCH_H_SMBUS 0xa2a3
233
234 struct i801_mux_config {
235 char *gpio_chip;
236 unsigned values[3];
237 int n_values;
238 unsigned classes[3];
239 unsigned gpios[2]; /* Relative to gpio_chip->base */
240 int n_gpios;
241 };
242
243 struct i801_priv {
244 struct i2c_adapter adapter;
245 unsigned long smba;
246 unsigned char original_hstcfg;
247 unsigned char original_slvcmd;
248 struct pci_dev *pci_dev;
249 unsigned int features;
250
251 /* isr processing */
252 wait_queue_head_t waitq;
253 u8 status;
254
255 /* Command state used by isr for byte-by-byte block transactions */
256 u8 cmd;
257 bool is_read;
258 int count;
259 int len;
260 u8 *data;
261
262 #if IS_ENABLED(CONFIG_I2C_MUX_GPIO) && defined CONFIG_DMI
263 const struct i801_mux_config *mux_drvdata;
264 struct platform_device *mux_pdev;
265 #endif
266 struct platform_device *tco_pdev;
267
268 /*
269 * If set to true the host controller registers are reserved for
270 * ACPI AML use. Protected by acpi_lock.
271 */
272 bool acpi_reserved;
273 struct mutex acpi_lock;
274 };
275
276 #define FEATURE_SMBUS_PEC BIT(0)
277 #define FEATURE_BLOCK_BUFFER BIT(1)
278 #define FEATURE_BLOCK_PROC BIT(2)
279 #define FEATURE_I2C_BLOCK_READ BIT(3)
280 #define FEATURE_IRQ BIT(4)
281 #define FEATURE_HOST_NOTIFY BIT(5)
282 /* Not really a feature, but it's convenient to handle it as such */
283 #define FEATURE_IDF BIT(15)
284 #define FEATURE_TCO BIT(16)
285
286 static const char *i801_feature_names[] = {
287 "SMBus PEC",
288 "Block buffer",
289 "Block process call",
290 "I2C block read",
291 "Interrupt",
292 "SMBus Host Notify",
293 };
294
295 static unsigned int disable_features;
296 module_param(disable_features, uint, S_IRUGO | S_IWUSR);
297 MODULE_PARM_DESC(disable_features, "Disable selected driver features:\n"
298 "\t\t 0x01 disable SMBus PEC\n"
299 "\t\t 0x02 disable the block buffer\n"
300 "\t\t 0x08 disable the I2C block read functionality\n"
301 "\t\t 0x10 don't use interrupts\n"
302 "\t\t 0x20 disable SMBus Host Notify ");
303
304 /* Make sure the SMBus host is ready to start transmitting.
305 Return 0 if it is, -EBUSY if it is not. */
306 static int i801_check_pre(struct i801_priv *priv)
307 {
308 int status;
309
310 status = inb_p(SMBHSTSTS(priv));
311 if (status & SMBHSTSTS_HOST_BUSY) {
312 dev_err(&priv->pci_dev->dev, "SMBus is busy, can't use it!\n");
313 return -EBUSY;
314 }
315
316 status &= STATUS_FLAGS;
317 if (status) {
318 dev_dbg(&priv->pci_dev->dev, "Clearing status flags (%02x)\n",
319 status);
320 outb_p(status, SMBHSTSTS(priv));
321 status = inb_p(SMBHSTSTS(priv)) & STATUS_FLAGS;
322 if (status) {
323 dev_err(&priv->pci_dev->dev,
324 "Failed clearing status flags (%02x)\n",
325 status);
326 return -EBUSY;
327 }
328 }
329
330 /*
331 * Clear CRC status if needed.
332 * During normal operation, i801_check_post() takes care
333 * of it after every operation. We do it here only in case
334 * the hardware was already in this state when the driver
335 * started.
336 */
337 if (priv->features & FEATURE_SMBUS_PEC) {
338 status = inb_p(SMBAUXSTS(priv)) & SMBAUXSTS_CRCE;
339 if (status) {
340 dev_dbg(&priv->pci_dev->dev,
341 "Clearing aux status flags (%02x)\n", status);
342 outb_p(status, SMBAUXSTS(priv));
343 status = inb_p(SMBAUXSTS(priv)) & SMBAUXSTS_CRCE;
344 if (status) {
345 dev_err(&priv->pci_dev->dev,
346 "Failed clearing aux status flags (%02x)\n",
347 status);
348 return -EBUSY;
349 }
350 }
351 }
352
353 return 0;
354 }
355
356 /*
357 * Convert the status register to an error code, and clear it.
358 * Note that status only contains the bits we want to clear, not the
359 * actual register value.
360 */
361 static int i801_check_post(struct i801_priv *priv, int status)
362 {
363 int result = 0;
364
365 /*
366 * If the SMBus is still busy, we give up
367 * Note: This timeout condition only happens when using polling
368 * transactions. For interrupt operation, NAK/timeout is indicated by
369 * DEV_ERR.
370 */
371 if (unlikely(status < 0)) {
372 dev_err(&priv->pci_dev->dev, "Transaction timeout\n");
373 /* try to stop the current command */
374 dev_dbg(&priv->pci_dev->dev, "Terminating the current operation\n");
375 outb_p(inb_p(SMBHSTCNT(priv)) | SMBHSTCNT_KILL,
376 SMBHSTCNT(priv));
377 usleep_range(1000, 2000);
378 outb_p(inb_p(SMBHSTCNT(priv)) & (~SMBHSTCNT_KILL),
379 SMBHSTCNT(priv));
380
381 /* Check if it worked */
382 status = inb_p(SMBHSTSTS(priv));
383 if ((status & SMBHSTSTS_HOST_BUSY) ||
384 !(status & SMBHSTSTS_FAILED))
385 dev_err(&priv->pci_dev->dev,
386 "Failed terminating the transaction\n");
387 outb_p(STATUS_FLAGS, SMBHSTSTS(priv));
388 return -ETIMEDOUT;
389 }
390
391 if (status & SMBHSTSTS_FAILED) {
392 result = -EIO;
393 dev_err(&priv->pci_dev->dev, "Transaction failed\n");
394 }
395 if (status & SMBHSTSTS_DEV_ERR) {
396 /*
397 * This may be a PEC error, check and clear it.
398 *
399 * AUXSTS is handled differently from HSTSTS.
400 * For HSTSTS, i801_isr() or i801_wait_intr()
401 * has already cleared the error bits in hardware,
402 * and we are passed a copy of the original value
403 * in "status".
404 * For AUXSTS, the hardware register is left
405 * for us to handle here.
406 * This is asymmetric, slightly iffy, but safe,
407 * since all this code is serialized and the CRCE
408 * bit is harmless as long as it's cleared before
409 * the next operation.
410 */
411 if ((priv->features & FEATURE_SMBUS_PEC) &&
412 (inb_p(SMBAUXSTS(priv)) & SMBAUXSTS_CRCE)) {
413 outb_p(SMBAUXSTS_CRCE, SMBAUXSTS(priv));
414 result = -EBADMSG;
415 dev_dbg(&priv->pci_dev->dev, "PEC error\n");
416 } else {
417 result = -ENXIO;
418 dev_dbg(&priv->pci_dev->dev, "No response\n");
419 }
420 }
421 if (status & SMBHSTSTS_BUS_ERR) {
422 result = -EAGAIN;
423 dev_dbg(&priv->pci_dev->dev, "Lost arbitration\n");
424 }
425
426 /* Clear status flags except BYTE_DONE, to be cleared by caller */
427 outb_p(status, SMBHSTSTS(priv));
428
429 return result;
430 }
431
432 /* Wait for BUSY being cleared and either INTR or an error flag being set */
433 static int i801_wait_intr(struct i801_priv *priv)
434 {
435 int timeout = 0;
436 int status;
437
438 /* We will always wait for a fraction of a second! */
439 do {
440 usleep_range(250, 500);
441 status = inb_p(SMBHSTSTS(priv));
442 } while (((status & SMBHSTSTS_HOST_BUSY) ||
443 !(status & (STATUS_ERROR_FLAGS | SMBHSTSTS_INTR))) &&
444 (timeout++ < MAX_RETRIES));
445
446 if (timeout > MAX_RETRIES) {
447 dev_dbg(&priv->pci_dev->dev, "INTR Timeout!\n");
448 return -ETIMEDOUT;
449 }
450 return status & (STATUS_ERROR_FLAGS | SMBHSTSTS_INTR);
451 }
452
453 /* Wait for either BYTE_DONE or an error flag being set */
454 static int i801_wait_byte_done(struct i801_priv *priv)
455 {
456 int timeout = 0;
457 int status;
458
459 /* We will always wait for a fraction of a second! */
460 do {
461 usleep_range(250, 500);
462 status = inb_p(SMBHSTSTS(priv));
463 } while (!(status & (STATUS_ERROR_FLAGS | SMBHSTSTS_BYTE_DONE)) &&
464 (timeout++ < MAX_RETRIES));
465
466 if (timeout > MAX_RETRIES) {
467 dev_dbg(&priv->pci_dev->dev, "BYTE_DONE Timeout!\n");
468 return -ETIMEDOUT;
469 }
470 return status & STATUS_ERROR_FLAGS;
471 }
472
473 static int i801_transaction(struct i801_priv *priv, int xact)
474 {
475 int status;
476 int result;
477 const struct i2c_adapter *adap = &priv->adapter;
478
479 result = i801_check_pre(priv);
480 if (result < 0)
481 return result;
482
483 if (priv->features & FEATURE_IRQ) {
484 outb_p(xact | SMBHSTCNT_INTREN | SMBHSTCNT_START,
485 SMBHSTCNT(priv));
486 result = wait_event_timeout(priv->waitq,
487 (status = priv->status),
488 adap->timeout);
489 if (!result) {
490 status = -ETIMEDOUT;
491 dev_warn(&priv->pci_dev->dev,
492 "Timeout waiting for interrupt!\n");
493 }
494 priv->status = 0;
495 return i801_check_post(priv, status);
496 }
497
498 /* the current contents of SMBHSTCNT can be overwritten, since PEC,
499 * SMBSCMD are passed in xact */
500 outb_p(xact | SMBHSTCNT_START, SMBHSTCNT(priv));
501
502 status = i801_wait_intr(priv);
503 return i801_check_post(priv, status);
504 }
505
506 static int i801_block_transaction_by_block(struct i801_priv *priv,
507 union i2c_smbus_data *data,
508 char read_write, int hwpec)
509 {
510 int i, len;
511 int status;
512
513 inb_p(SMBHSTCNT(priv)); /* reset the data buffer index */
514
515 /* Use 32-byte buffer to process this transaction */
516 if (read_write == I2C_SMBUS_WRITE) {
517 len = data->block[0];
518 outb_p(len, SMBHSTDAT0(priv));
519 for (i = 0; i < len; i++)
520 outb_p(data->block[i+1], SMBBLKDAT(priv));
521 }
522
523 status = i801_transaction(priv, I801_BLOCK_DATA |
524 (hwpec ? SMBHSTCNT_PEC_EN : 0));
525 if (status)
526 return status;
527
528 if (read_write == I2C_SMBUS_READ) {
529 len = inb_p(SMBHSTDAT0(priv));
530 if (len < 1 || len > I2C_SMBUS_BLOCK_MAX)
531 return -EPROTO;
532
533 data->block[0] = len;
534 for (i = 0; i < len; i++)
535 data->block[i + 1] = inb_p(SMBBLKDAT(priv));
536 }
537 return 0;
538 }
539
540 static void i801_isr_byte_done(struct i801_priv *priv)
541 {
542 if (priv->is_read) {
543 /* For SMBus block reads, length is received with first byte */
544 if (((priv->cmd & 0x1c) == I801_BLOCK_DATA) &&
545 (priv->count == 0)) {
546 priv->len = inb_p(SMBHSTDAT0(priv));
547 if (priv->len < 1 || priv->len > I2C_SMBUS_BLOCK_MAX) {
548 dev_err(&priv->pci_dev->dev,
549 "Illegal SMBus block read size %d\n",
550 priv->len);
551 /* FIXME: Recover */
552 priv->len = I2C_SMBUS_BLOCK_MAX;
553 } else {
554 dev_dbg(&priv->pci_dev->dev,
555 "SMBus block read size is %d\n",
556 priv->len);
557 }
558 priv->data[-1] = priv->len;
559 }
560
561 /* Read next byte */
562 if (priv->count < priv->len)
563 priv->data[priv->count++] = inb(SMBBLKDAT(priv));
564 else
565 dev_dbg(&priv->pci_dev->dev,
566 "Discarding extra byte on block read\n");
567
568 /* Set LAST_BYTE for last byte of read transaction */
569 if (priv->count == priv->len - 1)
570 outb_p(priv->cmd | SMBHSTCNT_LAST_BYTE,
571 SMBHSTCNT(priv));
572 } else if (priv->count < priv->len - 1) {
573 /* Write next byte, except for IRQ after last byte */
574 outb_p(priv->data[++priv->count], SMBBLKDAT(priv));
575 }
576
577 /* Clear BYTE_DONE to continue with next byte */
578 outb_p(SMBHSTSTS_BYTE_DONE, SMBHSTSTS(priv));
579 }
580
581 static irqreturn_t i801_host_notify_isr(struct i801_priv *priv)
582 {
583 unsigned short addr;
584
585 addr = inb_p(SMBNTFDADD(priv)) >> 1;
586
587 /*
588 * With the tested platforms, reading SMBNTFDDAT (22 + (p)->smba)
589 * always returns 0. Our current implementation doesn't provide
590 * data, so we just ignore it.
591 */
592 i2c_handle_smbus_host_notify(&priv->adapter, addr);
593
594 /* clear Host Notify bit and return */
595 outb_p(SMBSLVSTS_HST_NTFY_STS, SMBSLVSTS(priv));
596 return IRQ_HANDLED;
597 }
598
599 /*
600 * There are three kinds of interrupts:
601 *
602 * 1) i801 signals transaction completion with one of these interrupts:
603 * INTR - Success
604 * DEV_ERR - Invalid command, NAK or communication timeout
605 * BUS_ERR - SMI# transaction collision
606 * FAILED - transaction was canceled due to a KILL request
607 * When any of these occur, update ->status and wake up the waitq.
608 * ->status must be cleared before kicking off the next transaction.
609 *
610 * 2) For byte-by-byte (I2C read/write) transactions, one BYTE_DONE interrupt
611 * occurs for each byte of a byte-by-byte to prepare the next byte.
612 *
613 * 3) Host Notify interrupts
614 */
615 static irqreturn_t i801_isr(int irq, void *dev_id)
616 {
617 struct i801_priv *priv = dev_id;
618 u16 pcists;
619 u8 status;
620
621 /* Confirm this is our interrupt */
622 pci_read_config_word(priv->pci_dev, SMBPCISTS, &pcists);
623 if (!(pcists & SMBPCISTS_INTS))
624 return IRQ_NONE;
625
626 if (priv->features & FEATURE_HOST_NOTIFY) {
627 status = inb_p(SMBSLVSTS(priv));
628 if (status & SMBSLVSTS_HST_NTFY_STS)
629 return i801_host_notify_isr(priv);
630 }
631
632 status = inb_p(SMBHSTSTS(priv));
633 if (status & SMBHSTSTS_BYTE_DONE)
634 i801_isr_byte_done(priv);
635
636 /*
637 * Clear irq sources and report transaction result.
638 * ->status must be cleared before the next transaction is started.
639 */
640 status &= SMBHSTSTS_INTR | STATUS_ERROR_FLAGS;
641 if (status) {
642 outb_p(status, SMBHSTSTS(priv));
643 priv->status = status;
644 wake_up(&priv->waitq);
645 }
646
647 return IRQ_HANDLED;
648 }
649
650 /*
651 * For "byte-by-byte" block transactions:
652 * I2C write uses cmd=I801_BLOCK_DATA, I2C_EN=1
653 * I2C read uses cmd=I801_I2C_BLOCK_DATA
654 */
655 static int i801_block_transaction_byte_by_byte(struct i801_priv *priv,
656 union i2c_smbus_data *data,
657 char read_write, int command,
658 int hwpec)
659 {
660 int i, len;
661 int smbcmd;
662 int status;
663 int result;
664 const struct i2c_adapter *adap = &priv->adapter;
665
666 result = i801_check_pre(priv);
667 if (result < 0)
668 return result;
669
670 len = data->block[0];
671
672 if (read_write == I2C_SMBUS_WRITE) {
673 outb_p(len, SMBHSTDAT0(priv));
674 outb_p(data->block[1], SMBBLKDAT(priv));
675 }
676
677 if (command == I2C_SMBUS_I2C_BLOCK_DATA &&
678 read_write == I2C_SMBUS_READ)
679 smbcmd = I801_I2C_BLOCK_DATA;
680 else
681 smbcmd = I801_BLOCK_DATA;
682
683 if (priv->features & FEATURE_IRQ) {
684 priv->is_read = (read_write == I2C_SMBUS_READ);
685 if (len == 1 && priv->is_read)
686 smbcmd |= SMBHSTCNT_LAST_BYTE;
687 priv->cmd = smbcmd | SMBHSTCNT_INTREN;
688 priv->len = len;
689 priv->count = 0;
690 priv->data = &data->block[1];
691
692 outb_p(priv->cmd | SMBHSTCNT_START, SMBHSTCNT(priv));
693 result = wait_event_timeout(priv->waitq,
694 (status = priv->status),
695 adap->timeout);
696 if (!result) {
697 status = -ETIMEDOUT;
698 dev_warn(&priv->pci_dev->dev,
699 "Timeout waiting for interrupt!\n");
700 }
701 priv->status = 0;
702 return i801_check_post(priv, status);
703 }
704
705 for (i = 1; i <= len; i++) {
706 if (i == len && read_write == I2C_SMBUS_READ)
707 smbcmd |= SMBHSTCNT_LAST_BYTE;
708 outb_p(smbcmd, SMBHSTCNT(priv));
709
710 if (i == 1)
711 outb_p(inb(SMBHSTCNT(priv)) | SMBHSTCNT_START,
712 SMBHSTCNT(priv));
713
714 status = i801_wait_byte_done(priv);
715 if (status)
716 goto exit;
717
718 if (i == 1 && read_write == I2C_SMBUS_READ
719 && command != I2C_SMBUS_I2C_BLOCK_DATA) {
720 len = inb_p(SMBHSTDAT0(priv));
721 if (len < 1 || len > I2C_SMBUS_BLOCK_MAX) {
722 dev_err(&priv->pci_dev->dev,
723 "Illegal SMBus block read size %d\n",
724 len);
725 /* Recover */
726 while (inb_p(SMBHSTSTS(priv)) &
727 SMBHSTSTS_HOST_BUSY)
728 outb_p(SMBHSTSTS_BYTE_DONE,
729 SMBHSTSTS(priv));
730 outb_p(SMBHSTSTS_INTR, SMBHSTSTS(priv));
731 return -EPROTO;
732 }
733 data->block[0] = len;
734 }
735
736 /* Retrieve/store value in SMBBLKDAT */
737 if (read_write == I2C_SMBUS_READ)
738 data->block[i] = inb_p(SMBBLKDAT(priv));
739 if (read_write == I2C_SMBUS_WRITE && i+1 <= len)
740 outb_p(data->block[i+1], SMBBLKDAT(priv));
741
742 /* signals SMBBLKDAT ready */
743 outb_p(SMBHSTSTS_BYTE_DONE, SMBHSTSTS(priv));
744 }
745
746 status = i801_wait_intr(priv);
747 exit:
748 return i801_check_post(priv, status);
749 }
750
751 static int i801_set_block_buffer_mode(struct i801_priv *priv)
752 {
753 outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_E32B, SMBAUXCTL(priv));
754 if ((inb_p(SMBAUXCTL(priv)) & SMBAUXCTL_E32B) == 0)
755 return -EIO;
756 return 0;
757 }
758
759 /* Block transaction function */
760 static int i801_block_transaction(struct i801_priv *priv,
761 union i2c_smbus_data *data, char read_write,
762 int command, int hwpec)
763 {
764 int result = 0;
765 unsigned char hostc;
766
767 if (command == I2C_SMBUS_I2C_BLOCK_DATA) {
768 if (read_write == I2C_SMBUS_WRITE) {
769 /* set I2C_EN bit in configuration register */
770 pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &hostc);
771 pci_write_config_byte(priv->pci_dev, SMBHSTCFG,
772 hostc | SMBHSTCFG_I2C_EN);
773 } else if (!(priv->features & FEATURE_I2C_BLOCK_READ)) {
774 dev_err(&priv->pci_dev->dev,
775 "I2C block read is unsupported!\n");
776 return -EOPNOTSUPP;
777 }
778 }
779
780 if (read_write == I2C_SMBUS_WRITE
781 || command == I2C_SMBUS_I2C_BLOCK_DATA) {
782 if (data->block[0] < 1)
783 data->block[0] = 1;
784 if (data->block[0] > I2C_SMBUS_BLOCK_MAX)
785 data->block[0] = I2C_SMBUS_BLOCK_MAX;
786 } else {
787 data->block[0] = 32; /* max for SMBus block reads */
788 }
789
790 /* Experience has shown that the block buffer can only be used for
791 SMBus (not I2C) block transactions, even though the datasheet
792 doesn't mention this limitation. */
793 if ((priv->features & FEATURE_BLOCK_BUFFER)
794 && command != I2C_SMBUS_I2C_BLOCK_DATA
795 && i801_set_block_buffer_mode(priv) == 0)
796 result = i801_block_transaction_by_block(priv, data,
797 read_write, hwpec);
798 else
799 result = i801_block_transaction_byte_by_byte(priv, data,
800 read_write,
801 command, hwpec);
802
803 if (command == I2C_SMBUS_I2C_BLOCK_DATA
804 && read_write == I2C_SMBUS_WRITE) {
805 /* restore saved configuration register value */
806 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, hostc);
807 }
808 return result;
809 }
810
811 /* Return negative errno on error. */
812 static s32 i801_access(struct i2c_adapter *adap, u16 addr,
813 unsigned short flags, char read_write, u8 command,
814 int size, union i2c_smbus_data *data)
815 {
816 int hwpec;
817 int block = 0;
818 int ret = 0, xact = 0;
819 struct i801_priv *priv = i2c_get_adapdata(adap);
820
821 mutex_lock(&priv->acpi_lock);
822 if (priv->acpi_reserved) {
823 mutex_unlock(&priv->acpi_lock);
824 return -EBUSY;
825 }
826
827 pm_runtime_get_sync(&priv->pci_dev->dev);
828
829 hwpec = (priv->features & FEATURE_SMBUS_PEC) && (flags & I2C_CLIENT_PEC)
830 && size != I2C_SMBUS_QUICK
831 && size != I2C_SMBUS_I2C_BLOCK_DATA;
832
833 switch (size) {
834 case I2C_SMBUS_QUICK:
835 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
836 SMBHSTADD(priv));
837 xact = I801_QUICK;
838 break;
839 case I2C_SMBUS_BYTE:
840 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
841 SMBHSTADD(priv));
842 if (read_write == I2C_SMBUS_WRITE)
843 outb_p(command, SMBHSTCMD(priv));
844 xact = I801_BYTE;
845 break;
846 case I2C_SMBUS_BYTE_DATA:
847 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
848 SMBHSTADD(priv));
849 outb_p(command, SMBHSTCMD(priv));
850 if (read_write == I2C_SMBUS_WRITE)
851 outb_p(data->byte, SMBHSTDAT0(priv));
852 xact = I801_BYTE_DATA;
853 break;
854 case I2C_SMBUS_WORD_DATA:
855 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
856 SMBHSTADD(priv));
857 outb_p(command, SMBHSTCMD(priv));
858 if (read_write == I2C_SMBUS_WRITE) {
859 outb_p(data->word & 0xff, SMBHSTDAT0(priv));
860 outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1(priv));
861 }
862 xact = I801_WORD_DATA;
863 break;
864 case I2C_SMBUS_BLOCK_DATA:
865 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
866 SMBHSTADD(priv));
867 outb_p(command, SMBHSTCMD(priv));
868 block = 1;
869 break;
870 case I2C_SMBUS_I2C_BLOCK_DATA:
871 /*
872 * NB: page 240 of ICH5 datasheet shows that the R/#W
873 * bit should be cleared here, even when reading.
874 * However if SPD Write Disable is set (Lynx Point and later),
875 * the read will fail if we don't set the R/#W bit.
876 */
877 outb_p(((addr & 0x7f) << 1) |
878 ((priv->original_hstcfg & SMBHSTCFG_SPD_WD) ?
879 (read_write & 0x01) : 0),
880 SMBHSTADD(priv));
881 if (read_write == I2C_SMBUS_READ) {
882 /* NB: page 240 of ICH5 datasheet also shows
883 * that DATA1 is the cmd field when reading */
884 outb_p(command, SMBHSTDAT1(priv));
885 } else
886 outb_p(command, SMBHSTCMD(priv));
887 block = 1;
888 break;
889 default:
890 dev_err(&priv->pci_dev->dev, "Unsupported transaction %d\n",
891 size);
892 ret = -EOPNOTSUPP;
893 goto out;
894 }
895
896 if (hwpec) /* enable/disable hardware PEC */
897 outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_CRC, SMBAUXCTL(priv));
898 else
899 outb_p(inb_p(SMBAUXCTL(priv)) & (~SMBAUXCTL_CRC),
900 SMBAUXCTL(priv));
901
902 if (block)
903 ret = i801_block_transaction(priv, data, read_write, size,
904 hwpec);
905 else
906 ret = i801_transaction(priv, xact);
907
908 /* Some BIOSes don't like it when PEC is enabled at reboot or resume
909 time, so we forcibly disable it after every transaction. Turn off
910 E32B for the same reason. */
911 if (hwpec || block)
912 outb_p(inb_p(SMBAUXCTL(priv)) &
913 ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv));
914
915 if (block)
916 goto out;
917 if (ret)
918 goto out;
919 if ((read_write == I2C_SMBUS_WRITE) || (xact == I801_QUICK))
920 goto out;
921
922 switch (xact & 0x7f) {
923 case I801_BYTE: /* Result put in SMBHSTDAT0 */
924 case I801_BYTE_DATA:
925 data->byte = inb_p(SMBHSTDAT0(priv));
926 break;
927 case I801_WORD_DATA:
928 data->word = inb_p(SMBHSTDAT0(priv)) +
929 (inb_p(SMBHSTDAT1(priv)) << 8);
930 break;
931 }
932
933 out:
934 pm_runtime_mark_last_busy(&priv->pci_dev->dev);
935 pm_runtime_put_autosuspend(&priv->pci_dev->dev);
936 mutex_unlock(&priv->acpi_lock);
937 return ret;
938 }
939
940
941 static u32 i801_func(struct i2c_adapter *adapter)
942 {
943 struct i801_priv *priv = i2c_get_adapdata(adapter);
944
945 return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
946 I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
947 I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_WRITE_I2C_BLOCK |
948 ((priv->features & FEATURE_SMBUS_PEC) ? I2C_FUNC_SMBUS_PEC : 0) |
949 ((priv->features & FEATURE_I2C_BLOCK_READ) ?
950 I2C_FUNC_SMBUS_READ_I2C_BLOCK : 0) |
951 ((priv->features & FEATURE_HOST_NOTIFY) ?
952 I2C_FUNC_SMBUS_HOST_NOTIFY : 0);
953 }
954
955 static void i801_enable_host_notify(struct i2c_adapter *adapter)
956 {
957 struct i801_priv *priv = i2c_get_adapdata(adapter);
958
959 if (!(priv->features & FEATURE_HOST_NOTIFY))
960 return;
961
962 priv->original_slvcmd = inb_p(SMBSLVCMD(priv));
963
964 if (!(SMBSLVCMD_HST_NTFY_INTREN & priv->original_slvcmd))
965 outb_p(SMBSLVCMD_HST_NTFY_INTREN | priv->original_slvcmd,
966 SMBSLVCMD(priv));
967
968 /* clear Host Notify bit to allow a new notification */
969 outb_p(SMBSLVSTS_HST_NTFY_STS, SMBSLVSTS(priv));
970 }
971
972 static void i801_disable_host_notify(struct i801_priv *priv)
973 {
974 if (!(priv->features & FEATURE_HOST_NOTIFY))
975 return;
976
977 outb_p(priv->original_slvcmd, SMBSLVCMD(priv));
978 }
979
980 static const struct i2c_algorithm smbus_algorithm = {
981 .smbus_xfer = i801_access,
982 .functionality = i801_func,
983 };
984
985 static const struct pci_device_id i801_ids[] = {
986 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_3) },
987 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_3) },
988 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_2) },
989 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_3) },
990 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_3) },
991 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_3) },
992 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_4) },
993 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_16) },
994 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_17) },
995 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_17) },
996 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_5) },
997 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_6) },
998 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EP80579_1) },
999 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_4) },
1000 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_5) },
1001 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS) },
1002 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS) },
1003 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS) },
1004 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0) },
1005 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1) },
1006 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2) },
1007 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS) },
1008 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS) },
1009 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS) },
1010 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS) },
1011 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_AVOTON_SMBUS) },
1012 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS) },
1013 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0) },
1014 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1) },
1015 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2) },
1016 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COLETOCREEK_SMBUS) },
1017 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_GEMINILAKE_SMBUS) },
1018 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WILDCATPOINT_SMBUS) },
1019 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_SMBUS) },
1020 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BAYTRAIL_SMBUS) },
1021 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BRASWELL_SMBUS) },
1022 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS) },
1023 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS) },
1024 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_DNV_SMBUS) },
1025 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BROXTON_SMBUS) },
1026 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LEWISBURG_SMBUS) },
1027 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LEWISBURG_SSKU_SMBUS) },
1028 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_KABYLAKE_PCH_H_SMBUS) },
1029 { 0, }
1030 };
1031
1032 MODULE_DEVICE_TABLE(pci, i801_ids);
1033
1034 #if defined CONFIG_X86 && defined CONFIG_DMI
1035 static unsigned char apanel_addr;
1036
1037 /* Scan the system ROM for the signature "FJKEYINF" */
1038 static __init const void __iomem *bios_signature(const void __iomem *bios)
1039 {
1040 ssize_t offset;
1041 const unsigned char signature[] = "FJKEYINF";
1042
1043 for (offset = 0; offset < 0x10000; offset += 0x10) {
1044 if (check_signature(bios + offset, signature,
1045 sizeof(signature)-1))
1046 return bios + offset;
1047 }
1048 return NULL;
1049 }
1050
1051 static void __init input_apanel_init(void)
1052 {
1053 void __iomem *bios;
1054 const void __iomem *p;
1055
1056 bios = ioremap(0xF0000, 0x10000); /* Can't fail */
1057 p = bios_signature(bios);
1058 if (p) {
1059 /* just use the first address */
1060 apanel_addr = readb(p + 8 + 3) >> 1;
1061 }
1062 iounmap(bios);
1063 }
1064
1065 struct dmi_onboard_device_info {
1066 const char *name;
1067 u8 type;
1068 unsigned short i2c_addr;
1069 const char *i2c_type;
1070 };
1071
1072 static const struct dmi_onboard_device_info dmi_devices[] = {
1073 { "Syleus", DMI_DEV_TYPE_OTHER, 0x73, "fscsyl" },
1074 { "Hermes", DMI_DEV_TYPE_OTHER, 0x73, "fscher" },
1075 { "Hades", DMI_DEV_TYPE_OTHER, 0x73, "fschds" },
1076 };
1077
1078 static void dmi_check_onboard_device(u8 type, const char *name,
1079 struct i2c_adapter *adap)
1080 {
1081 int i;
1082 struct i2c_board_info info;
1083
1084 for (i = 0; i < ARRAY_SIZE(dmi_devices); i++) {
1085 /* & ~0x80, ignore enabled/disabled bit */
1086 if ((type & ~0x80) != dmi_devices[i].type)
1087 continue;
1088 if (strcasecmp(name, dmi_devices[i].name))
1089 continue;
1090
1091 memset(&info, 0, sizeof(struct i2c_board_info));
1092 info.addr = dmi_devices[i].i2c_addr;
1093 strlcpy(info.type, dmi_devices[i].i2c_type, I2C_NAME_SIZE);
1094 i2c_new_device(adap, &info);
1095 break;
1096 }
1097 }
1098
1099 /* We use our own function to check for onboard devices instead of
1100 dmi_find_device() as some buggy BIOS's have the devices we are interested
1101 in marked as disabled */
1102 static void dmi_check_onboard_devices(const struct dmi_header *dm, void *adap)
1103 {
1104 int i, count;
1105
1106 if (dm->type != 10)
1107 return;
1108
1109 count = (dm->length - sizeof(struct dmi_header)) / 2;
1110 for (i = 0; i < count; i++) {
1111 const u8 *d = (char *)(dm + 1) + (i * 2);
1112 const char *name = ((char *) dm) + dm->length;
1113 u8 type = d[0];
1114 u8 s = d[1];
1115
1116 if (!s)
1117 continue;
1118 s--;
1119 while (s > 0 && name[0]) {
1120 name += strlen(name) + 1;
1121 s--;
1122 }
1123 if (name[0] == 0) /* Bogus string reference */
1124 continue;
1125
1126 dmi_check_onboard_device(type, name, adap);
1127 }
1128 }
1129
1130 /* Register optional slaves */
1131 static void i801_probe_optional_slaves(struct i801_priv *priv)
1132 {
1133 /* Only register slaves on main SMBus channel */
1134 if (priv->features & FEATURE_IDF)
1135 return;
1136
1137 if (apanel_addr) {
1138 struct i2c_board_info info;
1139
1140 memset(&info, 0, sizeof(struct i2c_board_info));
1141 info.addr = apanel_addr;
1142 strlcpy(info.type, "fujitsu_apanel", I2C_NAME_SIZE);
1143 i2c_new_device(&priv->adapter, &info);
1144 }
1145
1146 if (dmi_name_in_vendors("FUJITSU"))
1147 dmi_walk(dmi_check_onboard_devices, &priv->adapter);
1148 }
1149 #else
1150 static void __init input_apanel_init(void) {}
1151 static void i801_probe_optional_slaves(struct i801_priv *priv) {}
1152 #endif /* CONFIG_X86 && CONFIG_DMI */
1153
1154 #if IS_ENABLED(CONFIG_I2C_MUX_GPIO) && defined CONFIG_DMI
1155 static struct i801_mux_config i801_mux_config_asus_z8_d12 = {
1156 .gpio_chip = "gpio_ich",
1157 .values = { 0x02, 0x03 },
1158 .n_values = 2,
1159 .classes = { I2C_CLASS_SPD, I2C_CLASS_SPD },
1160 .gpios = { 52, 53 },
1161 .n_gpios = 2,
1162 };
1163
1164 static struct i801_mux_config i801_mux_config_asus_z8_d18 = {
1165 .gpio_chip = "gpio_ich",
1166 .values = { 0x02, 0x03, 0x01 },
1167 .n_values = 3,
1168 .classes = { I2C_CLASS_SPD, I2C_CLASS_SPD, I2C_CLASS_SPD },
1169 .gpios = { 52, 53 },
1170 .n_gpios = 2,
1171 };
1172
1173 static const struct dmi_system_id mux_dmi_table[] = {
1174 {
1175 .matches = {
1176 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1177 DMI_MATCH(DMI_BOARD_NAME, "Z8NA-D6(C)"),
1178 },
1179 .driver_data = &i801_mux_config_asus_z8_d12,
1180 },
1181 {
1182 .matches = {
1183 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1184 DMI_MATCH(DMI_BOARD_NAME, "Z8P(N)E-D12(X)"),
1185 },
1186 .driver_data = &i801_mux_config_asus_z8_d12,
1187 },
1188 {
1189 .matches = {
1190 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1191 DMI_MATCH(DMI_BOARD_NAME, "Z8NH-D12"),
1192 },
1193 .driver_data = &i801_mux_config_asus_z8_d12,
1194 },
1195 {
1196 .matches = {
1197 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1198 DMI_MATCH(DMI_BOARD_NAME, "Z8PH-D12/IFB"),
1199 },
1200 .driver_data = &i801_mux_config_asus_z8_d12,
1201 },
1202 {
1203 .matches = {
1204 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1205 DMI_MATCH(DMI_BOARD_NAME, "Z8NR-D12"),
1206 },
1207 .driver_data = &i801_mux_config_asus_z8_d12,
1208 },
1209 {
1210 .matches = {
1211 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1212 DMI_MATCH(DMI_BOARD_NAME, "Z8P(N)H-D12"),
1213 },
1214 .driver_data = &i801_mux_config_asus_z8_d12,
1215 },
1216 {
1217 .matches = {
1218 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1219 DMI_MATCH(DMI_BOARD_NAME, "Z8PG-D18"),
1220 },
1221 .driver_data = &i801_mux_config_asus_z8_d18,
1222 },
1223 {
1224 .matches = {
1225 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1226 DMI_MATCH(DMI_BOARD_NAME, "Z8PE-D18"),
1227 },
1228 .driver_data = &i801_mux_config_asus_z8_d18,
1229 },
1230 {
1231 .matches = {
1232 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1233 DMI_MATCH(DMI_BOARD_NAME, "Z8PS-D12"),
1234 },
1235 .driver_data = &i801_mux_config_asus_z8_d12,
1236 },
1237 { }
1238 };
1239
1240 /* Setup multiplexing if needed */
1241 static int i801_add_mux(struct i801_priv *priv)
1242 {
1243 struct device *dev = &priv->adapter.dev;
1244 const struct i801_mux_config *mux_config;
1245 struct i2c_mux_gpio_platform_data gpio_data;
1246 int err;
1247
1248 if (!priv->mux_drvdata)
1249 return 0;
1250 mux_config = priv->mux_drvdata;
1251
1252 /* Prepare the platform data */
1253 memset(&gpio_data, 0, sizeof(struct i2c_mux_gpio_platform_data));
1254 gpio_data.parent = priv->adapter.nr;
1255 gpio_data.values = mux_config->values;
1256 gpio_data.n_values = mux_config->n_values;
1257 gpio_data.classes = mux_config->classes;
1258 gpio_data.gpio_chip = mux_config->gpio_chip;
1259 gpio_data.gpios = mux_config->gpios;
1260 gpio_data.n_gpios = mux_config->n_gpios;
1261 gpio_data.idle = I2C_MUX_GPIO_NO_IDLE;
1262
1263 /* Register the mux device */
1264 priv->mux_pdev = platform_device_register_data(dev, "i2c-mux-gpio",
1265 PLATFORM_DEVID_AUTO, &gpio_data,
1266 sizeof(struct i2c_mux_gpio_platform_data));
1267 if (IS_ERR(priv->mux_pdev)) {
1268 err = PTR_ERR(priv->mux_pdev);
1269 priv->mux_pdev = NULL;
1270 dev_err(dev, "Failed to register i2c-mux-gpio device\n");
1271 return err;
1272 }
1273
1274 return 0;
1275 }
1276
1277 static void i801_del_mux(struct i801_priv *priv)
1278 {
1279 if (priv->mux_pdev)
1280 platform_device_unregister(priv->mux_pdev);
1281 }
1282
1283 static unsigned int i801_get_adapter_class(struct i801_priv *priv)
1284 {
1285 const struct dmi_system_id *id;
1286 const struct i801_mux_config *mux_config;
1287 unsigned int class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
1288 int i;
1289
1290 id = dmi_first_match(mux_dmi_table);
1291 if (id) {
1292 /* Remove branch classes from trunk */
1293 mux_config = id->driver_data;
1294 for (i = 0; i < mux_config->n_values; i++)
1295 class &= ~mux_config->classes[i];
1296
1297 /* Remember for later */
1298 priv->mux_drvdata = mux_config;
1299 }
1300
1301 return class;
1302 }
1303 #else
1304 static inline int i801_add_mux(struct i801_priv *priv) { return 0; }
1305 static inline void i801_del_mux(struct i801_priv *priv) { }
1306
1307 static inline unsigned int i801_get_adapter_class(struct i801_priv *priv)
1308 {
1309 return I2C_CLASS_HWMON | I2C_CLASS_SPD;
1310 }
1311 #endif
1312
1313 static const struct itco_wdt_platform_data tco_platform_data = {
1314 .name = "Intel PCH",
1315 .version = 4,
1316 };
1317
1318 static DEFINE_SPINLOCK(p2sb_spinlock);
1319
1320 static void i801_add_tco(struct i801_priv *priv)
1321 {
1322 struct pci_dev *pci_dev = priv->pci_dev;
1323 struct resource tco_res[3], *res;
1324 struct platform_device *pdev;
1325 unsigned int devfn;
1326 u32 tco_base, tco_ctl;
1327 u32 base_addr, ctrl_val;
1328 u64 base64_addr;
1329
1330 if (!(priv->features & FEATURE_TCO))
1331 return;
1332
1333 pci_read_config_dword(pci_dev, TCOBASE, &tco_base);
1334 pci_read_config_dword(pci_dev, TCOCTL, &tco_ctl);
1335 if (!(tco_ctl & TCOCTL_EN))
1336 return;
1337
1338 memset(tco_res, 0, sizeof(tco_res));
1339
1340 res = &tco_res[ICH_RES_IO_TCO];
1341 res->start = tco_base & ~1;
1342 res->end = res->start + 32 - 1;
1343 res->flags = IORESOURCE_IO;
1344
1345 /*
1346 * Power Management registers.
1347 */
1348 devfn = PCI_DEVFN(PCI_SLOT(pci_dev->devfn), 2);
1349 pci_bus_read_config_dword(pci_dev->bus, devfn, ACPIBASE, &base_addr);
1350
1351 res = &tco_res[ICH_RES_IO_SMI];
1352 res->start = (base_addr & ~1) + ACPIBASE_SMI_OFF;
1353 res->end = res->start + 3;
1354 res->flags = IORESOURCE_IO;
1355
1356 /*
1357 * Enable the ACPI I/O space.
1358 */
1359 pci_bus_read_config_dword(pci_dev->bus, devfn, ACPICTRL, &ctrl_val);
1360 ctrl_val |= ACPICTRL_EN;
1361 pci_bus_write_config_dword(pci_dev->bus, devfn, ACPICTRL, ctrl_val);
1362
1363 /*
1364 * We must access the NO_REBOOT bit over the Primary to Sideband
1365 * bridge (P2SB). The BIOS prevents the P2SB device from being
1366 * enumerated by the PCI subsystem, so we need to unhide/hide it
1367 * to lookup the P2SB BAR.
1368 */
1369 spin_lock(&p2sb_spinlock);
1370
1371 devfn = PCI_DEVFN(PCI_SLOT(pci_dev->devfn), 1);
1372
1373 /* Unhide the P2SB device */
1374 pci_bus_write_config_byte(pci_dev->bus, devfn, 0xe1, 0x0);
1375
1376 pci_bus_read_config_dword(pci_dev->bus, devfn, SBREG_BAR, &base_addr);
1377 base64_addr = base_addr & 0xfffffff0;
1378
1379 pci_bus_read_config_dword(pci_dev->bus, devfn, SBREG_BAR + 0x4, &base_addr);
1380 base64_addr |= (u64)base_addr << 32;
1381
1382 /* Hide the P2SB device */
1383 pci_bus_write_config_byte(pci_dev->bus, devfn, 0xe1, 0x1);
1384 spin_unlock(&p2sb_spinlock);
1385
1386 res = &tco_res[ICH_RES_MEM_OFF];
1387 res->start = (resource_size_t)base64_addr + SBREG_SMBCTRL;
1388 res->end = res->start + 3;
1389 res->flags = IORESOURCE_MEM;
1390
1391 pdev = platform_device_register_resndata(&pci_dev->dev, "iTCO_wdt", -1,
1392 tco_res, 3, &tco_platform_data,
1393 sizeof(tco_platform_data));
1394 if (IS_ERR(pdev)) {
1395 dev_warn(&pci_dev->dev, "failed to create iTCO device\n");
1396 return;
1397 }
1398
1399 priv->tco_pdev = pdev;
1400 }
1401
1402 #ifdef CONFIG_ACPI
1403 static acpi_status
1404 i801_acpi_io_handler(u32 function, acpi_physical_address address, u32 bits,
1405 u64 *value, void *handler_context, void *region_context)
1406 {
1407 struct i801_priv *priv = handler_context;
1408 struct pci_dev *pdev = priv->pci_dev;
1409 acpi_status status;
1410
1411 /*
1412 * Once BIOS AML code touches the OpRegion we warn and inhibit any
1413 * further access from the driver itself. This device is now owned
1414 * by the system firmware.
1415 */
1416 mutex_lock(&priv->acpi_lock);
1417
1418 if (!priv->acpi_reserved) {
1419 priv->acpi_reserved = true;
1420
1421 dev_warn(&pdev->dev, "BIOS is accessing SMBus registers\n");
1422 dev_warn(&pdev->dev, "Driver SMBus register access inhibited\n");
1423
1424 /*
1425 * BIOS is accessing the host controller so prevent it from
1426 * suspending automatically from now on.
1427 */
1428 pm_runtime_get_sync(&pdev->dev);
1429 }
1430
1431 if ((function & ACPI_IO_MASK) == ACPI_READ)
1432 status = acpi_os_read_port(address, (u32 *)value, bits);
1433 else
1434 status = acpi_os_write_port(address, (u32)*value, bits);
1435
1436 mutex_unlock(&priv->acpi_lock);
1437
1438 return status;
1439 }
1440
1441 static int i801_acpi_probe(struct i801_priv *priv)
1442 {
1443 struct acpi_device *adev;
1444 acpi_status status;
1445
1446 adev = ACPI_COMPANION(&priv->pci_dev->dev);
1447 if (adev) {
1448 status = acpi_install_address_space_handler(adev->handle,
1449 ACPI_ADR_SPACE_SYSTEM_IO, i801_acpi_io_handler,
1450 NULL, priv);
1451 if (ACPI_SUCCESS(status))
1452 return 0;
1453 }
1454
1455 return acpi_check_resource_conflict(&priv->pci_dev->resource[SMBBAR]);
1456 }
1457
1458 static void i801_acpi_remove(struct i801_priv *priv)
1459 {
1460 struct acpi_device *adev;
1461
1462 adev = ACPI_COMPANION(&priv->pci_dev->dev);
1463 if (!adev)
1464 return;
1465
1466 acpi_remove_address_space_handler(adev->handle,
1467 ACPI_ADR_SPACE_SYSTEM_IO, i801_acpi_io_handler);
1468
1469 mutex_lock(&priv->acpi_lock);
1470 if (priv->acpi_reserved)
1471 pm_runtime_put(&priv->pci_dev->dev);
1472 mutex_unlock(&priv->acpi_lock);
1473 }
1474 #else
1475 static inline int i801_acpi_probe(struct i801_priv *priv) { return 0; }
1476 static inline void i801_acpi_remove(struct i801_priv *priv) { }
1477 #endif
1478
1479 static int i801_probe(struct pci_dev *dev, const struct pci_device_id *id)
1480 {
1481 unsigned char temp;
1482 int err, i;
1483 struct i801_priv *priv;
1484
1485 priv = devm_kzalloc(&dev->dev, sizeof(*priv), GFP_KERNEL);
1486 if (!priv)
1487 return -ENOMEM;
1488
1489 i2c_set_adapdata(&priv->adapter, priv);
1490 priv->adapter.owner = THIS_MODULE;
1491 priv->adapter.class = i801_get_adapter_class(priv);
1492 priv->adapter.algo = &smbus_algorithm;
1493 priv->adapter.dev.parent = &dev->dev;
1494 ACPI_COMPANION_SET(&priv->adapter.dev, ACPI_COMPANION(&dev->dev));
1495 priv->adapter.retries = 3;
1496 mutex_init(&priv->acpi_lock);
1497
1498 priv->pci_dev = dev;
1499 switch (dev->device) {
1500 case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS:
1501 case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS:
1502 case PCI_DEVICE_ID_INTEL_LEWISBURG_SMBUS:
1503 case PCI_DEVICE_ID_INTEL_LEWISBURG_SSKU_SMBUS:
1504 case PCI_DEVICE_ID_INTEL_DNV_SMBUS:
1505 case PCI_DEVICE_ID_INTEL_KABYLAKE_PCH_H_SMBUS:
1506 priv->features |= FEATURE_I2C_BLOCK_READ;
1507 priv->features |= FEATURE_IRQ;
1508 priv->features |= FEATURE_SMBUS_PEC;
1509 priv->features |= FEATURE_BLOCK_BUFFER;
1510 /* If we have ACPI based watchdog use that instead */
1511 if (!acpi_has_watchdog())
1512 priv->features |= FEATURE_TCO;
1513 priv->features |= FEATURE_HOST_NOTIFY;
1514 break;
1515
1516 case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0:
1517 case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1:
1518 case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2:
1519 case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0:
1520 case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1:
1521 case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2:
1522 priv->features |= FEATURE_IDF;
1523 /* fall through */
1524 default:
1525 priv->features |= FEATURE_I2C_BLOCK_READ;
1526 priv->features |= FEATURE_IRQ;
1527 /* fall through */
1528 case PCI_DEVICE_ID_INTEL_82801DB_3:
1529 priv->features |= FEATURE_SMBUS_PEC;
1530 priv->features |= FEATURE_BLOCK_BUFFER;
1531 /* fall through */
1532 case PCI_DEVICE_ID_INTEL_82801CA_3:
1533 priv->features |= FEATURE_HOST_NOTIFY;
1534 /* fall through */
1535 case PCI_DEVICE_ID_INTEL_82801BA_2:
1536 case PCI_DEVICE_ID_INTEL_82801AB_3:
1537 case PCI_DEVICE_ID_INTEL_82801AA_3:
1538 break;
1539 }
1540
1541 /* Disable features on user request */
1542 for (i = 0; i < ARRAY_SIZE(i801_feature_names); i++) {
1543 if (priv->features & disable_features & (1 << i))
1544 dev_notice(&dev->dev, "%s disabled by user\n",
1545 i801_feature_names[i]);
1546 }
1547 priv->features &= ~disable_features;
1548
1549 err = pcim_enable_device(dev);
1550 if (err) {
1551 dev_err(&dev->dev, "Failed to enable SMBus PCI device (%d)\n",
1552 err);
1553 return err;
1554 }
1555 pcim_pin_device(dev);
1556
1557 /* Determine the address of the SMBus area */
1558 priv->smba = pci_resource_start(dev, SMBBAR);
1559 if (!priv->smba) {
1560 dev_err(&dev->dev,
1561 "SMBus base address uninitialized, upgrade BIOS\n");
1562 return -ENODEV;
1563 }
1564
1565 if (i801_acpi_probe(priv))
1566 return -ENODEV;
1567
1568 err = pcim_iomap_regions(dev, 1 << SMBBAR,
1569 dev_driver_string(&dev->dev));
1570 if (err) {
1571 dev_err(&dev->dev,
1572 "Failed to request SMBus region 0x%lx-0x%Lx\n",
1573 priv->smba,
1574 (unsigned long long)pci_resource_end(dev, SMBBAR));
1575 i801_acpi_remove(priv);
1576 return err;
1577 }
1578
1579 pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &temp);
1580 priv->original_hstcfg = temp;
1581 temp &= ~SMBHSTCFG_I2C_EN; /* SMBus timing */
1582 if (!(temp & SMBHSTCFG_HST_EN)) {
1583 dev_info(&dev->dev, "Enabling SMBus device\n");
1584 temp |= SMBHSTCFG_HST_EN;
1585 }
1586 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, temp);
1587
1588 if (temp & SMBHSTCFG_SMB_SMI_EN) {
1589 dev_dbg(&dev->dev, "SMBus using interrupt SMI#\n");
1590 /* Disable SMBus interrupt feature if SMBus using SMI# */
1591 priv->features &= ~FEATURE_IRQ;
1592 }
1593 if (temp & SMBHSTCFG_SPD_WD)
1594 dev_info(&dev->dev, "SPD Write Disable is set\n");
1595
1596 /* Clear special mode bits */
1597 if (priv->features & (FEATURE_SMBUS_PEC | FEATURE_BLOCK_BUFFER))
1598 outb_p(inb_p(SMBAUXCTL(priv)) &
1599 ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv));
1600
1601 /* Default timeout in interrupt mode: 200 ms */
1602 priv->adapter.timeout = HZ / 5;
1603
1604 if (priv->features & FEATURE_IRQ) {
1605 u16 pcictl, pcists;
1606
1607 /* Complain if an interrupt is already pending */
1608 pci_read_config_word(priv->pci_dev, SMBPCISTS, &pcists);
1609 if (pcists & SMBPCISTS_INTS)
1610 dev_warn(&dev->dev, "An interrupt is pending!\n");
1611
1612 /* Check if interrupts have been disabled */
1613 pci_read_config_word(priv->pci_dev, SMBPCICTL, &pcictl);
1614 if (pcictl & SMBPCICTL_INTDIS) {
1615 dev_info(&dev->dev, "Interrupts are disabled\n");
1616 priv->features &= ~FEATURE_IRQ;
1617 }
1618 }
1619
1620 if (priv->features & FEATURE_IRQ) {
1621 init_waitqueue_head(&priv->waitq);
1622
1623 err = devm_request_irq(&dev->dev, dev->irq, i801_isr,
1624 IRQF_SHARED,
1625 dev_driver_string(&dev->dev), priv);
1626 if (err) {
1627 dev_err(&dev->dev, "Failed to allocate irq %d: %d\n",
1628 dev->irq, err);
1629 priv->features &= ~FEATURE_IRQ;
1630 }
1631 }
1632 dev_info(&dev->dev, "SMBus using %s\n",
1633 priv->features & FEATURE_IRQ ? "PCI interrupt" : "polling");
1634
1635 i801_add_tco(priv);
1636
1637 snprintf(priv->adapter.name, sizeof(priv->adapter.name),
1638 "SMBus I801 adapter at %04lx", priv->smba);
1639 err = i2c_add_adapter(&priv->adapter);
1640 if (err) {
1641 i801_acpi_remove(priv);
1642 return err;
1643 }
1644
1645 i801_enable_host_notify(&priv->adapter);
1646
1647 i801_probe_optional_slaves(priv);
1648 /* We ignore errors - multiplexing is optional */
1649 i801_add_mux(priv);
1650
1651 pci_set_drvdata(dev, priv);
1652
1653 pm_runtime_set_autosuspend_delay(&dev->dev, 1000);
1654 pm_runtime_use_autosuspend(&dev->dev);
1655 pm_runtime_put_autosuspend(&dev->dev);
1656 pm_runtime_allow(&dev->dev);
1657
1658 return 0;
1659 }
1660
1661 static void i801_remove(struct pci_dev *dev)
1662 {
1663 struct i801_priv *priv = pci_get_drvdata(dev);
1664
1665 pm_runtime_forbid(&dev->dev);
1666 pm_runtime_get_noresume(&dev->dev);
1667
1668 i801_disable_host_notify(priv);
1669 i801_del_mux(priv);
1670 i2c_del_adapter(&priv->adapter);
1671 i801_acpi_remove(priv);
1672 pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg);
1673
1674 platform_device_unregister(priv->tco_pdev);
1675
1676 /*
1677 * do not call pci_disable_device(dev) since it can cause hard hangs on
1678 * some systems during power-off (eg. Fujitsu-Siemens Lifebook E8010)
1679 */
1680 }
1681
1682 #ifdef CONFIG_PM
1683 static int i801_suspend(struct device *dev)
1684 {
1685 struct pci_dev *pci_dev = to_pci_dev(dev);
1686 struct i801_priv *priv = pci_get_drvdata(pci_dev);
1687
1688 pci_write_config_byte(pci_dev, SMBHSTCFG, priv->original_hstcfg);
1689 return 0;
1690 }
1691
1692 static int i801_resume(struct device *dev)
1693 {
1694 struct pci_dev *pci_dev = to_pci_dev(dev);
1695 struct i801_priv *priv = pci_get_drvdata(pci_dev);
1696
1697 i801_enable_host_notify(&priv->adapter);
1698
1699 return 0;
1700 }
1701 #endif
1702
1703 static UNIVERSAL_DEV_PM_OPS(i801_pm_ops, i801_suspend,
1704 i801_resume, NULL);
1705
1706 static struct pci_driver i801_driver = {
1707 .name = "i801_smbus",
1708 .id_table = i801_ids,
1709 .probe = i801_probe,
1710 .remove = i801_remove,
1711 .driver = {
1712 .pm = &i801_pm_ops,
1713 },
1714 };
1715
1716 static int __init i2c_i801_init(void)
1717 {
1718 if (dmi_name_in_vendors("FUJITSU"))
1719 input_apanel_init();
1720 return pci_register_driver(&i801_driver);
1721 }
1722
1723 static void __exit i2c_i801_exit(void)
1724 {
1725 pci_unregister_driver(&i801_driver);
1726 }
1727
1728 MODULE_AUTHOR("Mark D. Studebaker <mdsxyz123@yahoo.com>, Jean Delvare <jdelvare@suse.de>");
1729 MODULE_DESCRIPTION("I801 SMBus driver");
1730 MODULE_LICENSE("GPL");
1731
1732 module_init(i2c_i801_init);
1733 module_exit(i2c_i801_exit);
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