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[mirror_ubuntu-artful-kernel.git] / drivers / i2c / busses / i2c-i801.c
1 /*
2 Copyright (c) 1998 - 2002 Frodo Looijaard <frodol@dds.nl>,
3 Philip Edelbrock <phil@netroedge.com>, and Mark D. Studebaker
4 <mdsxyz123@yahoo.com>
5 Copyright (C) 2007 - 2014 Jean Delvare <jdelvare@suse.de>
6 Copyright (C) 2010 Intel Corporation,
7 David Woodhouse <dwmw2@infradead.org>
8
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2 of the License, or
12 (at your option) any later version.
13
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
18 */
19
20 /*
21 * Supports the following Intel I/O Controller Hubs (ICH):
22 *
23 * I/O Block I2C
24 * region SMBus Block proc. block
25 * Chip name PCI ID size PEC buffer call read
26 * ---------------------------------------------------------------------------
27 * 82801AA (ICH) 0x2413 16 no no no no
28 * 82801AB (ICH0) 0x2423 16 no no no no
29 * 82801BA (ICH2) 0x2443 16 no no no no
30 * 82801CA (ICH3) 0x2483 32 soft no no no
31 * 82801DB (ICH4) 0x24c3 32 hard yes no no
32 * 82801E (ICH5) 0x24d3 32 hard yes yes yes
33 * 6300ESB 0x25a4 32 hard yes yes yes
34 * 82801F (ICH6) 0x266a 32 hard yes yes yes
35 * 6310ESB/6320ESB 0x269b 32 hard yes yes yes
36 * 82801G (ICH7) 0x27da 32 hard yes yes yes
37 * 82801H (ICH8) 0x283e 32 hard yes yes yes
38 * 82801I (ICH9) 0x2930 32 hard yes yes yes
39 * EP80579 (Tolapai) 0x5032 32 hard yes yes yes
40 * ICH10 0x3a30 32 hard yes yes yes
41 * ICH10 0x3a60 32 hard yes yes yes
42 * 5/3400 Series (PCH) 0x3b30 32 hard yes yes yes
43 * 6 Series (PCH) 0x1c22 32 hard yes yes yes
44 * Patsburg (PCH) 0x1d22 32 hard yes yes yes
45 * Patsburg (PCH) IDF 0x1d70 32 hard yes yes yes
46 * Patsburg (PCH) IDF 0x1d71 32 hard yes yes yes
47 * Patsburg (PCH) IDF 0x1d72 32 hard yes yes yes
48 * DH89xxCC (PCH) 0x2330 32 hard yes yes yes
49 * Panther Point (PCH) 0x1e22 32 hard yes yes yes
50 * Lynx Point (PCH) 0x8c22 32 hard yes yes yes
51 * Lynx Point-LP (PCH) 0x9c22 32 hard yes yes yes
52 * Avoton (SOC) 0x1f3c 32 hard yes yes yes
53 * Wellsburg (PCH) 0x8d22 32 hard yes yes yes
54 * Wellsburg (PCH) MS 0x8d7d 32 hard yes yes yes
55 * Wellsburg (PCH) MS 0x8d7e 32 hard yes yes yes
56 * Wellsburg (PCH) MS 0x8d7f 32 hard yes yes yes
57 * Coleto Creek (PCH) 0x23b0 32 hard yes yes yes
58 * Wildcat Point (PCH) 0x8ca2 32 hard yes yes yes
59 * Wildcat Point-LP (PCH) 0x9ca2 32 hard yes yes yes
60 * BayTrail (SOC) 0x0f12 32 hard yes yes yes
61 * Sunrise Point-H (PCH) 0xa123 32 hard yes yes yes
62 * Sunrise Point-LP (PCH) 0x9d23 32 hard yes yes yes
63 * DNV (SOC) 0x19df 32 hard yes yes yes
64 * Broxton (SOC) 0x5ad4 32 hard yes yes yes
65 * Lewisburg (PCH) 0xa1a3 32 hard yes yes yes
66 * Lewisburg Supersku (PCH) 0xa223 32 hard yes yes yes
67 *
68 * Features supported by this driver:
69 * Software PEC no
70 * Hardware PEC yes
71 * Block buffer yes
72 * Block process call transaction no
73 * I2C block read transaction yes (doesn't use the block buffer)
74 * Slave mode no
75 * Interrupt processing yes
76 *
77 * See the file Documentation/i2c/busses/i2c-i801 for details.
78 */
79
80 #include <linux/interrupt.h>
81 #include <linux/module.h>
82 #include <linux/pci.h>
83 #include <linux/kernel.h>
84 #include <linux/stddef.h>
85 #include <linux/delay.h>
86 #include <linux/ioport.h>
87 #include <linux/init.h>
88 #include <linux/i2c.h>
89 #include <linux/acpi.h>
90 #include <linux/io.h>
91 #include <linux/dmi.h>
92 #include <linux/slab.h>
93 #include <linux/wait.h>
94 #include <linux/err.h>
95 #include <linux/platform_device.h>
96 #include <linux/platform_data/itco_wdt.h>
97
98 #if (defined CONFIG_I2C_MUX_GPIO || defined CONFIG_I2C_MUX_GPIO_MODULE) && \
99 defined CONFIG_DMI
100 #include <linux/gpio.h>
101 #include <linux/i2c-mux-gpio.h>
102 #endif
103
104 /* I801 SMBus address offsets */
105 #define SMBHSTSTS(p) (0 + (p)->smba)
106 #define SMBHSTCNT(p) (2 + (p)->smba)
107 #define SMBHSTCMD(p) (3 + (p)->smba)
108 #define SMBHSTADD(p) (4 + (p)->smba)
109 #define SMBHSTDAT0(p) (5 + (p)->smba)
110 #define SMBHSTDAT1(p) (6 + (p)->smba)
111 #define SMBBLKDAT(p) (7 + (p)->smba)
112 #define SMBPEC(p) (8 + (p)->smba) /* ICH3 and later */
113 #define SMBAUXSTS(p) (12 + (p)->smba) /* ICH4 and later */
114 #define SMBAUXCTL(p) (13 + (p)->smba) /* ICH4 and later */
115
116 /* PCI Address Constants */
117 #define SMBBAR 4
118 #define SMBPCICTL 0x004
119 #define SMBPCISTS 0x006
120 #define SMBHSTCFG 0x040
121 #define TCOBASE 0x050
122 #define TCOCTL 0x054
123
124 #define ACPIBASE 0x040
125 #define ACPIBASE_SMI_OFF 0x030
126 #define ACPICTRL 0x044
127 #define ACPICTRL_EN 0x080
128
129 #define SBREG_BAR 0x10
130 #define SBREG_SMBCTRL 0xc6000c
131
132 /* Host status bits for SMBPCISTS */
133 #define SMBPCISTS_INTS 0x08
134
135 /* Control bits for SMBPCICTL */
136 #define SMBPCICTL_INTDIS 0x0400
137
138 /* Host configuration bits for SMBHSTCFG */
139 #define SMBHSTCFG_HST_EN 1
140 #define SMBHSTCFG_SMB_SMI_EN 2
141 #define SMBHSTCFG_I2C_EN 4
142
143 /* TCO configuration bits for TCOCTL */
144 #define TCOCTL_EN 0x0100
145
146 /* Auxiliary control register bits, ICH4+ only */
147 #define SMBAUXCTL_CRC 1
148 #define SMBAUXCTL_E32B 2
149
150 /* Other settings */
151 #define MAX_RETRIES 400
152
153 /* I801 command constants */
154 #define I801_QUICK 0x00
155 #define I801_BYTE 0x04
156 #define I801_BYTE_DATA 0x08
157 #define I801_WORD_DATA 0x0C
158 #define I801_PROC_CALL 0x10 /* unimplemented */
159 #define I801_BLOCK_DATA 0x14
160 #define I801_I2C_BLOCK_DATA 0x18 /* ICH5 and later */
161
162 /* I801 Host Control register bits */
163 #define SMBHSTCNT_INTREN 0x01
164 #define SMBHSTCNT_KILL 0x02
165 #define SMBHSTCNT_LAST_BYTE 0x20
166 #define SMBHSTCNT_START 0x40
167 #define SMBHSTCNT_PEC_EN 0x80 /* ICH3 and later */
168
169 /* I801 Hosts Status register bits */
170 #define SMBHSTSTS_BYTE_DONE 0x80
171 #define SMBHSTSTS_INUSE_STS 0x40
172 #define SMBHSTSTS_SMBALERT_STS 0x20
173 #define SMBHSTSTS_FAILED 0x10
174 #define SMBHSTSTS_BUS_ERR 0x08
175 #define SMBHSTSTS_DEV_ERR 0x04
176 #define SMBHSTSTS_INTR 0x02
177 #define SMBHSTSTS_HOST_BUSY 0x01
178
179 #define STATUS_ERROR_FLAGS (SMBHSTSTS_FAILED | SMBHSTSTS_BUS_ERR | \
180 SMBHSTSTS_DEV_ERR)
181
182 #define STATUS_FLAGS (SMBHSTSTS_BYTE_DONE | SMBHSTSTS_INTR | \
183 STATUS_ERROR_FLAGS)
184
185 /* Older devices have their ID defined in <linux/pci_ids.h> */
186 #define PCI_DEVICE_ID_INTEL_BAYTRAIL_SMBUS 0x0f12
187 #define PCI_DEVICE_ID_INTEL_BRASWELL_SMBUS 0x2292
188 #define PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS 0x1c22
189 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS 0x1d22
190 /* Patsburg also has three 'Integrated Device Function' SMBus controllers */
191 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0 0x1d70
192 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1 0x1d71
193 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2 0x1d72
194 #define PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS 0x1e22
195 #define PCI_DEVICE_ID_INTEL_AVOTON_SMBUS 0x1f3c
196 #define PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS 0x2330
197 #define PCI_DEVICE_ID_INTEL_COLETOCREEK_SMBUS 0x23b0
198 #define PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS 0x3b30
199 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS 0x8c22
200 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_SMBUS 0x8ca2
201 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS 0x8d22
202 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0 0x8d7d
203 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1 0x8d7e
204 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2 0x8d7f
205 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS 0x9c22
206 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_SMBUS 0x9ca2
207 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS 0xa123
208 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS 0x9d23
209 #define PCI_DEVICE_ID_INTEL_DNV_SMBUS 0x19df
210 #define PCI_DEVICE_ID_INTEL_BROXTON_SMBUS 0x5ad4
211 #define PCI_DEVICE_ID_INTEL_LEWISBURG_SMBUS 0xa1a3
212 #define PCI_DEVICE_ID_INTEL_LEWISBURG_SSKU_SMBUS 0xa223
213
214 struct i801_mux_config {
215 char *gpio_chip;
216 unsigned values[3];
217 int n_values;
218 unsigned classes[3];
219 unsigned gpios[2]; /* Relative to gpio_chip->base */
220 int n_gpios;
221 };
222
223 struct i801_priv {
224 struct i2c_adapter adapter;
225 unsigned long smba;
226 unsigned char original_hstcfg;
227 struct pci_dev *pci_dev;
228 unsigned int features;
229
230 /* isr processing */
231 wait_queue_head_t waitq;
232 u8 status;
233
234 /* Command state used by isr for byte-by-byte block transactions */
235 u8 cmd;
236 bool is_read;
237 int count;
238 int len;
239 u8 *data;
240
241 #if (defined CONFIG_I2C_MUX_GPIO || defined CONFIG_I2C_MUX_GPIO_MODULE) && \
242 defined CONFIG_DMI
243 const struct i801_mux_config *mux_drvdata;
244 struct platform_device *mux_pdev;
245 #endif
246 struct platform_device *tco_pdev;
247 };
248
249 #define FEATURE_SMBUS_PEC (1 << 0)
250 #define FEATURE_BLOCK_BUFFER (1 << 1)
251 #define FEATURE_BLOCK_PROC (1 << 2)
252 #define FEATURE_I2C_BLOCK_READ (1 << 3)
253 #define FEATURE_IRQ (1 << 4)
254 /* Not really a feature, but it's convenient to handle it as such */
255 #define FEATURE_IDF (1 << 15)
256 #define FEATURE_TCO (1 << 16)
257
258 static const char *i801_feature_names[] = {
259 "SMBus PEC",
260 "Block buffer",
261 "Block process call",
262 "I2C block read",
263 "Interrupt",
264 };
265
266 static unsigned int disable_features;
267 module_param(disable_features, uint, S_IRUGO | S_IWUSR);
268 MODULE_PARM_DESC(disable_features, "Disable selected driver features:\n"
269 "\t\t 0x01 disable SMBus PEC\n"
270 "\t\t 0x02 disable the block buffer\n"
271 "\t\t 0x08 disable the I2C block read functionality\n"
272 "\t\t 0x10 don't use interrupts ");
273
274 /* Make sure the SMBus host is ready to start transmitting.
275 Return 0 if it is, -EBUSY if it is not. */
276 static int i801_check_pre(struct i801_priv *priv)
277 {
278 int status;
279
280 status = inb_p(SMBHSTSTS(priv));
281 if (status & SMBHSTSTS_HOST_BUSY) {
282 dev_err(&priv->pci_dev->dev, "SMBus is busy, can't use it!\n");
283 return -EBUSY;
284 }
285
286 status &= STATUS_FLAGS;
287 if (status) {
288 dev_dbg(&priv->pci_dev->dev, "Clearing status flags (%02x)\n",
289 status);
290 outb_p(status, SMBHSTSTS(priv));
291 status = inb_p(SMBHSTSTS(priv)) & STATUS_FLAGS;
292 if (status) {
293 dev_err(&priv->pci_dev->dev,
294 "Failed clearing status flags (%02x)\n",
295 status);
296 return -EBUSY;
297 }
298 }
299
300 return 0;
301 }
302
303 /*
304 * Convert the status register to an error code, and clear it.
305 * Note that status only contains the bits we want to clear, not the
306 * actual register value.
307 */
308 static int i801_check_post(struct i801_priv *priv, int status)
309 {
310 int result = 0;
311
312 /*
313 * If the SMBus is still busy, we give up
314 * Note: This timeout condition only happens when using polling
315 * transactions. For interrupt operation, NAK/timeout is indicated by
316 * DEV_ERR.
317 */
318 if (unlikely(status < 0)) {
319 dev_err(&priv->pci_dev->dev, "Transaction timeout\n");
320 /* try to stop the current command */
321 dev_dbg(&priv->pci_dev->dev, "Terminating the current operation\n");
322 outb_p(inb_p(SMBHSTCNT(priv)) | SMBHSTCNT_KILL,
323 SMBHSTCNT(priv));
324 usleep_range(1000, 2000);
325 outb_p(inb_p(SMBHSTCNT(priv)) & (~SMBHSTCNT_KILL),
326 SMBHSTCNT(priv));
327
328 /* Check if it worked */
329 status = inb_p(SMBHSTSTS(priv));
330 if ((status & SMBHSTSTS_HOST_BUSY) ||
331 !(status & SMBHSTSTS_FAILED))
332 dev_err(&priv->pci_dev->dev,
333 "Failed terminating the transaction\n");
334 outb_p(STATUS_FLAGS, SMBHSTSTS(priv));
335 return -ETIMEDOUT;
336 }
337
338 if (status & SMBHSTSTS_FAILED) {
339 result = -EIO;
340 dev_err(&priv->pci_dev->dev, "Transaction failed\n");
341 }
342 if (status & SMBHSTSTS_DEV_ERR) {
343 result = -ENXIO;
344 dev_dbg(&priv->pci_dev->dev, "No response\n");
345 }
346 if (status & SMBHSTSTS_BUS_ERR) {
347 result = -EAGAIN;
348 dev_dbg(&priv->pci_dev->dev, "Lost arbitration\n");
349 }
350
351 /* Clear status flags except BYTE_DONE, to be cleared by caller */
352 outb_p(status, SMBHSTSTS(priv));
353
354 return result;
355 }
356
357 /* Wait for BUSY being cleared and either INTR or an error flag being set */
358 static int i801_wait_intr(struct i801_priv *priv)
359 {
360 int timeout = 0;
361 int status;
362
363 /* We will always wait for a fraction of a second! */
364 do {
365 usleep_range(250, 500);
366 status = inb_p(SMBHSTSTS(priv));
367 } while (((status & SMBHSTSTS_HOST_BUSY) ||
368 !(status & (STATUS_ERROR_FLAGS | SMBHSTSTS_INTR))) &&
369 (timeout++ < MAX_RETRIES));
370
371 if (timeout > MAX_RETRIES) {
372 dev_dbg(&priv->pci_dev->dev, "INTR Timeout!\n");
373 return -ETIMEDOUT;
374 }
375 return status & (STATUS_ERROR_FLAGS | SMBHSTSTS_INTR);
376 }
377
378 /* Wait for either BYTE_DONE or an error flag being set */
379 static int i801_wait_byte_done(struct i801_priv *priv)
380 {
381 int timeout = 0;
382 int status;
383
384 /* We will always wait for a fraction of a second! */
385 do {
386 usleep_range(250, 500);
387 status = inb_p(SMBHSTSTS(priv));
388 } while (!(status & (STATUS_ERROR_FLAGS | SMBHSTSTS_BYTE_DONE)) &&
389 (timeout++ < MAX_RETRIES));
390
391 if (timeout > MAX_RETRIES) {
392 dev_dbg(&priv->pci_dev->dev, "BYTE_DONE Timeout!\n");
393 return -ETIMEDOUT;
394 }
395 return status & STATUS_ERROR_FLAGS;
396 }
397
398 static int i801_transaction(struct i801_priv *priv, int xact)
399 {
400 int status;
401 int result;
402 const struct i2c_adapter *adap = &priv->adapter;
403
404 result = i801_check_pre(priv);
405 if (result < 0)
406 return result;
407
408 if (priv->features & FEATURE_IRQ) {
409 outb_p(xact | SMBHSTCNT_INTREN | SMBHSTCNT_START,
410 SMBHSTCNT(priv));
411 result = wait_event_timeout(priv->waitq,
412 (status = priv->status),
413 adap->timeout);
414 if (!result) {
415 status = -ETIMEDOUT;
416 dev_warn(&priv->pci_dev->dev,
417 "Timeout waiting for interrupt!\n");
418 }
419 priv->status = 0;
420 return i801_check_post(priv, status);
421 }
422
423 /* the current contents of SMBHSTCNT can be overwritten, since PEC,
424 * SMBSCMD are passed in xact */
425 outb_p(xact | SMBHSTCNT_START, SMBHSTCNT(priv));
426
427 status = i801_wait_intr(priv);
428 return i801_check_post(priv, status);
429 }
430
431 static int i801_block_transaction_by_block(struct i801_priv *priv,
432 union i2c_smbus_data *data,
433 char read_write, int hwpec)
434 {
435 int i, len;
436 int status;
437
438 inb_p(SMBHSTCNT(priv)); /* reset the data buffer index */
439
440 /* Use 32-byte buffer to process this transaction */
441 if (read_write == I2C_SMBUS_WRITE) {
442 len = data->block[0];
443 outb_p(len, SMBHSTDAT0(priv));
444 for (i = 0; i < len; i++)
445 outb_p(data->block[i+1], SMBBLKDAT(priv));
446 }
447
448 status = i801_transaction(priv, I801_BLOCK_DATA |
449 (hwpec ? SMBHSTCNT_PEC_EN : 0));
450 if (status)
451 return status;
452
453 if (read_write == I2C_SMBUS_READ) {
454 len = inb_p(SMBHSTDAT0(priv));
455 if (len < 1 || len > I2C_SMBUS_BLOCK_MAX)
456 return -EPROTO;
457
458 data->block[0] = len;
459 for (i = 0; i < len; i++)
460 data->block[i + 1] = inb_p(SMBBLKDAT(priv));
461 }
462 return 0;
463 }
464
465 static void i801_isr_byte_done(struct i801_priv *priv)
466 {
467 if (priv->is_read) {
468 /* For SMBus block reads, length is received with first byte */
469 if (((priv->cmd & 0x1c) == I801_BLOCK_DATA) &&
470 (priv->count == 0)) {
471 priv->len = inb_p(SMBHSTDAT0(priv));
472 if (priv->len < 1 || priv->len > I2C_SMBUS_BLOCK_MAX) {
473 dev_err(&priv->pci_dev->dev,
474 "Illegal SMBus block read size %d\n",
475 priv->len);
476 /* FIXME: Recover */
477 priv->len = I2C_SMBUS_BLOCK_MAX;
478 } else {
479 dev_dbg(&priv->pci_dev->dev,
480 "SMBus block read size is %d\n",
481 priv->len);
482 }
483 priv->data[-1] = priv->len;
484 }
485
486 /* Read next byte */
487 if (priv->count < priv->len)
488 priv->data[priv->count++] = inb(SMBBLKDAT(priv));
489 else
490 dev_dbg(&priv->pci_dev->dev,
491 "Discarding extra byte on block read\n");
492
493 /* Set LAST_BYTE for last byte of read transaction */
494 if (priv->count == priv->len - 1)
495 outb_p(priv->cmd | SMBHSTCNT_LAST_BYTE,
496 SMBHSTCNT(priv));
497 } else if (priv->count < priv->len - 1) {
498 /* Write next byte, except for IRQ after last byte */
499 outb_p(priv->data[++priv->count], SMBBLKDAT(priv));
500 }
501
502 /* Clear BYTE_DONE to continue with next byte */
503 outb_p(SMBHSTSTS_BYTE_DONE, SMBHSTSTS(priv));
504 }
505
506 /*
507 * There are two kinds of interrupts:
508 *
509 * 1) i801 signals transaction completion with one of these interrupts:
510 * INTR - Success
511 * DEV_ERR - Invalid command, NAK or communication timeout
512 * BUS_ERR - SMI# transaction collision
513 * FAILED - transaction was canceled due to a KILL request
514 * When any of these occur, update ->status and wake up the waitq.
515 * ->status must be cleared before kicking off the next transaction.
516 *
517 * 2) For byte-by-byte (I2C read/write) transactions, one BYTE_DONE interrupt
518 * occurs for each byte of a byte-by-byte to prepare the next byte.
519 */
520 static irqreturn_t i801_isr(int irq, void *dev_id)
521 {
522 struct i801_priv *priv = dev_id;
523 u16 pcists;
524 u8 status;
525
526 /* Confirm this is our interrupt */
527 pci_read_config_word(priv->pci_dev, SMBPCISTS, &pcists);
528 if (!(pcists & SMBPCISTS_INTS))
529 return IRQ_NONE;
530
531 status = inb_p(SMBHSTSTS(priv));
532 if (status & SMBHSTSTS_BYTE_DONE)
533 i801_isr_byte_done(priv);
534
535 /*
536 * Clear irq sources and report transaction result.
537 * ->status must be cleared before the next transaction is started.
538 */
539 status &= SMBHSTSTS_INTR | STATUS_ERROR_FLAGS;
540 if (status) {
541 outb_p(status, SMBHSTSTS(priv));
542 priv->status |= status;
543 wake_up(&priv->waitq);
544 }
545
546 return IRQ_HANDLED;
547 }
548
549 /*
550 * For "byte-by-byte" block transactions:
551 * I2C write uses cmd=I801_BLOCK_DATA, I2C_EN=1
552 * I2C read uses cmd=I801_I2C_BLOCK_DATA
553 */
554 static int i801_block_transaction_byte_by_byte(struct i801_priv *priv,
555 union i2c_smbus_data *data,
556 char read_write, int command,
557 int hwpec)
558 {
559 int i, len;
560 int smbcmd;
561 int status;
562 int result;
563 const struct i2c_adapter *adap = &priv->adapter;
564
565 result = i801_check_pre(priv);
566 if (result < 0)
567 return result;
568
569 len = data->block[0];
570
571 if (read_write == I2C_SMBUS_WRITE) {
572 outb_p(len, SMBHSTDAT0(priv));
573 outb_p(data->block[1], SMBBLKDAT(priv));
574 }
575
576 if (command == I2C_SMBUS_I2C_BLOCK_DATA &&
577 read_write == I2C_SMBUS_READ)
578 smbcmd = I801_I2C_BLOCK_DATA;
579 else
580 smbcmd = I801_BLOCK_DATA;
581
582 if (priv->features & FEATURE_IRQ) {
583 priv->is_read = (read_write == I2C_SMBUS_READ);
584 if (len == 1 && priv->is_read)
585 smbcmd |= SMBHSTCNT_LAST_BYTE;
586 priv->cmd = smbcmd | SMBHSTCNT_INTREN;
587 priv->len = len;
588 priv->count = 0;
589 priv->data = &data->block[1];
590
591 outb_p(priv->cmd | SMBHSTCNT_START, SMBHSTCNT(priv));
592 result = wait_event_timeout(priv->waitq,
593 (status = priv->status),
594 adap->timeout);
595 if (!result) {
596 status = -ETIMEDOUT;
597 dev_warn(&priv->pci_dev->dev,
598 "Timeout waiting for interrupt!\n");
599 }
600 priv->status = 0;
601 return i801_check_post(priv, status);
602 }
603
604 for (i = 1; i <= len; i++) {
605 if (i == len && read_write == I2C_SMBUS_READ)
606 smbcmd |= SMBHSTCNT_LAST_BYTE;
607 outb_p(smbcmd, SMBHSTCNT(priv));
608
609 if (i == 1)
610 outb_p(inb(SMBHSTCNT(priv)) | SMBHSTCNT_START,
611 SMBHSTCNT(priv));
612
613 status = i801_wait_byte_done(priv);
614 if (status)
615 goto exit;
616
617 if (i == 1 && read_write == I2C_SMBUS_READ
618 && command != I2C_SMBUS_I2C_BLOCK_DATA) {
619 len = inb_p(SMBHSTDAT0(priv));
620 if (len < 1 || len > I2C_SMBUS_BLOCK_MAX) {
621 dev_err(&priv->pci_dev->dev,
622 "Illegal SMBus block read size %d\n",
623 len);
624 /* Recover */
625 while (inb_p(SMBHSTSTS(priv)) &
626 SMBHSTSTS_HOST_BUSY)
627 outb_p(SMBHSTSTS_BYTE_DONE,
628 SMBHSTSTS(priv));
629 outb_p(SMBHSTSTS_INTR, SMBHSTSTS(priv));
630 return -EPROTO;
631 }
632 data->block[0] = len;
633 }
634
635 /* Retrieve/store value in SMBBLKDAT */
636 if (read_write == I2C_SMBUS_READ)
637 data->block[i] = inb_p(SMBBLKDAT(priv));
638 if (read_write == I2C_SMBUS_WRITE && i+1 <= len)
639 outb_p(data->block[i+1], SMBBLKDAT(priv));
640
641 /* signals SMBBLKDAT ready */
642 outb_p(SMBHSTSTS_BYTE_DONE, SMBHSTSTS(priv));
643 }
644
645 status = i801_wait_intr(priv);
646 exit:
647 return i801_check_post(priv, status);
648 }
649
650 static int i801_set_block_buffer_mode(struct i801_priv *priv)
651 {
652 outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_E32B, SMBAUXCTL(priv));
653 if ((inb_p(SMBAUXCTL(priv)) & SMBAUXCTL_E32B) == 0)
654 return -EIO;
655 return 0;
656 }
657
658 /* Block transaction function */
659 static int i801_block_transaction(struct i801_priv *priv,
660 union i2c_smbus_data *data, char read_write,
661 int command, int hwpec)
662 {
663 int result = 0;
664 unsigned char hostc;
665
666 if (command == I2C_SMBUS_I2C_BLOCK_DATA) {
667 if (read_write == I2C_SMBUS_WRITE) {
668 /* set I2C_EN bit in configuration register */
669 pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &hostc);
670 pci_write_config_byte(priv->pci_dev, SMBHSTCFG,
671 hostc | SMBHSTCFG_I2C_EN);
672 } else if (!(priv->features & FEATURE_I2C_BLOCK_READ)) {
673 dev_err(&priv->pci_dev->dev,
674 "I2C block read is unsupported!\n");
675 return -EOPNOTSUPP;
676 }
677 }
678
679 if (read_write == I2C_SMBUS_WRITE
680 || command == I2C_SMBUS_I2C_BLOCK_DATA) {
681 if (data->block[0] < 1)
682 data->block[0] = 1;
683 if (data->block[0] > I2C_SMBUS_BLOCK_MAX)
684 data->block[0] = I2C_SMBUS_BLOCK_MAX;
685 } else {
686 data->block[0] = 32; /* max for SMBus block reads */
687 }
688
689 /* Experience has shown that the block buffer can only be used for
690 SMBus (not I2C) block transactions, even though the datasheet
691 doesn't mention this limitation. */
692 if ((priv->features & FEATURE_BLOCK_BUFFER)
693 && command != I2C_SMBUS_I2C_BLOCK_DATA
694 && i801_set_block_buffer_mode(priv) == 0)
695 result = i801_block_transaction_by_block(priv, data,
696 read_write, hwpec);
697 else
698 result = i801_block_transaction_byte_by_byte(priv, data,
699 read_write,
700 command, hwpec);
701
702 if (command == I2C_SMBUS_I2C_BLOCK_DATA
703 && read_write == I2C_SMBUS_WRITE) {
704 /* restore saved configuration register value */
705 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, hostc);
706 }
707 return result;
708 }
709
710 /* Return negative errno on error. */
711 static s32 i801_access(struct i2c_adapter *adap, u16 addr,
712 unsigned short flags, char read_write, u8 command,
713 int size, union i2c_smbus_data *data)
714 {
715 int hwpec;
716 int block = 0;
717 int ret, xact = 0;
718 struct i801_priv *priv = i2c_get_adapdata(adap);
719
720 hwpec = (priv->features & FEATURE_SMBUS_PEC) && (flags & I2C_CLIENT_PEC)
721 && size != I2C_SMBUS_QUICK
722 && size != I2C_SMBUS_I2C_BLOCK_DATA;
723
724 switch (size) {
725 case I2C_SMBUS_QUICK:
726 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
727 SMBHSTADD(priv));
728 xact = I801_QUICK;
729 break;
730 case I2C_SMBUS_BYTE:
731 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
732 SMBHSTADD(priv));
733 if (read_write == I2C_SMBUS_WRITE)
734 outb_p(command, SMBHSTCMD(priv));
735 xact = I801_BYTE;
736 break;
737 case I2C_SMBUS_BYTE_DATA:
738 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
739 SMBHSTADD(priv));
740 outb_p(command, SMBHSTCMD(priv));
741 if (read_write == I2C_SMBUS_WRITE)
742 outb_p(data->byte, SMBHSTDAT0(priv));
743 xact = I801_BYTE_DATA;
744 break;
745 case I2C_SMBUS_WORD_DATA:
746 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
747 SMBHSTADD(priv));
748 outb_p(command, SMBHSTCMD(priv));
749 if (read_write == I2C_SMBUS_WRITE) {
750 outb_p(data->word & 0xff, SMBHSTDAT0(priv));
751 outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1(priv));
752 }
753 xact = I801_WORD_DATA;
754 break;
755 case I2C_SMBUS_BLOCK_DATA:
756 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
757 SMBHSTADD(priv));
758 outb_p(command, SMBHSTCMD(priv));
759 block = 1;
760 break;
761 case I2C_SMBUS_I2C_BLOCK_DATA:
762 /* NB: page 240 of ICH5 datasheet shows that the R/#W
763 * bit should be cleared here, even when reading */
764 outb_p((addr & 0x7f) << 1, SMBHSTADD(priv));
765 if (read_write == I2C_SMBUS_READ) {
766 /* NB: page 240 of ICH5 datasheet also shows
767 * that DATA1 is the cmd field when reading */
768 outb_p(command, SMBHSTDAT1(priv));
769 } else
770 outb_p(command, SMBHSTCMD(priv));
771 block = 1;
772 break;
773 default:
774 dev_err(&priv->pci_dev->dev, "Unsupported transaction %d\n",
775 size);
776 return -EOPNOTSUPP;
777 }
778
779 if (hwpec) /* enable/disable hardware PEC */
780 outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_CRC, SMBAUXCTL(priv));
781 else
782 outb_p(inb_p(SMBAUXCTL(priv)) & (~SMBAUXCTL_CRC),
783 SMBAUXCTL(priv));
784
785 if (block)
786 ret = i801_block_transaction(priv, data, read_write, size,
787 hwpec);
788 else
789 ret = i801_transaction(priv, xact);
790
791 /* Some BIOSes don't like it when PEC is enabled at reboot or resume
792 time, so we forcibly disable it after every transaction. Turn off
793 E32B for the same reason. */
794 if (hwpec || block)
795 outb_p(inb_p(SMBAUXCTL(priv)) &
796 ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv));
797
798 if (block)
799 return ret;
800 if (ret)
801 return ret;
802 if ((read_write == I2C_SMBUS_WRITE) || (xact == I801_QUICK))
803 return 0;
804
805 switch (xact & 0x7f) {
806 case I801_BYTE: /* Result put in SMBHSTDAT0 */
807 case I801_BYTE_DATA:
808 data->byte = inb_p(SMBHSTDAT0(priv));
809 break;
810 case I801_WORD_DATA:
811 data->word = inb_p(SMBHSTDAT0(priv)) +
812 (inb_p(SMBHSTDAT1(priv)) << 8);
813 break;
814 }
815 return 0;
816 }
817
818
819 static u32 i801_func(struct i2c_adapter *adapter)
820 {
821 struct i801_priv *priv = i2c_get_adapdata(adapter);
822
823 return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
824 I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
825 I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_WRITE_I2C_BLOCK |
826 ((priv->features & FEATURE_SMBUS_PEC) ? I2C_FUNC_SMBUS_PEC : 0) |
827 ((priv->features & FEATURE_I2C_BLOCK_READ) ?
828 I2C_FUNC_SMBUS_READ_I2C_BLOCK : 0);
829 }
830
831 static const struct i2c_algorithm smbus_algorithm = {
832 .smbus_xfer = i801_access,
833 .functionality = i801_func,
834 };
835
836 static const struct pci_device_id i801_ids[] = {
837 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_3) },
838 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_3) },
839 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_2) },
840 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_3) },
841 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_3) },
842 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_3) },
843 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_4) },
844 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_16) },
845 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_17) },
846 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_17) },
847 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_5) },
848 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_6) },
849 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EP80579_1) },
850 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_4) },
851 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_5) },
852 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS) },
853 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS) },
854 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS) },
855 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0) },
856 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1) },
857 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2) },
858 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS) },
859 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS) },
860 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS) },
861 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS) },
862 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_AVOTON_SMBUS) },
863 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS) },
864 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0) },
865 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1) },
866 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2) },
867 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COLETOCREEK_SMBUS) },
868 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WILDCATPOINT_SMBUS) },
869 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_SMBUS) },
870 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BAYTRAIL_SMBUS) },
871 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BRASWELL_SMBUS) },
872 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS) },
873 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS) },
874 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_DNV_SMBUS) },
875 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BROXTON_SMBUS) },
876 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LEWISBURG_SMBUS) },
877 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LEWISBURG_SSKU_SMBUS) },
878 { 0, }
879 };
880
881 MODULE_DEVICE_TABLE(pci, i801_ids);
882
883 #if defined CONFIG_X86 && defined CONFIG_DMI
884 static unsigned char apanel_addr;
885
886 /* Scan the system ROM for the signature "FJKEYINF" */
887 static __init const void __iomem *bios_signature(const void __iomem *bios)
888 {
889 ssize_t offset;
890 const unsigned char signature[] = "FJKEYINF";
891
892 for (offset = 0; offset < 0x10000; offset += 0x10) {
893 if (check_signature(bios + offset, signature,
894 sizeof(signature)-1))
895 return bios + offset;
896 }
897 return NULL;
898 }
899
900 static void __init input_apanel_init(void)
901 {
902 void __iomem *bios;
903 const void __iomem *p;
904
905 bios = ioremap(0xF0000, 0x10000); /* Can't fail */
906 p = bios_signature(bios);
907 if (p) {
908 /* just use the first address */
909 apanel_addr = readb(p + 8 + 3) >> 1;
910 }
911 iounmap(bios);
912 }
913
914 struct dmi_onboard_device_info {
915 const char *name;
916 u8 type;
917 unsigned short i2c_addr;
918 const char *i2c_type;
919 };
920
921 static const struct dmi_onboard_device_info dmi_devices[] = {
922 { "Syleus", DMI_DEV_TYPE_OTHER, 0x73, "fscsyl" },
923 { "Hermes", DMI_DEV_TYPE_OTHER, 0x73, "fscher" },
924 { "Hades", DMI_DEV_TYPE_OTHER, 0x73, "fschds" },
925 };
926
927 static void dmi_check_onboard_device(u8 type, const char *name,
928 struct i2c_adapter *adap)
929 {
930 int i;
931 struct i2c_board_info info;
932
933 for (i = 0; i < ARRAY_SIZE(dmi_devices); i++) {
934 /* & ~0x80, ignore enabled/disabled bit */
935 if ((type & ~0x80) != dmi_devices[i].type)
936 continue;
937 if (strcasecmp(name, dmi_devices[i].name))
938 continue;
939
940 memset(&info, 0, sizeof(struct i2c_board_info));
941 info.addr = dmi_devices[i].i2c_addr;
942 strlcpy(info.type, dmi_devices[i].i2c_type, I2C_NAME_SIZE);
943 i2c_new_device(adap, &info);
944 break;
945 }
946 }
947
948 /* We use our own function to check for onboard devices instead of
949 dmi_find_device() as some buggy BIOS's have the devices we are interested
950 in marked as disabled */
951 static void dmi_check_onboard_devices(const struct dmi_header *dm, void *adap)
952 {
953 int i, count;
954
955 if (dm->type != 10)
956 return;
957
958 count = (dm->length - sizeof(struct dmi_header)) / 2;
959 for (i = 0; i < count; i++) {
960 const u8 *d = (char *)(dm + 1) + (i * 2);
961 const char *name = ((char *) dm) + dm->length;
962 u8 type = d[0];
963 u8 s = d[1];
964
965 if (!s)
966 continue;
967 s--;
968 while (s > 0 && name[0]) {
969 name += strlen(name) + 1;
970 s--;
971 }
972 if (name[0] == 0) /* Bogus string reference */
973 continue;
974
975 dmi_check_onboard_device(type, name, adap);
976 }
977 }
978
979 /* Register optional slaves */
980 static void i801_probe_optional_slaves(struct i801_priv *priv)
981 {
982 /* Only register slaves on main SMBus channel */
983 if (priv->features & FEATURE_IDF)
984 return;
985
986 if (apanel_addr) {
987 struct i2c_board_info info;
988
989 memset(&info, 0, sizeof(struct i2c_board_info));
990 info.addr = apanel_addr;
991 strlcpy(info.type, "fujitsu_apanel", I2C_NAME_SIZE);
992 i2c_new_device(&priv->adapter, &info);
993 }
994
995 if (dmi_name_in_vendors("FUJITSU"))
996 dmi_walk(dmi_check_onboard_devices, &priv->adapter);
997 }
998 #else
999 static void __init input_apanel_init(void) {}
1000 static void i801_probe_optional_slaves(struct i801_priv *priv) {}
1001 #endif /* CONFIG_X86 && CONFIG_DMI */
1002
1003 #if (defined CONFIG_I2C_MUX_GPIO || defined CONFIG_I2C_MUX_GPIO_MODULE) && \
1004 defined CONFIG_DMI
1005 static struct i801_mux_config i801_mux_config_asus_z8_d12 = {
1006 .gpio_chip = "gpio_ich",
1007 .values = { 0x02, 0x03 },
1008 .n_values = 2,
1009 .classes = { I2C_CLASS_SPD, I2C_CLASS_SPD },
1010 .gpios = { 52, 53 },
1011 .n_gpios = 2,
1012 };
1013
1014 static struct i801_mux_config i801_mux_config_asus_z8_d18 = {
1015 .gpio_chip = "gpio_ich",
1016 .values = { 0x02, 0x03, 0x01 },
1017 .n_values = 3,
1018 .classes = { I2C_CLASS_SPD, I2C_CLASS_SPD, I2C_CLASS_SPD },
1019 .gpios = { 52, 53 },
1020 .n_gpios = 2,
1021 };
1022
1023 static const struct dmi_system_id mux_dmi_table[] = {
1024 {
1025 .matches = {
1026 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1027 DMI_MATCH(DMI_BOARD_NAME, "Z8NA-D6(C)"),
1028 },
1029 .driver_data = &i801_mux_config_asus_z8_d12,
1030 },
1031 {
1032 .matches = {
1033 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1034 DMI_MATCH(DMI_BOARD_NAME, "Z8P(N)E-D12(X)"),
1035 },
1036 .driver_data = &i801_mux_config_asus_z8_d12,
1037 },
1038 {
1039 .matches = {
1040 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1041 DMI_MATCH(DMI_BOARD_NAME, "Z8NH-D12"),
1042 },
1043 .driver_data = &i801_mux_config_asus_z8_d12,
1044 },
1045 {
1046 .matches = {
1047 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1048 DMI_MATCH(DMI_BOARD_NAME, "Z8PH-D12/IFB"),
1049 },
1050 .driver_data = &i801_mux_config_asus_z8_d12,
1051 },
1052 {
1053 .matches = {
1054 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1055 DMI_MATCH(DMI_BOARD_NAME, "Z8NR-D12"),
1056 },
1057 .driver_data = &i801_mux_config_asus_z8_d12,
1058 },
1059 {
1060 .matches = {
1061 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1062 DMI_MATCH(DMI_BOARD_NAME, "Z8P(N)H-D12"),
1063 },
1064 .driver_data = &i801_mux_config_asus_z8_d12,
1065 },
1066 {
1067 .matches = {
1068 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1069 DMI_MATCH(DMI_BOARD_NAME, "Z8PG-D18"),
1070 },
1071 .driver_data = &i801_mux_config_asus_z8_d18,
1072 },
1073 {
1074 .matches = {
1075 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1076 DMI_MATCH(DMI_BOARD_NAME, "Z8PE-D18"),
1077 },
1078 .driver_data = &i801_mux_config_asus_z8_d18,
1079 },
1080 {
1081 .matches = {
1082 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1083 DMI_MATCH(DMI_BOARD_NAME, "Z8PS-D12"),
1084 },
1085 .driver_data = &i801_mux_config_asus_z8_d12,
1086 },
1087 { }
1088 };
1089
1090 /* Setup multiplexing if needed */
1091 static int i801_add_mux(struct i801_priv *priv)
1092 {
1093 struct device *dev = &priv->adapter.dev;
1094 const struct i801_mux_config *mux_config;
1095 struct i2c_mux_gpio_platform_data gpio_data;
1096 int err;
1097
1098 if (!priv->mux_drvdata)
1099 return 0;
1100 mux_config = priv->mux_drvdata;
1101
1102 /* Prepare the platform data */
1103 memset(&gpio_data, 0, sizeof(struct i2c_mux_gpio_platform_data));
1104 gpio_data.parent = priv->adapter.nr;
1105 gpio_data.values = mux_config->values;
1106 gpio_data.n_values = mux_config->n_values;
1107 gpio_data.classes = mux_config->classes;
1108 gpio_data.gpio_chip = mux_config->gpio_chip;
1109 gpio_data.gpios = mux_config->gpios;
1110 gpio_data.n_gpios = mux_config->n_gpios;
1111 gpio_data.idle = I2C_MUX_GPIO_NO_IDLE;
1112
1113 /* Register the mux device */
1114 priv->mux_pdev = platform_device_register_data(dev, "i2c-mux-gpio",
1115 PLATFORM_DEVID_AUTO, &gpio_data,
1116 sizeof(struct i2c_mux_gpio_platform_data));
1117 if (IS_ERR(priv->mux_pdev)) {
1118 err = PTR_ERR(priv->mux_pdev);
1119 priv->mux_pdev = NULL;
1120 dev_err(dev, "Failed to register i2c-mux-gpio device\n");
1121 return err;
1122 }
1123
1124 return 0;
1125 }
1126
1127 static void i801_del_mux(struct i801_priv *priv)
1128 {
1129 if (priv->mux_pdev)
1130 platform_device_unregister(priv->mux_pdev);
1131 }
1132
1133 static unsigned int i801_get_adapter_class(struct i801_priv *priv)
1134 {
1135 const struct dmi_system_id *id;
1136 const struct i801_mux_config *mux_config;
1137 unsigned int class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
1138 int i;
1139
1140 id = dmi_first_match(mux_dmi_table);
1141 if (id) {
1142 /* Remove branch classes from trunk */
1143 mux_config = id->driver_data;
1144 for (i = 0; i < mux_config->n_values; i++)
1145 class &= ~mux_config->classes[i];
1146
1147 /* Remember for later */
1148 priv->mux_drvdata = mux_config;
1149 }
1150
1151 return class;
1152 }
1153 #else
1154 static inline int i801_add_mux(struct i801_priv *priv) { return 0; }
1155 static inline void i801_del_mux(struct i801_priv *priv) { }
1156
1157 static inline unsigned int i801_get_adapter_class(struct i801_priv *priv)
1158 {
1159 return I2C_CLASS_HWMON | I2C_CLASS_SPD;
1160 }
1161 #endif
1162
1163 static const struct itco_wdt_platform_data tco_platform_data = {
1164 .name = "Intel PCH",
1165 .version = 4,
1166 };
1167
1168 static DEFINE_SPINLOCK(p2sb_spinlock);
1169
1170 static void i801_add_tco(struct i801_priv *priv)
1171 {
1172 struct pci_dev *pci_dev = priv->pci_dev;
1173 struct resource tco_res[3], *res;
1174 struct platform_device *pdev;
1175 unsigned int devfn;
1176 u32 tco_base, tco_ctl;
1177 u32 base_addr, ctrl_val;
1178 u64 base64_addr;
1179
1180 if (!(priv->features & FEATURE_TCO))
1181 return;
1182
1183 pci_read_config_dword(pci_dev, TCOBASE, &tco_base);
1184 pci_read_config_dword(pci_dev, TCOCTL, &tco_ctl);
1185 if (!(tco_ctl & TCOCTL_EN))
1186 return;
1187
1188 memset(tco_res, 0, sizeof(tco_res));
1189
1190 res = &tco_res[ICH_RES_IO_TCO];
1191 res->start = tco_base & ~1;
1192 res->end = res->start + 32 - 1;
1193 res->flags = IORESOURCE_IO;
1194
1195 /*
1196 * Power Management registers.
1197 */
1198 devfn = PCI_DEVFN(PCI_SLOT(pci_dev->devfn), 2);
1199 pci_bus_read_config_dword(pci_dev->bus, devfn, ACPIBASE, &base_addr);
1200
1201 res = &tco_res[ICH_RES_IO_SMI];
1202 res->start = (base_addr & ~1) + ACPIBASE_SMI_OFF;
1203 res->end = res->start + 3;
1204 res->flags = IORESOURCE_IO;
1205
1206 /*
1207 * Enable the ACPI I/O space.
1208 */
1209 pci_bus_read_config_dword(pci_dev->bus, devfn, ACPICTRL, &ctrl_val);
1210 ctrl_val |= ACPICTRL_EN;
1211 pci_bus_write_config_dword(pci_dev->bus, devfn, ACPICTRL, ctrl_val);
1212
1213 /*
1214 * We must access the NO_REBOOT bit over the Primary to Sideband
1215 * bridge (P2SB). The BIOS prevents the P2SB device from being
1216 * enumerated by the PCI subsystem, so we need to unhide/hide it
1217 * to lookup the P2SB BAR.
1218 */
1219 spin_lock(&p2sb_spinlock);
1220
1221 devfn = PCI_DEVFN(PCI_SLOT(pci_dev->devfn), 1);
1222
1223 /* Unhide the P2SB device */
1224 pci_bus_write_config_byte(pci_dev->bus, devfn, 0xe1, 0x0);
1225
1226 pci_bus_read_config_dword(pci_dev->bus, devfn, SBREG_BAR, &base_addr);
1227 base64_addr = base_addr & 0xfffffff0;
1228
1229 pci_bus_read_config_dword(pci_dev->bus, devfn, SBREG_BAR + 0x4, &base_addr);
1230 base64_addr |= (u64)base_addr << 32;
1231
1232 /* Hide the P2SB device */
1233 pci_bus_write_config_byte(pci_dev->bus, devfn, 0xe1, 0x1);
1234 spin_unlock(&p2sb_spinlock);
1235
1236 res = &tco_res[ICH_RES_MEM_OFF];
1237 res->start = (resource_size_t)base64_addr + SBREG_SMBCTRL;
1238 res->end = res->start + 3;
1239 res->flags = IORESOURCE_MEM;
1240
1241 pdev = platform_device_register_resndata(&pci_dev->dev, "iTCO_wdt", -1,
1242 tco_res, 3, &tco_platform_data,
1243 sizeof(tco_platform_data));
1244 if (IS_ERR(pdev)) {
1245 dev_warn(&pci_dev->dev, "failed to create iTCO device\n");
1246 return;
1247 }
1248
1249 priv->tco_pdev = pdev;
1250 }
1251
1252 static int i801_probe(struct pci_dev *dev, const struct pci_device_id *id)
1253 {
1254 unsigned char temp;
1255 int err, i;
1256 struct i801_priv *priv;
1257
1258 priv = devm_kzalloc(&dev->dev, sizeof(*priv), GFP_KERNEL);
1259 if (!priv)
1260 return -ENOMEM;
1261
1262 i2c_set_adapdata(&priv->adapter, priv);
1263 priv->adapter.owner = THIS_MODULE;
1264 priv->adapter.class = i801_get_adapter_class(priv);
1265 priv->adapter.algo = &smbus_algorithm;
1266 priv->adapter.dev.parent = &dev->dev;
1267 ACPI_COMPANION_SET(&priv->adapter.dev, ACPI_COMPANION(&dev->dev));
1268 priv->adapter.retries = 3;
1269
1270 priv->pci_dev = dev;
1271 switch (dev->device) {
1272 case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS:
1273 case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS:
1274 case PCI_DEVICE_ID_INTEL_DNV_SMBUS:
1275 priv->features |= FEATURE_I2C_BLOCK_READ;
1276 priv->features |= FEATURE_IRQ;
1277 priv->features |= FEATURE_SMBUS_PEC;
1278 priv->features |= FEATURE_BLOCK_BUFFER;
1279 priv->features |= FEATURE_TCO;
1280 break;
1281
1282 case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0:
1283 case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1:
1284 case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2:
1285 case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0:
1286 case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1:
1287 case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2:
1288 priv->features |= FEATURE_IDF;
1289 /* fall through */
1290 default:
1291 priv->features |= FEATURE_I2C_BLOCK_READ;
1292 priv->features |= FEATURE_IRQ;
1293 /* fall through */
1294 case PCI_DEVICE_ID_INTEL_82801DB_3:
1295 priv->features |= FEATURE_SMBUS_PEC;
1296 priv->features |= FEATURE_BLOCK_BUFFER;
1297 /* fall through */
1298 case PCI_DEVICE_ID_INTEL_82801CA_3:
1299 case PCI_DEVICE_ID_INTEL_82801BA_2:
1300 case PCI_DEVICE_ID_INTEL_82801AB_3:
1301 case PCI_DEVICE_ID_INTEL_82801AA_3:
1302 break;
1303 }
1304
1305 /* Disable features on user request */
1306 for (i = 0; i < ARRAY_SIZE(i801_feature_names); i++) {
1307 if (priv->features & disable_features & (1 << i))
1308 dev_notice(&dev->dev, "%s disabled by user\n",
1309 i801_feature_names[i]);
1310 }
1311 priv->features &= ~disable_features;
1312
1313 err = pcim_enable_device(dev);
1314 if (err) {
1315 dev_err(&dev->dev, "Failed to enable SMBus PCI device (%d)\n",
1316 err);
1317 return err;
1318 }
1319 pcim_pin_device(dev);
1320
1321 /* Determine the address of the SMBus area */
1322 priv->smba = pci_resource_start(dev, SMBBAR);
1323 if (!priv->smba) {
1324 dev_err(&dev->dev,
1325 "SMBus base address uninitialized, upgrade BIOS\n");
1326 return -ENODEV;
1327 }
1328
1329 err = acpi_check_resource_conflict(&dev->resource[SMBBAR]);
1330 if (err) {
1331 return -ENODEV;
1332 }
1333
1334 err = pcim_iomap_regions(dev, 1 << SMBBAR,
1335 dev_driver_string(&dev->dev));
1336 if (err) {
1337 dev_err(&dev->dev,
1338 "Failed to request SMBus region 0x%lx-0x%Lx\n",
1339 priv->smba,
1340 (unsigned long long)pci_resource_end(dev, SMBBAR));
1341 return err;
1342 }
1343
1344 pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &temp);
1345 priv->original_hstcfg = temp;
1346 temp &= ~SMBHSTCFG_I2C_EN; /* SMBus timing */
1347 if (!(temp & SMBHSTCFG_HST_EN)) {
1348 dev_info(&dev->dev, "Enabling SMBus device\n");
1349 temp |= SMBHSTCFG_HST_EN;
1350 }
1351 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, temp);
1352
1353 if (temp & SMBHSTCFG_SMB_SMI_EN) {
1354 dev_dbg(&dev->dev, "SMBus using interrupt SMI#\n");
1355 /* Disable SMBus interrupt feature if SMBus using SMI# */
1356 priv->features &= ~FEATURE_IRQ;
1357 }
1358
1359 /* Clear special mode bits */
1360 if (priv->features & (FEATURE_SMBUS_PEC | FEATURE_BLOCK_BUFFER))
1361 outb_p(inb_p(SMBAUXCTL(priv)) &
1362 ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv));
1363
1364 /* Default timeout in interrupt mode: 200 ms */
1365 priv->adapter.timeout = HZ / 5;
1366
1367 if (priv->features & FEATURE_IRQ) {
1368 u16 pcictl, pcists;
1369
1370 /* Complain if an interrupt is already pending */
1371 pci_read_config_word(priv->pci_dev, SMBPCISTS, &pcists);
1372 if (pcists & SMBPCISTS_INTS)
1373 dev_warn(&dev->dev, "An interrupt is pending!\n");
1374
1375 /* Check if interrupts have been disabled */
1376 pci_read_config_word(priv->pci_dev, SMBPCICTL, &pcictl);
1377 if (pcictl & SMBPCICTL_INTDIS) {
1378 dev_info(&dev->dev, "Interrupts are disabled\n");
1379 priv->features &= ~FEATURE_IRQ;
1380 }
1381 }
1382
1383 if (priv->features & FEATURE_IRQ) {
1384 init_waitqueue_head(&priv->waitq);
1385
1386 err = devm_request_irq(&dev->dev, dev->irq, i801_isr,
1387 IRQF_SHARED,
1388 dev_driver_string(&dev->dev), priv);
1389 if (err) {
1390 dev_err(&dev->dev, "Failed to allocate irq %d: %d\n",
1391 dev->irq, err);
1392 priv->features &= ~FEATURE_IRQ;
1393 }
1394 }
1395 dev_info(&dev->dev, "SMBus using %s\n",
1396 priv->features & FEATURE_IRQ ? "PCI interrupt" : "polling");
1397
1398 i801_add_tco(priv);
1399
1400 snprintf(priv->adapter.name, sizeof(priv->adapter.name),
1401 "SMBus I801 adapter at %04lx", priv->smba);
1402 err = i2c_add_adapter(&priv->adapter);
1403 if (err) {
1404 dev_err(&dev->dev, "Failed to add SMBus adapter\n");
1405 return err;
1406 }
1407
1408 i801_probe_optional_slaves(priv);
1409 /* We ignore errors - multiplexing is optional */
1410 i801_add_mux(priv);
1411
1412 pci_set_drvdata(dev, priv);
1413
1414 return 0;
1415 }
1416
1417 static void i801_remove(struct pci_dev *dev)
1418 {
1419 struct i801_priv *priv = pci_get_drvdata(dev);
1420
1421 i801_del_mux(priv);
1422 i2c_del_adapter(&priv->adapter);
1423 pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg);
1424
1425 platform_device_unregister(priv->tco_pdev);
1426
1427 /*
1428 * do not call pci_disable_device(dev) since it can cause hard hangs on
1429 * some systems during power-off (eg. Fujitsu-Siemens Lifebook E8010)
1430 */
1431 }
1432
1433 #ifdef CONFIG_PM
1434 static int i801_suspend(struct pci_dev *dev, pm_message_t mesg)
1435 {
1436 struct i801_priv *priv = pci_get_drvdata(dev);
1437
1438 pci_save_state(dev);
1439 pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg);
1440 pci_set_power_state(dev, pci_choose_state(dev, mesg));
1441 return 0;
1442 }
1443
1444 static int i801_resume(struct pci_dev *dev)
1445 {
1446 pci_set_power_state(dev, PCI_D0);
1447 pci_restore_state(dev);
1448 return 0;
1449 }
1450 #else
1451 #define i801_suspend NULL
1452 #define i801_resume NULL
1453 #endif
1454
1455 static struct pci_driver i801_driver = {
1456 .name = "i801_smbus",
1457 .id_table = i801_ids,
1458 .probe = i801_probe,
1459 .remove = i801_remove,
1460 .suspend = i801_suspend,
1461 .resume = i801_resume,
1462 };
1463
1464 static int __init i2c_i801_init(void)
1465 {
1466 if (dmi_name_in_vendors("FUJITSU"))
1467 input_apanel_init();
1468 return pci_register_driver(&i801_driver);
1469 }
1470
1471 static void __exit i2c_i801_exit(void)
1472 {
1473 pci_unregister_driver(&i801_driver);
1474 }
1475
1476 MODULE_AUTHOR("Mark D. Studebaker <mdsxyz123@yahoo.com>, Jean Delvare <jdelvare@suse.de>");
1477 MODULE_DESCRIPTION("I801 SMBus driver");
1478 MODULE_LICENSE("GPL");
1479
1480 module_init(i2c_i801_init);
1481 module_exit(i2c_i801_exit);
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