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i2c: i801: store and restore the SLVCMD register at load and unload
[mirror_ubuntu-bionic-kernel.git] / drivers / i2c / busses / i2c-i801.c
1 /*
2 Copyright (c) 1998 - 2002 Frodo Looijaard <frodol@dds.nl>,
3 Philip Edelbrock <phil@netroedge.com>, and Mark D. Studebaker
4 <mdsxyz123@yahoo.com>
5 Copyright (C) 2007 - 2014 Jean Delvare <jdelvare@suse.de>
6 Copyright (C) 2010 Intel Corporation,
7 David Woodhouse <dwmw2@infradead.org>
8
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2 of the License, or
12 (at your option) any later version.
13
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
18 */
19
20 /*
21 * Supports the following Intel I/O Controller Hubs (ICH):
22 *
23 * I/O Block I2C
24 * region SMBus Block proc. block
25 * Chip name PCI ID size PEC buffer call read
26 * ---------------------------------------------------------------------------
27 * 82801AA (ICH) 0x2413 16 no no no no
28 * 82801AB (ICH0) 0x2423 16 no no no no
29 * 82801BA (ICH2) 0x2443 16 no no no no
30 * 82801CA (ICH3) 0x2483 32 soft no no no
31 * 82801DB (ICH4) 0x24c3 32 hard yes no no
32 * 82801E (ICH5) 0x24d3 32 hard yes yes yes
33 * 6300ESB 0x25a4 32 hard yes yes yes
34 * 82801F (ICH6) 0x266a 32 hard yes yes yes
35 * 6310ESB/6320ESB 0x269b 32 hard yes yes yes
36 * 82801G (ICH7) 0x27da 32 hard yes yes yes
37 * 82801H (ICH8) 0x283e 32 hard yes yes yes
38 * 82801I (ICH9) 0x2930 32 hard yes yes yes
39 * EP80579 (Tolapai) 0x5032 32 hard yes yes yes
40 * ICH10 0x3a30 32 hard yes yes yes
41 * ICH10 0x3a60 32 hard yes yes yes
42 * 5/3400 Series (PCH) 0x3b30 32 hard yes yes yes
43 * 6 Series (PCH) 0x1c22 32 hard yes yes yes
44 * Patsburg (PCH) 0x1d22 32 hard yes yes yes
45 * Patsburg (PCH) IDF 0x1d70 32 hard yes yes yes
46 * Patsburg (PCH) IDF 0x1d71 32 hard yes yes yes
47 * Patsburg (PCH) IDF 0x1d72 32 hard yes yes yes
48 * DH89xxCC (PCH) 0x2330 32 hard yes yes yes
49 * Panther Point (PCH) 0x1e22 32 hard yes yes yes
50 * Lynx Point (PCH) 0x8c22 32 hard yes yes yes
51 * Lynx Point-LP (PCH) 0x9c22 32 hard yes yes yes
52 * Avoton (SOC) 0x1f3c 32 hard yes yes yes
53 * Wellsburg (PCH) 0x8d22 32 hard yes yes yes
54 * Wellsburg (PCH) MS 0x8d7d 32 hard yes yes yes
55 * Wellsburg (PCH) MS 0x8d7e 32 hard yes yes yes
56 * Wellsburg (PCH) MS 0x8d7f 32 hard yes yes yes
57 * Coleto Creek (PCH) 0x23b0 32 hard yes yes yes
58 * Wildcat Point (PCH) 0x8ca2 32 hard yes yes yes
59 * Wildcat Point-LP (PCH) 0x9ca2 32 hard yes yes yes
60 * BayTrail (SOC) 0x0f12 32 hard yes yes yes
61 * Sunrise Point-H (PCH) 0xa123 32 hard yes yes yes
62 * Sunrise Point-LP (PCH) 0x9d23 32 hard yes yes yes
63 * DNV (SOC) 0x19df 32 hard yes yes yes
64 * Broxton (SOC) 0x5ad4 32 hard yes yes yes
65 * Lewisburg (PCH) 0xa1a3 32 hard yes yes yes
66 * Lewisburg Supersku (PCH) 0xa223 32 hard yes yes yes
67 * Kaby Lake PCH-H (PCH) 0xa2a3 32 hard yes yes yes
68 *
69 * Features supported by this driver:
70 * Software PEC no
71 * Hardware PEC yes
72 * Block buffer yes
73 * Block process call transaction no
74 * I2C block read transaction yes (doesn't use the block buffer)
75 * Slave mode no
76 * SMBus Host Notify yes
77 * Interrupt processing yes
78 *
79 * See the file Documentation/i2c/busses/i2c-i801 for details.
80 */
81
82 #include <linux/interrupt.h>
83 #include <linux/module.h>
84 #include <linux/pci.h>
85 #include <linux/kernel.h>
86 #include <linux/stddef.h>
87 #include <linux/delay.h>
88 #include <linux/ioport.h>
89 #include <linux/init.h>
90 #include <linux/i2c.h>
91 #include <linux/i2c-smbus.h>
92 #include <linux/acpi.h>
93 #include <linux/io.h>
94 #include <linux/dmi.h>
95 #include <linux/slab.h>
96 #include <linux/wait.h>
97 #include <linux/err.h>
98 #include <linux/platform_device.h>
99 #include <linux/platform_data/itco_wdt.h>
100 #include <linux/pm_runtime.h>
101
102 #if IS_ENABLED(CONFIG_I2C_MUX_GPIO) && defined CONFIG_DMI
103 #include <linux/gpio.h>
104 #include <linux/i2c-mux-gpio.h>
105 #endif
106
107 /* I801 SMBus address offsets */
108 #define SMBHSTSTS(p) (0 + (p)->smba)
109 #define SMBHSTCNT(p) (2 + (p)->smba)
110 #define SMBHSTCMD(p) (3 + (p)->smba)
111 #define SMBHSTADD(p) (4 + (p)->smba)
112 #define SMBHSTDAT0(p) (5 + (p)->smba)
113 #define SMBHSTDAT1(p) (6 + (p)->smba)
114 #define SMBBLKDAT(p) (7 + (p)->smba)
115 #define SMBPEC(p) (8 + (p)->smba) /* ICH3 and later */
116 #define SMBAUXSTS(p) (12 + (p)->smba) /* ICH4 and later */
117 #define SMBAUXCTL(p) (13 + (p)->smba) /* ICH4 and later */
118 #define SMBSLVSTS(p) (16 + (p)->smba) /* ICH3 and later */
119 #define SMBSLVCMD(p) (17 + (p)->smba) /* ICH3 and later */
120 #define SMBNTFDADD(p) (20 + (p)->smba) /* ICH3 and later */
121 #define SMBNTFDDAT(p) (22 + (p)->smba) /* ICH3 and later */
122
123 /* PCI Address Constants */
124 #define SMBBAR 4
125 #define SMBPCICTL 0x004
126 #define SMBPCISTS 0x006
127 #define SMBHSTCFG 0x040
128 #define TCOBASE 0x050
129 #define TCOCTL 0x054
130
131 #define ACPIBASE 0x040
132 #define ACPIBASE_SMI_OFF 0x030
133 #define ACPICTRL 0x044
134 #define ACPICTRL_EN 0x080
135
136 #define SBREG_BAR 0x10
137 #define SBREG_SMBCTRL 0xc6000c
138
139 /* Host status bits for SMBPCISTS */
140 #define SMBPCISTS_INTS 0x08
141
142 /* Control bits for SMBPCICTL */
143 #define SMBPCICTL_INTDIS 0x0400
144
145 /* Host configuration bits for SMBHSTCFG */
146 #define SMBHSTCFG_HST_EN 1
147 #define SMBHSTCFG_SMB_SMI_EN 2
148 #define SMBHSTCFG_I2C_EN 4
149 #define SMBHSTCFG_SPD_WD 0x10
150
151 /* TCO configuration bits for TCOCTL */
152 #define TCOCTL_EN 0x0100
153
154 /* Auxiliary status register bits, ICH4+ only */
155 #define SMBAUXSTS_CRCE 1
156 #define SMBAUXSTS_STCO 2
157
158 /* Auxiliary control register bits, ICH4+ only */
159 #define SMBAUXCTL_CRC 1
160 #define SMBAUXCTL_E32B 2
161
162 /* Other settings */
163 #define MAX_RETRIES 400
164
165 /* I801 command constants */
166 #define I801_QUICK 0x00
167 #define I801_BYTE 0x04
168 #define I801_BYTE_DATA 0x08
169 #define I801_WORD_DATA 0x0C
170 #define I801_PROC_CALL 0x10 /* unimplemented */
171 #define I801_BLOCK_DATA 0x14
172 #define I801_I2C_BLOCK_DATA 0x18 /* ICH5 and later */
173
174 /* I801 Host Control register bits */
175 #define SMBHSTCNT_INTREN 0x01
176 #define SMBHSTCNT_KILL 0x02
177 #define SMBHSTCNT_LAST_BYTE 0x20
178 #define SMBHSTCNT_START 0x40
179 #define SMBHSTCNT_PEC_EN 0x80 /* ICH3 and later */
180
181 /* I801 Hosts Status register bits */
182 #define SMBHSTSTS_BYTE_DONE 0x80
183 #define SMBHSTSTS_INUSE_STS 0x40
184 #define SMBHSTSTS_SMBALERT_STS 0x20
185 #define SMBHSTSTS_FAILED 0x10
186 #define SMBHSTSTS_BUS_ERR 0x08
187 #define SMBHSTSTS_DEV_ERR 0x04
188 #define SMBHSTSTS_INTR 0x02
189 #define SMBHSTSTS_HOST_BUSY 0x01
190
191 /* Host Notify Status registers bits */
192 #define SMBSLVSTS_HST_NTFY_STS 1
193
194 /* Host Notify Command registers bits */
195 #define SMBSLVCMD_HST_NTFY_INTREN 0x01
196
197 #define STATUS_ERROR_FLAGS (SMBHSTSTS_FAILED | SMBHSTSTS_BUS_ERR | \
198 SMBHSTSTS_DEV_ERR)
199
200 #define STATUS_FLAGS (SMBHSTSTS_BYTE_DONE | SMBHSTSTS_INTR | \
201 STATUS_ERROR_FLAGS)
202
203 /* Older devices have their ID defined in <linux/pci_ids.h> */
204 #define PCI_DEVICE_ID_INTEL_BAYTRAIL_SMBUS 0x0f12
205 #define PCI_DEVICE_ID_INTEL_DNV_SMBUS 0x19df
206 #define PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS 0x1c22
207 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS 0x1d22
208 /* Patsburg also has three 'Integrated Device Function' SMBus controllers */
209 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0 0x1d70
210 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1 0x1d71
211 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2 0x1d72
212 #define PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS 0x1e22
213 #define PCI_DEVICE_ID_INTEL_AVOTON_SMBUS 0x1f3c
214 #define PCI_DEVICE_ID_INTEL_BRASWELL_SMBUS 0x2292
215 #define PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS 0x2330
216 #define PCI_DEVICE_ID_INTEL_COLETOCREEK_SMBUS 0x23b0
217 #define PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS 0x3b30
218 #define PCI_DEVICE_ID_INTEL_BROXTON_SMBUS 0x5ad4
219 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS 0x8c22
220 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_SMBUS 0x8ca2
221 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS 0x8d22
222 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0 0x8d7d
223 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1 0x8d7e
224 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2 0x8d7f
225 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS 0x9c22
226 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_SMBUS 0x9ca2
227 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS 0x9d23
228 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS 0xa123
229 #define PCI_DEVICE_ID_INTEL_LEWISBURG_SMBUS 0xa1a3
230 #define PCI_DEVICE_ID_INTEL_LEWISBURG_SSKU_SMBUS 0xa223
231 #define PCI_DEVICE_ID_INTEL_KABYLAKE_PCH_H_SMBUS 0xa2a3
232
233 struct i801_mux_config {
234 char *gpio_chip;
235 unsigned values[3];
236 int n_values;
237 unsigned classes[3];
238 unsigned gpios[2]; /* Relative to gpio_chip->base */
239 int n_gpios;
240 };
241
242 struct i801_priv {
243 struct i2c_adapter adapter;
244 unsigned long smba;
245 unsigned char original_hstcfg;
246 unsigned char original_slvcmd;
247 struct pci_dev *pci_dev;
248 unsigned int features;
249
250 /* isr processing */
251 wait_queue_head_t waitq;
252 u8 status;
253
254 /* Command state used by isr for byte-by-byte block transactions */
255 u8 cmd;
256 bool is_read;
257 int count;
258 int len;
259 u8 *data;
260
261 #if IS_ENABLED(CONFIG_I2C_MUX_GPIO) && defined CONFIG_DMI
262 const struct i801_mux_config *mux_drvdata;
263 struct platform_device *mux_pdev;
264 #endif
265 struct platform_device *tco_pdev;
266
267 /*
268 * If set to true the host controller registers are reserved for
269 * ACPI AML use. Protected by acpi_lock.
270 */
271 bool acpi_reserved;
272 struct mutex acpi_lock;
273 struct smbus_host_notify *host_notify;
274 };
275
276 #define SMBHSTNTFY_SIZE 8
277
278 #define FEATURE_SMBUS_PEC (1 << 0)
279 #define FEATURE_BLOCK_BUFFER (1 << 1)
280 #define FEATURE_BLOCK_PROC (1 << 2)
281 #define FEATURE_I2C_BLOCK_READ (1 << 3)
282 #define FEATURE_IRQ (1 << 4)
283 #define FEATURE_HOST_NOTIFY (1 << 5)
284 /* Not really a feature, but it's convenient to handle it as such */
285 #define FEATURE_IDF (1 << 15)
286 #define FEATURE_TCO (1 << 16)
287
288 static const char *i801_feature_names[] = {
289 "SMBus PEC",
290 "Block buffer",
291 "Block process call",
292 "I2C block read",
293 "Interrupt",
294 "SMBus Host Notify",
295 };
296
297 static unsigned int disable_features;
298 module_param(disable_features, uint, S_IRUGO | S_IWUSR);
299 MODULE_PARM_DESC(disable_features, "Disable selected driver features:\n"
300 "\t\t 0x01 disable SMBus PEC\n"
301 "\t\t 0x02 disable the block buffer\n"
302 "\t\t 0x08 disable the I2C block read functionality\n"
303 "\t\t 0x10 don't use interrupts\n"
304 "\t\t 0x20 disable SMBus Host Notify ");
305
306 /* Make sure the SMBus host is ready to start transmitting.
307 Return 0 if it is, -EBUSY if it is not. */
308 static int i801_check_pre(struct i801_priv *priv)
309 {
310 int status;
311
312 status = inb_p(SMBHSTSTS(priv));
313 if (status & SMBHSTSTS_HOST_BUSY) {
314 dev_err(&priv->pci_dev->dev, "SMBus is busy, can't use it!\n");
315 return -EBUSY;
316 }
317
318 status &= STATUS_FLAGS;
319 if (status) {
320 dev_dbg(&priv->pci_dev->dev, "Clearing status flags (%02x)\n",
321 status);
322 outb_p(status, SMBHSTSTS(priv));
323 status = inb_p(SMBHSTSTS(priv)) & STATUS_FLAGS;
324 if (status) {
325 dev_err(&priv->pci_dev->dev,
326 "Failed clearing status flags (%02x)\n",
327 status);
328 return -EBUSY;
329 }
330 }
331
332 /*
333 * Clear CRC status if needed.
334 * During normal operation, i801_check_post() takes care
335 * of it after every operation. We do it here only in case
336 * the hardware was already in this state when the driver
337 * started.
338 */
339 if (priv->features & FEATURE_SMBUS_PEC) {
340 status = inb_p(SMBAUXSTS(priv)) & SMBAUXSTS_CRCE;
341 if (status) {
342 dev_dbg(&priv->pci_dev->dev,
343 "Clearing aux status flags (%02x)\n", status);
344 outb_p(status, SMBAUXSTS(priv));
345 status = inb_p(SMBAUXSTS(priv)) & SMBAUXSTS_CRCE;
346 if (status) {
347 dev_err(&priv->pci_dev->dev,
348 "Failed clearing aux status flags (%02x)\n",
349 status);
350 return -EBUSY;
351 }
352 }
353 }
354
355 return 0;
356 }
357
358 /*
359 * Convert the status register to an error code, and clear it.
360 * Note that status only contains the bits we want to clear, not the
361 * actual register value.
362 */
363 static int i801_check_post(struct i801_priv *priv, int status)
364 {
365 int result = 0;
366
367 /*
368 * If the SMBus is still busy, we give up
369 * Note: This timeout condition only happens when using polling
370 * transactions. For interrupt operation, NAK/timeout is indicated by
371 * DEV_ERR.
372 */
373 if (unlikely(status < 0)) {
374 dev_err(&priv->pci_dev->dev, "Transaction timeout\n");
375 /* try to stop the current command */
376 dev_dbg(&priv->pci_dev->dev, "Terminating the current operation\n");
377 outb_p(inb_p(SMBHSTCNT(priv)) | SMBHSTCNT_KILL,
378 SMBHSTCNT(priv));
379 usleep_range(1000, 2000);
380 outb_p(inb_p(SMBHSTCNT(priv)) & (~SMBHSTCNT_KILL),
381 SMBHSTCNT(priv));
382
383 /* Check if it worked */
384 status = inb_p(SMBHSTSTS(priv));
385 if ((status & SMBHSTSTS_HOST_BUSY) ||
386 !(status & SMBHSTSTS_FAILED))
387 dev_err(&priv->pci_dev->dev,
388 "Failed terminating the transaction\n");
389 outb_p(STATUS_FLAGS, SMBHSTSTS(priv));
390 return -ETIMEDOUT;
391 }
392
393 if (status & SMBHSTSTS_FAILED) {
394 result = -EIO;
395 dev_err(&priv->pci_dev->dev, "Transaction failed\n");
396 }
397 if (status & SMBHSTSTS_DEV_ERR) {
398 /*
399 * This may be a PEC error, check and clear it.
400 *
401 * AUXSTS is handled differently from HSTSTS.
402 * For HSTSTS, i801_isr() or i801_wait_intr()
403 * has already cleared the error bits in hardware,
404 * and we are passed a copy of the original value
405 * in "status".
406 * For AUXSTS, the hardware register is left
407 * for us to handle here.
408 * This is asymmetric, slightly iffy, but safe,
409 * since all this code is serialized and the CRCE
410 * bit is harmless as long as it's cleared before
411 * the next operation.
412 */
413 if ((priv->features & FEATURE_SMBUS_PEC) &&
414 (inb_p(SMBAUXSTS(priv)) & SMBAUXSTS_CRCE)) {
415 outb_p(SMBAUXSTS_CRCE, SMBAUXSTS(priv));
416 result = -EBADMSG;
417 dev_dbg(&priv->pci_dev->dev, "PEC error\n");
418 } else {
419 result = -ENXIO;
420 dev_dbg(&priv->pci_dev->dev, "No response\n");
421 }
422 }
423 if (status & SMBHSTSTS_BUS_ERR) {
424 result = -EAGAIN;
425 dev_dbg(&priv->pci_dev->dev, "Lost arbitration\n");
426 }
427
428 /* Clear status flags except BYTE_DONE, to be cleared by caller */
429 outb_p(status, SMBHSTSTS(priv));
430
431 return result;
432 }
433
434 /* Wait for BUSY being cleared and either INTR or an error flag being set */
435 static int i801_wait_intr(struct i801_priv *priv)
436 {
437 int timeout = 0;
438 int status;
439
440 /* We will always wait for a fraction of a second! */
441 do {
442 usleep_range(250, 500);
443 status = inb_p(SMBHSTSTS(priv));
444 } while (((status & SMBHSTSTS_HOST_BUSY) ||
445 !(status & (STATUS_ERROR_FLAGS | SMBHSTSTS_INTR))) &&
446 (timeout++ < MAX_RETRIES));
447
448 if (timeout > MAX_RETRIES) {
449 dev_dbg(&priv->pci_dev->dev, "INTR Timeout!\n");
450 return -ETIMEDOUT;
451 }
452 return status & (STATUS_ERROR_FLAGS | SMBHSTSTS_INTR);
453 }
454
455 /* Wait for either BYTE_DONE or an error flag being set */
456 static int i801_wait_byte_done(struct i801_priv *priv)
457 {
458 int timeout = 0;
459 int status;
460
461 /* We will always wait for a fraction of a second! */
462 do {
463 usleep_range(250, 500);
464 status = inb_p(SMBHSTSTS(priv));
465 } while (!(status & (STATUS_ERROR_FLAGS | SMBHSTSTS_BYTE_DONE)) &&
466 (timeout++ < MAX_RETRIES));
467
468 if (timeout > MAX_RETRIES) {
469 dev_dbg(&priv->pci_dev->dev, "BYTE_DONE Timeout!\n");
470 return -ETIMEDOUT;
471 }
472 return status & STATUS_ERROR_FLAGS;
473 }
474
475 static int i801_transaction(struct i801_priv *priv, int xact)
476 {
477 int status;
478 int result;
479 const struct i2c_adapter *adap = &priv->adapter;
480
481 result = i801_check_pre(priv);
482 if (result < 0)
483 return result;
484
485 if (priv->features & FEATURE_IRQ) {
486 outb_p(xact | SMBHSTCNT_INTREN | SMBHSTCNT_START,
487 SMBHSTCNT(priv));
488 result = wait_event_timeout(priv->waitq,
489 (status = priv->status),
490 adap->timeout);
491 if (!result) {
492 status = -ETIMEDOUT;
493 dev_warn(&priv->pci_dev->dev,
494 "Timeout waiting for interrupt!\n");
495 }
496 priv->status = 0;
497 return i801_check_post(priv, status);
498 }
499
500 /* the current contents of SMBHSTCNT can be overwritten, since PEC,
501 * SMBSCMD are passed in xact */
502 outb_p(xact | SMBHSTCNT_START, SMBHSTCNT(priv));
503
504 status = i801_wait_intr(priv);
505 return i801_check_post(priv, status);
506 }
507
508 static int i801_block_transaction_by_block(struct i801_priv *priv,
509 union i2c_smbus_data *data,
510 char read_write, int hwpec)
511 {
512 int i, len;
513 int status;
514
515 inb_p(SMBHSTCNT(priv)); /* reset the data buffer index */
516
517 /* Use 32-byte buffer to process this transaction */
518 if (read_write == I2C_SMBUS_WRITE) {
519 len = data->block[0];
520 outb_p(len, SMBHSTDAT0(priv));
521 for (i = 0; i < len; i++)
522 outb_p(data->block[i+1], SMBBLKDAT(priv));
523 }
524
525 status = i801_transaction(priv, I801_BLOCK_DATA |
526 (hwpec ? SMBHSTCNT_PEC_EN : 0));
527 if (status)
528 return status;
529
530 if (read_write == I2C_SMBUS_READ) {
531 len = inb_p(SMBHSTDAT0(priv));
532 if (len < 1 || len > I2C_SMBUS_BLOCK_MAX)
533 return -EPROTO;
534
535 data->block[0] = len;
536 for (i = 0; i < len; i++)
537 data->block[i + 1] = inb_p(SMBBLKDAT(priv));
538 }
539 return 0;
540 }
541
542 static void i801_isr_byte_done(struct i801_priv *priv)
543 {
544 if (priv->is_read) {
545 /* For SMBus block reads, length is received with first byte */
546 if (((priv->cmd & 0x1c) == I801_BLOCK_DATA) &&
547 (priv->count == 0)) {
548 priv->len = inb_p(SMBHSTDAT0(priv));
549 if (priv->len < 1 || priv->len > I2C_SMBUS_BLOCK_MAX) {
550 dev_err(&priv->pci_dev->dev,
551 "Illegal SMBus block read size %d\n",
552 priv->len);
553 /* FIXME: Recover */
554 priv->len = I2C_SMBUS_BLOCK_MAX;
555 } else {
556 dev_dbg(&priv->pci_dev->dev,
557 "SMBus block read size is %d\n",
558 priv->len);
559 }
560 priv->data[-1] = priv->len;
561 }
562
563 /* Read next byte */
564 if (priv->count < priv->len)
565 priv->data[priv->count++] = inb(SMBBLKDAT(priv));
566 else
567 dev_dbg(&priv->pci_dev->dev,
568 "Discarding extra byte on block read\n");
569
570 /* Set LAST_BYTE for last byte of read transaction */
571 if (priv->count == priv->len - 1)
572 outb_p(priv->cmd | SMBHSTCNT_LAST_BYTE,
573 SMBHSTCNT(priv));
574 } else if (priv->count < priv->len - 1) {
575 /* Write next byte, except for IRQ after last byte */
576 outb_p(priv->data[++priv->count], SMBBLKDAT(priv));
577 }
578
579 /* Clear BYTE_DONE to continue with next byte */
580 outb_p(SMBHSTSTS_BYTE_DONE, SMBHSTSTS(priv));
581 }
582
583 static irqreturn_t i801_host_notify_isr(struct i801_priv *priv)
584 {
585 unsigned short addr;
586 unsigned int data;
587
588 addr = inb_p(SMBNTFDADD(priv)) >> 1;
589 data = inw_p(SMBNTFDDAT(priv));
590
591 i2c_handle_smbus_host_notify(priv->host_notify, addr, data);
592
593 /* clear Host Notify bit and return */
594 outb_p(SMBSLVSTS_HST_NTFY_STS, SMBSLVSTS(priv));
595 return IRQ_HANDLED;
596 }
597
598 /*
599 * There are three kinds of interrupts:
600 *
601 * 1) i801 signals transaction completion with one of these interrupts:
602 * INTR - Success
603 * DEV_ERR - Invalid command, NAK or communication timeout
604 * BUS_ERR - SMI# transaction collision
605 * FAILED - transaction was canceled due to a KILL request
606 * When any of these occur, update ->status and wake up the waitq.
607 * ->status must be cleared before kicking off the next transaction.
608 *
609 * 2) For byte-by-byte (I2C read/write) transactions, one BYTE_DONE interrupt
610 * occurs for each byte of a byte-by-byte to prepare the next byte.
611 *
612 * 3) Host Notify interrupts
613 */
614 static irqreturn_t i801_isr(int irq, void *dev_id)
615 {
616 struct i801_priv *priv = dev_id;
617 u16 pcists;
618 u8 status;
619
620 /* Confirm this is our interrupt */
621 pci_read_config_word(priv->pci_dev, SMBPCISTS, &pcists);
622 if (!(pcists & SMBPCISTS_INTS))
623 return IRQ_NONE;
624
625 if (priv->features & FEATURE_HOST_NOTIFY) {
626 status = inb_p(SMBSLVSTS(priv));
627 if (status & SMBSLVSTS_HST_NTFY_STS)
628 return i801_host_notify_isr(priv);
629 }
630
631 status = inb_p(SMBHSTSTS(priv));
632 if (status & SMBHSTSTS_BYTE_DONE)
633 i801_isr_byte_done(priv);
634
635 /*
636 * Clear irq sources and report transaction result.
637 * ->status must be cleared before the next transaction is started.
638 */
639 status &= SMBHSTSTS_INTR | STATUS_ERROR_FLAGS;
640 if (status) {
641 outb_p(status, SMBHSTSTS(priv));
642 priv->status = status;
643 wake_up(&priv->waitq);
644 }
645
646 return IRQ_HANDLED;
647 }
648
649 /*
650 * For "byte-by-byte" block transactions:
651 * I2C write uses cmd=I801_BLOCK_DATA, I2C_EN=1
652 * I2C read uses cmd=I801_I2C_BLOCK_DATA
653 */
654 static int i801_block_transaction_byte_by_byte(struct i801_priv *priv,
655 union i2c_smbus_data *data,
656 char read_write, int command,
657 int hwpec)
658 {
659 int i, len;
660 int smbcmd;
661 int status;
662 int result;
663 const struct i2c_adapter *adap = &priv->adapter;
664
665 result = i801_check_pre(priv);
666 if (result < 0)
667 return result;
668
669 len = data->block[0];
670
671 if (read_write == I2C_SMBUS_WRITE) {
672 outb_p(len, SMBHSTDAT0(priv));
673 outb_p(data->block[1], SMBBLKDAT(priv));
674 }
675
676 if (command == I2C_SMBUS_I2C_BLOCK_DATA &&
677 read_write == I2C_SMBUS_READ)
678 smbcmd = I801_I2C_BLOCK_DATA;
679 else
680 smbcmd = I801_BLOCK_DATA;
681
682 if (priv->features & FEATURE_IRQ) {
683 priv->is_read = (read_write == I2C_SMBUS_READ);
684 if (len == 1 && priv->is_read)
685 smbcmd |= SMBHSTCNT_LAST_BYTE;
686 priv->cmd = smbcmd | SMBHSTCNT_INTREN;
687 priv->len = len;
688 priv->count = 0;
689 priv->data = &data->block[1];
690
691 outb_p(priv->cmd | SMBHSTCNT_START, SMBHSTCNT(priv));
692 result = wait_event_timeout(priv->waitq,
693 (status = priv->status),
694 adap->timeout);
695 if (!result) {
696 status = -ETIMEDOUT;
697 dev_warn(&priv->pci_dev->dev,
698 "Timeout waiting for interrupt!\n");
699 }
700 priv->status = 0;
701 return i801_check_post(priv, status);
702 }
703
704 for (i = 1; i <= len; i++) {
705 if (i == len && read_write == I2C_SMBUS_READ)
706 smbcmd |= SMBHSTCNT_LAST_BYTE;
707 outb_p(smbcmd, SMBHSTCNT(priv));
708
709 if (i == 1)
710 outb_p(inb(SMBHSTCNT(priv)) | SMBHSTCNT_START,
711 SMBHSTCNT(priv));
712
713 status = i801_wait_byte_done(priv);
714 if (status)
715 goto exit;
716
717 if (i == 1 && read_write == I2C_SMBUS_READ
718 && command != I2C_SMBUS_I2C_BLOCK_DATA) {
719 len = inb_p(SMBHSTDAT0(priv));
720 if (len < 1 || len > I2C_SMBUS_BLOCK_MAX) {
721 dev_err(&priv->pci_dev->dev,
722 "Illegal SMBus block read size %d\n",
723 len);
724 /* Recover */
725 while (inb_p(SMBHSTSTS(priv)) &
726 SMBHSTSTS_HOST_BUSY)
727 outb_p(SMBHSTSTS_BYTE_DONE,
728 SMBHSTSTS(priv));
729 outb_p(SMBHSTSTS_INTR, SMBHSTSTS(priv));
730 return -EPROTO;
731 }
732 data->block[0] = len;
733 }
734
735 /* Retrieve/store value in SMBBLKDAT */
736 if (read_write == I2C_SMBUS_READ)
737 data->block[i] = inb_p(SMBBLKDAT(priv));
738 if (read_write == I2C_SMBUS_WRITE && i+1 <= len)
739 outb_p(data->block[i+1], SMBBLKDAT(priv));
740
741 /* signals SMBBLKDAT ready */
742 outb_p(SMBHSTSTS_BYTE_DONE, SMBHSTSTS(priv));
743 }
744
745 status = i801_wait_intr(priv);
746 exit:
747 return i801_check_post(priv, status);
748 }
749
750 static int i801_set_block_buffer_mode(struct i801_priv *priv)
751 {
752 outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_E32B, SMBAUXCTL(priv));
753 if ((inb_p(SMBAUXCTL(priv)) & SMBAUXCTL_E32B) == 0)
754 return -EIO;
755 return 0;
756 }
757
758 /* Block transaction function */
759 static int i801_block_transaction(struct i801_priv *priv,
760 union i2c_smbus_data *data, char read_write,
761 int command, int hwpec)
762 {
763 int result = 0;
764 unsigned char hostc;
765
766 if (command == I2C_SMBUS_I2C_BLOCK_DATA) {
767 if (read_write == I2C_SMBUS_WRITE) {
768 /* set I2C_EN bit in configuration register */
769 pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &hostc);
770 pci_write_config_byte(priv->pci_dev, SMBHSTCFG,
771 hostc | SMBHSTCFG_I2C_EN);
772 } else if (!(priv->features & FEATURE_I2C_BLOCK_READ)) {
773 dev_err(&priv->pci_dev->dev,
774 "I2C block read is unsupported!\n");
775 return -EOPNOTSUPP;
776 }
777 }
778
779 if (read_write == I2C_SMBUS_WRITE
780 || command == I2C_SMBUS_I2C_BLOCK_DATA) {
781 if (data->block[0] < 1)
782 data->block[0] = 1;
783 if (data->block[0] > I2C_SMBUS_BLOCK_MAX)
784 data->block[0] = I2C_SMBUS_BLOCK_MAX;
785 } else {
786 data->block[0] = 32; /* max for SMBus block reads */
787 }
788
789 /* Experience has shown that the block buffer can only be used for
790 SMBus (not I2C) block transactions, even though the datasheet
791 doesn't mention this limitation. */
792 if ((priv->features & FEATURE_BLOCK_BUFFER)
793 && command != I2C_SMBUS_I2C_BLOCK_DATA
794 && i801_set_block_buffer_mode(priv) == 0)
795 result = i801_block_transaction_by_block(priv, data,
796 read_write, hwpec);
797 else
798 result = i801_block_transaction_byte_by_byte(priv, data,
799 read_write,
800 command, hwpec);
801
802 if (command == I2C_SMBUS_I2C_BLOCK_DATA
803 && read_write == I2C_SMBUS_WRITE) {
804 /* restore saved configuration register value */
805 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, hostc);
806 }
807 return result;
808 }
809
810 /* Return negative errno on error. */
811 static s32 i801_access(struct i2c_adapter *adap, u16 addr,
812 unsigned short flags, char read_write, u8 command,
813 int size, union i2c_smbus_data *data)
814 {
815 int hwpec;
816 int block = 0;
817 int ret = 0, xact = 0;
818 struct i801_priv *priv = i2c_get_adapdata(adap);
819
820 mutex_lock(&priv->acpi_lock);
821 if (priv->acpi_reserved) {
822 mutex_unlock(&priv->acpi_lock);
823 return -EBUSY;
824 }
825
826 pm_runtime_get_sync(&priv->pci_dev->dev);
827
828 hwpec = (priv->features & FEATURE_SMBUS_PEC) && (flags & I2C_CLIENT_PEC)
829 && size != I2C_SMBUS_QUICK
830 && size != I2C_SMBUS_I2C_BLOCK_DATA;
831
832 switch (size) {
833 case I2C_SMBUS_QUICK:
834 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
835 SMBHSTADD(priv));
836 xact = I801_QUICK;
837 break;
838 case I2C_SMBUS_BYTE:
839 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
840 SMBHSTADD(priv));
841 if (read_write == I2C_SMBUS_WRITE)
842 outb_p(command, SMBHSTCMD(priv));
843 xact = I801_BYTE;
844 break;
845 case I2C_SMBUS_BYTE_DATA:
846 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
847 SMBHSTADD(priv));
848 outb_p(command, SMBHSTCMD(priv));
849 if (read_write == I2C_SMBUS_WRITE)
850 outb_p(data->byte, SMBHSTDAT0(priv));
851 xact = I801_BYTE_DATA;
852 break;
853 case I2C_SMBUS_WORD_DATA:
854 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
855 SMBHSTADD(priv));
856 outb_p(command, SMBHSTCMD(priv));
857 if (read_write == I2C_SMBUS_WRITE) {
858 outb_p(data->word & 0xff, SMBHSTDAT0(priv));
859 outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1(priv));
860 }
861 xact = I801_WORD_DATA;
862 break;
863 case I2C_SMBUS_BLOCK_DATA:
864 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
865 SMBHSTADD(priv));
866 outb_p(command, SMBHSTCMD(priv));
867 block = 1;
868 break;
869 case I2C_SMBUS_I2C_BLOCK_DATA:
870 /*
871 * NB: page 240 of ICH5 datasheet shows that the R/#W
872 * bit should be cleared here, even when reading.
873 * However if SPD Write Disable is set (Lynx Point and later),
874 * the read will fail if we don't set the R/#W bit.
875 */
876 outb_p(((addr & 0x7f) << 1) |
877 ((priv->original_hstcfg & SMBHSTCFG_SPD_WD) ?
878 (read_write & 0x01) : 0),
879 SMBHSTADD(priv));
880 if (read_write == I2C_SMBUS_READ) {
881 /* NB: page 240 of ICH5 datasheet also shows
882 * that DATA1 is the cmd field when reading */
883 outb_p(command, SMBHSTDAT1(priv));
884 } else
885 outb_p(command, SMBHSTCMD(priv));
886 block = 1;
887 break;
888 default:
889 dev_err(&priv->pci_dev->dev, "Unsupported transaction %d\n",
890 size);
891 ret = -EOPNOTSUPP;
892 goto out;
893 }
894
895 if (hwpec) /* enable/disable hardware PEC */
896 outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_CRC, SMBAUXCTL(priv));
897 else
898 outb_p(inb_p(SMBAUXCTL(priv)) & (~SMBAUXCTL_CRC),
899 SMBAUXCTL(priv));
900
901 if (block)
902 ret = i801_block_transaction(priv, data, read_write, size,
903 hwpec);
904 else
905 ret = i801_transaction(priv, xact);
906
907 /* Some BIOSes don't like it when PEC is enabled at reboot or resume
908 time, so we forcibly disable it after every transaction. Turn off
909 E32B for the same reason. */
910 if (hwpec || block)
911 outb_p(inb_p(SMBAUXCTL(priv)) &
912 ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv));
913
914 if (block)
915 goto out;
916 if (ret)
917 goto out;
918 if ((read_write == I2C_SMBUS_WRITE) || (xact == I801_QUICK))
919 goto out;
920
921 switch (xact & 0x7f) {
922 case I801_BYTE: /* Result put in SMBHSTDAT0 */
923 case I801_BYTE_DATA:
924 data->byte = inb_p(SMBHSTDAT0(priv));
925 break;
926 case I801_WORD_DATA:
927 data->word = inb_p(SMBHSTDAT0(priv)) +
928 (inb_p(SMBHSTDAT1(priv)) << 8);
929 break;
930 }
931
932 out:
933 pm_runtime_mark_last_busy(&priv->pci_dev->dev);
934 pm_runtime_put_autosuspend(&priv->pci_dev->dev);
935 mutex_unlock(&priv->acpi_lock);
936 return ret;
937 }
938
939
940 static u32 i801_func(struct i2c_adapter *adapter)
941 {
942 struct i801_priv *priv = i2c_get_adapdata(adapter);
943
944 return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
945 I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
946 I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_WRITE_I2C_BLOCK |
947 ((priv->features & FEATURE_SMBUS_PEC) ? I2C_FUNC_SMBUS_PEC : 0) |
948 ((priv->features & FEATURE_I2C_BLOCK_READ) ?
949 I2C_FUNC_SMBUS_READ_I2C_BLOCK : 0) |
950 ((priv->features & FEATURE_HOST_NOTIFY) ?
951 I2C_FUNC_SMBUS_HOST_NOTIFY : 0);
952 }
953
954 static int i801_enable_host_notify(struct i2c_adapter *adapter)
955 {
956 struct i801_priv *priv = i2c_get_adapdata(adapter);
957
958 if (!(priv->features & FEATURE_HOST_NOTIFY))
959 return -ENOTSUPP;
960
961 if (!priv->host_notify)
962 priv->host_notify = i2c_setup_smbus_host_notify(adapter);
963 if (!priv->host_notify)
964 return -ENOMEM;
965
966 priv->original_slvcmd = inb_p(SMBSLVCMD(priv));
967
968 if (!(SMBSLVCMD_HST_NTFY_INTREN & priv->original_slvcmd))
969 outb_p(SMBSLVCMD_HST_NTFY_INTREN | priv->original_slvcmd,
970 SMBSLVCMD(priv));
971
972 /* clear Host Notify bit to allow a new notification */
973 outb_p(SMBSLVSTS_HST_NTFY_STS, SMBSLVSTS(priv));
974
975 return 0;
976 }
977
978 static void i801_disable_host_notify(struct i801_priv *priv)
979 {
980 if (!(priv->features & FEATURE_HOST_NOTIFY))
981 return;
982
983 outb_p(priv->original_slvcmd, SMBSLVCMD(priv));
984 }
985
986 static const struct i2c_algorithm smbus_algorithm = {
987 .smbus_xfer = i801_access,
988 .functionality = i801_func,
989 };
990
991 static const struct pci_device_id i801_ids[] = {
992 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_3) },
993 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_3) },
994 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_2) },
995 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_3) },
996 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_3) },
997 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_3) },
998 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_4) },
999 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_16) },
1000 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_17) },
1001 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_17) },
1002 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_5) },
1003 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_6) },
1004 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EP80579_1) },
1005 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_4) },
1006 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_5) },
1007 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS) },
1008 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS) },
1009 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS) },
1010 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0) },
1011 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1) },
1012 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2) },
1013 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS) },
1014 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS) },
1015 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS) },
1016 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS) },
1017 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_AVOTON_SMBUS) },
1018 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS) },
1019 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0) },
1020 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1) },
1021 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2) },
1022 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COLETOCREEK_SMBUS) },
1023 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WILDCATPOINT_SMBUS) },
1024 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_SMBUS) },
1025 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BAYTRAIL_SMBUS) },
1026 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BRASWELL_SMBUS) },
1027 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS) },
1028 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS) },
1029 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_DNV_SMBUS) },
1030 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BROXTON_SMBUS) },
1031 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LEWISBURG_SMBUS) },
1032 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LEWISBURG_SSKU_SMBUS) },
1033 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_KABYLAKE_PCH_H_SMBUS) },
1034 { 0, }
1035 };
1036
1037 MODULE_DEVICE_TABLE(pci, i801_ids);
1038
1039 #if defined CONFIG_X86 && defined CONFIG_DMI
1040 static unsigned char apanel_addr;
1041
1042 /* Scan the system ROM for the signature "FJKEYINF" */
1043 static __init const void __iomem *bios_signature(const void __iomem *bios)
1044 {
1045 ssize_t offset;
1046 const unsigned char signature[] = "FJKEYINF";
1047
1048 for (offset = 0; offset < 0x10000; offset += 0x10) {
1049 if (check_signature(bios + offset, signature,
1050 sizeof(signature)-1))
1051 return bios + offset;
1052 }
1053 return NULL;
1054 }
1055
1056 static void __init input_apanel_init(void)
1057 {
1058 void __iomem *bios;
1059 const void __iomem *p;
1060
1061 bios = ioremap(0xF0000, 0x10000); /* Can't fail */
1062 p = bios_signature(bios);
1063 if (p) {
1064 /* just use the first address */
1065 apanel_addr = readb(p + 8 + 3) >> 1;
1066 }
1067 iounmap(bios);
1068 }
1069
1070 struct dmi_onboard_device_info {
1071 const char *name;
1072 u8 type;
1073 unsigned short i2c_addr;
1074 const char *i2c_type;
1075 };
1076
1077 static const struct dmi_onboard_device_info dmi_devices[] = {
1078 { "Syleus", DMI_DEV_TYPE_OTHER, 0x73, "fscsyl" },
1079 { "Hermes", DMI_DEV_TYPE_OTHER, 0x73, "fscher" },
1080 { "Hades", DMI_DEV_TYPE_OTHER, 0x73, "fschds" },
1081 };
1082
1083 static void dmi_check_onboard_device(u8 type, const char *name,
1084 struct i2c_adapter *adap)
1085 {
1086 int i;
1087 struct i2c_board_info info;
1088
1089 for (i = 0; i < ARRAY_SIZE(dmi_devices); i++) {
1090 /* & ~0x80, ignore enabled/disabled bit */
1091 if ((type & ~0x80) != dmi_devices[i].type)
1092 continue;
1093 if (strcasecmp(name, dmi_devices[i].name))
1094 continue;
1095
1096 memset(&info, 0, sizeof(struct i2c_board_info));
1097 info.addr = dmi_devices[i].i2c_addr;
1098 strlcpy(info.type, dmi_devices[i].i2c_type, I2C_NAME_SIZE);
1099 i2c_new_device(adap, &info);
1100 break;
1101 }
1102 }
1103
1104 /* We use our own function to check for onboard devices instead of
1105 dmi_find_device() as some buggy BIOS's have the devices we are interested
1106 in marked as disabled */
1107 static void dmi_check_onboard_devices(const struct dmi_header *dm, void *adap)
1108 {
1109 int i, count;
1110
1111 if (dm->type != 10)
1112 return;
1113
1114 count = (dm->length - sizeof(struct dmi_header)) / 2;
1115 for (i = 0; i < count; i++) {
1116 const u8 *d = (char *)(dm + 1) + (i * 2);
1117 const char *name = ((char *) dm) + dm->length;
1118 u8 type = d[0];
1119 u8 s = d[1];
1120
1121 if (!s)
1122 continue;
1123 s--;
1124 while (s > 0 && name[0]) {
1125 name += strlen(name) + 1;
1126 s--;
1127 }
1128 if (name[0] == 0) /* Bogus string reference */
1129 continue;
1130
1131 dmi_check_onboard_device(type, name, adap);
1132 }
1133 }
1134
1135 /* Register optional slaves */
1136 static void i801_probe_optional_slaves(struct i801_priv *priv)
1137 {
1138 /* Only register slaves on main SMBus channel */
1139 if (priv->features & FEATURE_IDF)
1140 return;
1141
1142 if (apanel_addr) {
1143 struct i2c_board_info info;
1144
1145 memset(&info, 0, sizeof(struct i2c_board_info));
1146 info.addr = apanel_addr;
1147 strlcpy(info.type, "fujitsu_apanel", I2C_NAME_SIZE);
1148 i2c_new_device(&priv->adapter, &info);
1149 }
1150
1151 if (dmi_name_in_vendors("FUJITSU"))
1152 dmi_walk(dmi_check_onboard_devices, &priv->adapter);
1153 }
1154 #else
1155 static void __init input_apanel_init(void) {}
1156 static void i801_probe_optional_slaves(struct i801_priv *priv) {}
1157 #endif /* CONFIG_X86 && CONFIG_DMI */
1158
1159 #if IS_ENABLED(CONFIG_I2C_MUX_GPIO) && defined CONFIG_DMI
1160 static struct i801_mux_config i801_mux_config_asus_z8_d12 = {
1161 .gpio_chip = "gpio_ich",
1162 .values = { 0x02, 0x03 },
1163 .n_values = 2,
1164 .classes = { I2C_CLASS_SPD, I2C_CLASS_SPD },
1165 .gpios = { 52, 53 },
1166 .n_gpios = 2,
1167 };
1168
1169 static struct i801_mux_config i801_mux_config_asus_z8_d18 = {
1170 .gpio_chip = "gpio_ich",
1171 .values = { 0x02, 0x03, 0x01 },
1172 .n_values = 3,
1173 .classes = { I2C_CLASS_SPD, I2C_CLASS_SPD, I2C_CLASS_SPD },
1174 .gpios = { 52, 53 },
1175 .n_gpios = 2,
1176 };
1177
1178 static const struct dmi_system_id mux_dmi_table[] = {
1179 {
1180 .matches = {
1181 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1182 DMI_MATCH(DMI_BOARD_NAME, "Z8NA-D6(C)"),
1183 },
1184 .driver_data = &i801_mux_config_asus_z8_d12,
1185 },
1186 {
1187 .matches = {
1188 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1189 DMI_MATCH(DMI_BOARD_NAME, "Z8P(N)E-D12(X)"),
1190 },
1191 .driver_data = &i801_mux_config_asus_z8_d12,
1192 },
1193 {
1194 .matches = {
1195 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1196 DMI_MATCH(DMI_BOARD_NAME, "Z8NH-D12"),
1197 },
1198 .driver_data = &i801_mux_config_asus_z8_d12,
1199 },
1200 {
1201 .matches = {
1202 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1203 DMI_MATCH(DMI_BOARD_NAME, "Z8PH-D12/IFB"),
1204 },
1205 .driver_data = &i801_mux_config_asus_z8_d12,
1206 },
1207 {
1208 .matches = {
1209 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1210 DMI_MATCH(DMI_BOARD_NAME, "Z8NR-D12"),
1211 },
1212 .driver_data = &i801_mux_config_asus_z8_d12,
1213 },
1214 {
1215 .matches = {
1216 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1217 DMI_MATCH(DMI_BOARD_NAME, "Z8P(N)H-D12"),
1218 },
1219 .driver_data = &i801_mux_config_asus_z8_d12,
1220 },
1221 {
1222 .matches = {
1223 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1224 DMI_MATCH(DMI_BOARD_NAME, "Z8PG-D18"),
1225 },
1226 .driver_data = &i801_mux_config_asus_z8_d18,
1227 },
1228 {
1229 .matches = {
1230 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1231 DMI_MATCH(DMI_BOARD_NAME, "Z8PE-D18"),
1232 },
1233 .driver_data = &i801_mux_config_asus_z8_d18,
1234 },
1235 {
1236 .matches = {
1237 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1238 DMI_MATCH(DMI_BOARD_NAME, "Z8PS-D12"),
1239 },
1240 .driver_data = &i801_mux_config_asus_z8_d12,
1241 },
1242 { }
1243 };
1244
1245 /* Setup multiplexing if needed */
1246 static int i801_add_mux(struct i801_priv *priv)
1247 {
1248 struct device *dev = &priv->adapter.dev;
1249 const struct i801_mux_config *mux_config;
1250 struct i2c_mux_gpio_platform_data gpio_data;
1251 int err;
1252
1253 if (!priv->mux_drvdata)
1254 return 0;
1255 mux_config = priv->mux_drvdata;
1256
1257 /* Prepare the platform data */
1258 memset(&gpio_data, 0, sizeof(struct i2c_mux_gpio_platform_data));
1259 gpio_data.parent = priv->adapter.nr;
1260 gpio_data.values = mux_config->values;
1261 gpio_data.n_values = mux_config->n_values;
1262 gpio_data.classes = mux_config->classes;
1263 gpio_data.gpio_chip = mux_config->gpio_chip;
1264 gpio_data.gpios = mux_config->gpios;
1265 gpio_data.n_gpios = mux_config->n_gpios;
1266 gpio_data.idle = I2C_MUX_GPIO_NO_IDLE;
1267
1268 /* Register the mux device */
1269 priv->mux_pdev = platform_device_register_data(dev, "i2c-mux-gpio",
1270 PLATFORM_DEVID_AUTO, &gpio_data,
1271 sizeof(struct i2c_mux_gpio_platform_data));
1272 if (IS_ERR(priv->mux_pdev)) {
1273 err = PTR_ERR(priv->mux_pdev);
1274 priv->mux_pdev = NULL;
1275 dev_err(dev, "Failed to register i2c-mux-gpio device\n");
1276 return err;
1277 }
1278
1279 return 0;
1280 }
1281
1282 static void i801_del_mux(struct i801_priv *priv)
1283 {
1284 if (priv->mux_pdev)
1285 platform_device_unregister(priv->mux_pdev);
1286 }
1287
1288 static unsigned int i801_get_adapter_class(struct i801_priv *priv)
1289 {
1290 const struct dmi_system_id *id;
1291 const struct i801_mux_config *mux_config;
1292 unsigned int class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
1293 int i;
1294
1295 id = dmi_first_match(mux_dmi_table);
1296 if (id) {
1297 /* Remove branch classes from trunk */
1298 mux_config = id->driver_data;
1299 for (i = 0; i < mux_config->n_values; i++)
1300 class &= ~mux_config->classes[i];
1301
1302 /* Remember for later */
1303 priv->mux_drvdata = mux_config;
1304 }
1305
1306 return class;
1307 }
1308 #else
1309 static inline int i801_add_mux(struct i801_priv *priv) { return 0; }
1310 static inline void i801_del_mux(struct i801_priv *priv) { }
1311
1312 static inline unsigned int i801_get_adapter_class(struct i801_priv *priv)
1313 {
1314 return I2C_CLASS_HWMON | I2C_CLASS_SPD;
1315 }
1316 #endif
1317
1318 static const struct itco_wdt_platform_data tco_platform_data = {
1319 .name = "Intel PCH",
1320 .version = 4,
1321 };
1322
1323 static DEFINE_SPINLOCK(p2sb_spinlock);
1324
1325 static void i801_add_tco(struct i801_priv *priv)
1326 {
1327 struct pci_dev *pci_dev = priv->pci_dev;
1328 struct resource tco_res[3], *res;
1329 struct platform_device *pdev;
1330 unsigned int devfn;
1331 u32 tco_base, tco_ctl;
1332 u32 base_addr, ctrl_val;
1333 u64 base64_addr;
1334
1335 if (!(priv->features & FEATURE_TCO))
1336 return;
1337
1338 pci_read_config_dword(pci_dev, TCOBASE, &tco_base);
1339 pci_read_config_dword(pci_dev, TCOCTL, &tco_ctl);
1340 if (!(tco_ctl & TCOCTL_EN))
1341 return;
1342
1343 memset(tco_res, 0, sizeof(tco_res));
1344
1345 res = &tco_res[ICH_RES_IO_TCO];
1346 res->start = tco_base & ~1;
1347 res->end = res->start + 32 - 1;
1348 res->flags = IORESOURCE_IO;
1349
1350 /*
1351 * Power Management registers.
1352 */
1353 devfn = PCI_DEVFN(PCI_SLOT(pci_dev->devfn), 2);
1354 pci_bus_read_config_dword(pci_dev->bus, devfn, ACPIBASE, &base_addr);
1355
1356 res = &tco_res[ICH_RES_IO_SMI];
1357 res->start = (base_addr & ~1) + ACPIBASE_SMI_OFF;
1358 res->end = res->start + 3;
1359 res->flags = IORESOURCE_IO;
1360
1361 /*
1362 * Enable the ACPI I/O space.
1363 */
1364 pci_bus_read_config_dword(pci_dev->bus, devfn, ACPICTRL, &ctrl_val);
1365 ctrl_val |= ACPICTRL_EN;
1366 pci_bus_write_config_dword(pci_dev->bus, devfn, ACPICTRL, ctrl_val);
1367
1368 /*
1369 * We must access the NO_REBOOT bit over the Primary to Sideband
1370 * bridge (P2SB). The BIOS prevents the P2SB device from being
1371 * enumerated by the PCI subsystem, so we need to unhide/hide it
1372 * to lookup the P2SB BAR.
1373 */
1374 spin_lock(&p2sb_spinlock);
1375
1376 devfn = PCI_DEVFN(PCI_SLOT(pci_dev->devfn), 1);
1377
1378 /* Unhide the P2SB device */
1379 pci_bus_write_config_byte(pci_dev->bus, devfn, 0xe1, 0x0);
1380
1381 pci_bus_read_config_dword(pci_dev->bus, devfn, SBREG_BAR, &base_addr);
1382 base64_addr = base_addr & 0xfffffff0;
1383
1384 pci_bus_read_config_dword(pci_dev->bus, devfn, SBREG_BAR + 0x4, &base_addr);
1385 base64_addr |= (u64)base_addr << 32;
1386
1387 /* Hide the P2SB device */
1388 pci_bus_write_config_byte(pci_dev->bus, devfn, 0xe1, 0x1);
1389 spin_unlock(&p2sb_spinlock);
1390
1391 res = &tco_res[ICH_RES_MEM_OFF];
1392 res->start = (resource_size_t)base64_addr + SBREG_SMBCTRL;
1393 res->end = res->start + 3;
1394 res->flags = IORESOURCE_MEM;
1395
1396 pdev = platform_device_register_resndata(&pci_dev->dev, "iTCO_wdt", -1,
1397 tco_res, 3, &tco_platform_data,
1398 sizeof(tco_platform_data));
1399 if (IS_ERR(pdev)) {
1400 dev_warn(&pci_dev->dev, "failed to create iTCO device\n");
1401 return;
1402 }
1403
1404 priv->tco_pdev = pdev;
1405 }
1406
1407 #ifdef CONFIG_ACPI
1408 static acpi_status
1409 i801_acpi_io_handler(u32 function, acpi_physical_address address, u32 bits,
1410 u64 *value, void *handler_context, void *region_context)
1411 {
1412 struct i801_priv *priv = handler_context;
1413 struct pci_dev *pdev = priv->pci_dev;
1414 acpi_status status;
1415
1416 /*
1417 * Once BIOS AML code touches the OpRegion we warn and inhibit any
1418 * further access from the driver itself. This device is now owned
1419 * by the system firmware.
1420 */
1421 mutex_lock(&priv->acpi_lock);
1422
1423 if (!priv->acpi_reserved) {
1424 priv->acpi_reserved = true;
1425
1426 dev_warn(&pdev->dev, "BIOS is accessing SMBus registers\n");
1427 dev_warn(&pdev->dev, "Driver SMBus register access inhibited\n");
1428
1429 /*
1430 * BIOS is accessing the host controller so prevent it from
1431 * suspending automatically from now on.
1432 */
1433 pm_runtime_get_sync(&pdev->dev);
1434 }
1435
1436 if ((function & ACPI_IO_MASK) == ACPI_READ)
1437 status = acpi_os_read_port(address, (u32 *)value, bits);
1438 else
1439 status = acpi_os_write_port(address, (u32)*value, bits);
1440
1441 mutex_unlock(&priv->acpi_lock);
1442
1443 return status;
1444 }
1445
1446 static int i801_acpi_probe(struct i801_priv *priv)
1447 {
1448 struct acpi_device *adev;
1449 acpi_status status;
1450
1451 adev = ACPI_COMPANION(&priv->pci_dev->dev);
1452 if (adev) {
1453 status = acpi_install_address_space_handler(adev->handle,
1454 ACPI_ADR_SPACE_SYSTEM_IO, i801_acpi_io_handler,
1455 NULL, priv);
1456 if (ACPI_SUCCESS(status))
1457 return 0;
1458 }
1459
1460 return acpi_check_resource_conflict(&priv->pci_dev->resource[SMBBAR]);
1461 }
1462
1463 static void i801_acpi_remove(struct i801_priv *priv)
1464 {
1465 struct acpi_device *adev;
1466
1467 adev = ACPI_COMPANION(&priv->pci_dev->dev);
1468 if (!adev)
1469 return;
1470
1471 acpi_remove_address_space_handler(adev->handle,
1472 ACPI_ADR_SPACE_SYSTEM_IO, i801_acpi_io_handler);
1473
1474 mutex_lock(&priv->acpi_lock);
1475 if (priv->acpi_reserved)
1476 pm_runtime_put(&priv->pci_dev->dev);
1477 mutex_unlock(&priv->acpi_lock);
1478 }
1479 #else
1480 static inline int i801_acpi_probe(struct i801_priv *priv) { return 0; }
1481 static inline void i801_acpi_remove(struct i801_priv *priv) { }
1482 #endif
1483
1484 static int i801_probe(struct pci_dev *dev, const struct pci_device_id *id)
1485 {
1486 unsigned char temp;
1487 int err, i;
1488 struct i801_priv *priv;
1489
1490 priv = devm_kzalloc(&dev->dev, sizeof(*priv), GFP_KERNEL);
1491 if (!priv)
1492 return -ENOMEM;
1493
1494 i2c_set_adapdata(&priv->adapter, priv);
1495 priv->adapter.owner = THIS_MODULE;
1496 priv->adapter.class = i801_get_adapter_class(priv);
1497 priv->adapter.algo = &smbus_algorithm;
1498 priv->adapter.dev.parent = &dev->dev;
1499 ACPI_COMPANION_SET(&priv->adapter.dev, ACPI_COMPANION(&dev->dev));
1500 priv->adapter.retries = 3;
1501 mutex_init(&priv->acpi_lock);
1502
1503 priv->pci_dev = dev;
1504 switch (dev->device) {
1505 case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS:
1506 case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS:
1507 case PCI_DEVICE_ID_INTEL_LEWISBURG_SMBUS:
1508 case PCI_DEVICE_ID_INTEL_LEWISBURG_SSKU_SMBUS:
1509 case PCI_DEVICE_ID_INTEL_DNV_SMBUS:
1510 case PCI_DEVICE_ID_INTEL_KABYLAKE_PCH_H_SMBUS:
1511 priv->features |= FEATURE_I2C_BLOCK_READ;
1512 priv->features |= FEATURE_IRQ;
1513 priv->features |= FEATURE_SMBUS_PEC;
1514 priv->features |= FEATURE_BLOCK_BUFFER;
1515 /* If we have ACPI based watchdog use that instead */
1516 if (!acpi_has_watchdog())
1517 priv->features |= FEATURE_TCO;
1518 priv->features |= FEATURE_HOST_NOTIFY;
1519 break;
1520
1521 case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0:
1522 case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1:
1523 case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2:
1524 case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0:
1525 case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1:
1526 case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2:
1527 priv->features |= FEATURE_IDF;
1528 /* fall through */
1529 default:
1530 priv->features |= FEATURE_I2C_BLOCK_READ;
1531 priv->features |= FEATURE_IRQ;
1532 /* fall through */
1533 case PCI_DEVICE_ID_INTEL_82801DB_3:
1534 priv->features |= FEATURE_SMBUS_PEC;
1535 priv->features |= FEATURE_BLOCK_BUFFER;
1536 /* fall through */
1537 case PCI_DEVICE_ID_INTEL_82801CA_3:
1538 priv->features |= FEATURE_HOST_NOTIFY;
1539 /* fall through */
1540 case PCI_DEVICE_ID_INTEL_82801BA_2:
1541 case PCI_DEVICE_ID_INTEL_82801AB_3:
1542 case PCI_DEVICE_ID_INTEL_82801AA_3:
1543 break;
1544 }
1545
1546 /* Disable features on user request */
1547 for (i = 0; i < ARRAY_SIZE(i801_feature_names); i++) {
1548 if (priv->features & disable_features & (1 << i))
1549 dev_notice(&dev->dev, "%s disabled by user\n",
1550 i801_feature_names[i]);
1551 }
1552 priv->features &= ~disable_features;
1553
1554 err = pcim_enable_device(dev);
1555 if (err) {
1556 dev_err(&dev->dev, "Failed to enable SMBus PCI device (%d)\n",
1557 err);
1558 return err;
1559 }
1560 pcim_pin_device(dev);
1561
1562 /* Determine the address of the SMBus area */
1563 priv->smba = pci_resource_start(dev, SMBBAR);
1564 if (!priv->smba) {
1565 dev_err(&dev->dev,
1566 "SMBus base address uninitialized, upgrade BIOS\n");
1567 return -ENODEV;
1568 }
1569
1570 if (i801_acpi_probe(priv))
1571 return -ENODEV;
1572
1573 err = pcim_iomap_regions(dev, 1 << SMBBAR,
1574 dev_driver_string(&dev->dev));
1575 if (err) {
1576 dev_err(&dev->dev,
1577 "Failed to request SMBus region 0x%lx-0x%Lx\n",
1578 priv->smba,
1579 (unsigned long long)pci_resource_end(dev, SMBBAR));
1580 i801_acpi_remove(priv);
1581 return err;
1582 }
1583
1584 pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &temp);
1585 priv->original_hstcfg = temp;
1586 temp &= ~SMBHSTCFG_I2C_EN; /* SMBus timing */
1587 if (!(temp & SMBHSTCFG_HST_EN)) {
1588 dev_info(&dev->dev, "Enabling SMBus device\n");
1589 temp |= SMBHSTCFG_HST_EN;
1590 }
1591 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, temp);
1592
1593 if (temp & SMBHSTCFG_SMB_SMI_EN) {
1594 dev_dbg(&dev->dev, "SMBus using interrupt SMI#\n");
1595 /* Disable SMBus interrupt feature if SMBus using SMI# */
1596 priv->features &= ~FEATURE_IRQ;
1597 }
1598 if (temp & SMBHSTCFG_SPD_WD)
1599 dev_info(&dev->dev, "SPD Write Disable is set\n");
1600
1601 /* Clear special mode bits */
1602 if (priv->features & (FEATURE_SMBUS_PEC | FEATURE_BLOCK_BUFFER))
1603 outb_p(inb_p(SMBAUXCTL(priv)) &
1604 ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv));
1605
1606 /* Default timeout in interrupt mode: 200 ms */
1607 priv->adapter.timeout = HZ / 5;
1608
1609 if (priv->features & FEATURE_IRQ) {
1610 u16 pcictl, pcists;
1611
1612 /* Complain if an interrupt is already pending */
1613 pci_read_config_word(priv->pci_dev, SMBPCISTS, &pcists);
1614 if (pcists & SMBPCISTS_INTS)
1615 dev_warn(&dev->dev, "An interrupt is pending!\n");
1616
1617 /* Check if interrupts have been disabled */
1618 pci_read_config_word(priv->pci_dev, SMBPCICTL, &pcictl);
1619 if (pcictl & SMBPCICTL_INTDIS) {
1620 dev_info(&dev->dev, "Interrupts are disabled\n");
1621 priv->features &= ~FEATURE_IRQ;
1622 }
1623 }
1624
1625 if (priv->features & FEATURE_IRQ) {
1626 init_waitqueue_head(&priv->waitq);
1627
1628 err = devm_request_irq(&dev->dev, dev->irq, i801_isr,
1629 IRQF_SHARED,
1630 dev_driver_string(&dev->dev), priv);
1631 if (err) {
1632 dev_err(&dev->dev, "Failed to allocate irq %d: %d\n",
1633 dev->irq, err);
1634 priv->features &= ~FEATURE_IRQ;
1635 }
1636 }
1637 dev_info(&dev->dev, "SMBus using %s\n",
1638 priv->features & FEATURE_IRQ ? "PCI interrupt" : "polling");
1639
1640 i801_add_tco(priv);
1641
1642 snprintf(priv->adapter.name, sizeof(priv->adapter.name),
1643 "SMBus I801 adapter at %04lx", priv->smba);
1644 err = i2c_add_adapter(&priv->adapter);
1645 if (err) {
1646 i801_acpi_remove(priv);
1647 return err;
1648 }
1649
1650 /*
1651 * Enable Host Notify for chips that supports it.
1652 * It is done after i2c_add_adapter() so that we are sure the work queue
1653 * is not used if i2c_add_adapter() fails.
1654 */
1655 err = i801_enable_host_notify(&priv->adapter);
1656 if (err && err != -ENOTSUPP)
1657 dev_warn(&dev->dev, "Unable to enable SMBus Host Notify\n");
1658
1659 i801_probe_optional_slaves(priv);
1660 /* We ignore errors - multiplexing is optional */
1661 i801_add_mux(priv);
1662
1663 pci_set_drvdata(dev, priv);
1664
1665 pm_runtime_set_autosuspend_delay(&dev->dev, 1000);
1666 pm_runtime_use_autosuspend(&dev->dev);
1667 pm_runtime_put_autosuspend(&dev->dev);
1668 pm_runtime_allow(&dev->dev);
1669
1670 return 0;
1671 }
1672
1673 static void i801_remove(struct pci_dev *dev)
1674 {
1675 struct i801_priv *priv = pci_get_drvdata(dev);
1676
1677 pm_runtime_forbid(&dev->dev);
1678 pm_runtime_get_noresume(&dev->dev);
1679
1680 i801_disable_host_notify(priv);
1681 i801_del_mux(priv);
1682 i2c_del_adapter(&priv->adapter);
1683 i801_acpi_remove(priv);
1684 pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg);
1685
1686 platform_device_unregister(priv->tco_pdev);
1687
1688 /*
1689 * do not call pci_disable_device(dev) since it can cause hard hangs on
1690 * some systems during power-off (eg. Fujitsu-Siemens Lifebook E8010)
1691 */
1692 }
1693
1694 #ifdef CONFIG_PM
1695 static int i801_suspend(struct device *dev)
1696 {
1697 struct pci_dev *pci_dev = to_pci_dev(dev);
1698 struct i801_priv *priv = pci_get_drvdata(pci_dev);
1699
1700 pci_write_config_byte(pci_dev, SMBHSTCFG, priv->original_hstcfg);
1701 return 0;
1702 }
1703
1704 static int i801_resume(struct device *dev)
1705 {
1706 struct pci_dev *pci_dev = to_pci_dev(dev);
1707 struct i801_priv *priv = pci_get_drvdata(pci_dev);
1708 int err;
1709
1710 err = i801_enable_host_notify(&priv->adapter);
1711 if (err && err != -ENOTSUPP)
1712 dev_warn(dev, "Unable to enable SMBus Host Notify\n");
1713
1714 return 0;
1715 }
1716 #endif
1717
1718 static UNIVERSAL_DEV_PM_OPS(i801_pm_ops, i801_suspend,
1719 i801_resume, NULL);
1720
1721 static struct pci_driver i801_driver = {
1722 .name = "i801_smbus",
1723 .id_table = i801_ids,
1724 .probe = i801_probe,
1725 .remove = i801_remove,
1726 .driver = {
1727 .pm = &i801_pm_ops,
1728 },
1729 };
1730
1731 static int __init i2c_i801_init(void)
1732 {
1733 if (dmi_name_in_vendors("FUJITSU"))
1734 input_apanel_init();
1735 return pci_register_driver(&i801_driver);
1736 }
1737
1738 static void __exit i2c_i801_exit(void)
1739 {
1740 pci_unregister_driver(&i801_driver);
1741 }
1742
1743 MODULE_AUTHOR("Mark D. Studebaker <mdsxyz123@yahoo.com>, Jean Delvare <jdelvare@suse.de>");
1744 MODULE_DESCRIPTION("I801 SMBus driver");
1745 MODULE_LICENSE("GPL");
1746
1747 module_init(i2c_i801_init);
1748 module_exit(i2c_i801_exit);
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