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Merge branch 'timers-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel...
[mirror_ubuntu-bionic-kernel.git] / drivers / i2c / busses / i2c-i801.c
1 /*
2 Copyright (c) 1998 - 2002 Frodo Looijaard <frodol@dds.nl>,
3 Philip Edelbrock <phil@netroedge.com>, and Mark D. Studebaker
4 <mdsxyz123@yahoo.com>
5 Copyright (C) 2007 - 2014 Jean Delvare <jdelvare@suse.de>
6 Copyright (C) 2010 Intel Corporation,
7 David Woodhouse <dwmw2@infradead.org>
8
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2 of the License, or
12 (at your option) any later version.
13
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
18 */
19
20 /*
21 * Supports the following Intel I/O Controller Hubs (ICH):
22 *
23 * I/O Block I2C
24 * region SMBus Block proc. block
25 * Chip name PCI ID size PEC buffer call read
26 * ---------------------------------------------------------------------------
27 * 82801AA (ICH) 0x2413 16 no no no no
28 * 82801AB (ICH0) 0x2423 16 no no no no
29 * 82801BA (ICH2) 0x2443 16 no no no no
30 * 82801CA (ICH3) 0x2483 32 soft no no no
31 * 82801DB (ICH4) 0x24c3 32 hard yes no no
32 * 82801E (ICH5) 0x24d3 32 hard yes yes yes
33 * 6300ESB 0x25a4 32 hard yes yes yes
34 * 82801F (ICH6) 0x266a 32 hard yes yes yes
35 * 6310ESB/6320ESB 0x269b 32 hard yes yes yes
36 * 82801G (ICH7) 0x27da 32 hard yes yes yes
37 * 82801H (ICH8) 0x283e 32 hard yes yes yes
38 * 82801I (ICH9) 0x2930 32 hard yes yes yes
39 * EP80579 (Tolapai) 0x5032 32 hard yes yes yes
40 * ICH10 0x3a30 32 hard yes yes yes
41 * ICH10 0x3a60 32 hard yes yes yes
42 * 5/3400 Series (PCH) 0x3b30 32 hard yes yes yes
43 * 6 Series (PCH) 0x1c22 32 hard yes yes yes
44 * Patsburg (PCH) 0x1d22 32 hard yes yes yes
45 * Patsburg (PCH) IDF 0x1d70 32 hard yes yes yes
46 * Patsburg (PCH) IDF 0x1d71 32 hard yes yes yes
47 * Patsburg (PCH) IDF 0x1d72 32 hard yes yes yes
48 * DH89xxCC (PCH) 0x2330 32 hard yes yes yes
49 * Panther Point (PCH) 0x1e22 32 hard yes yes yes
50 * Lynx Point (PCH) 0x8c22 32 hard yes yes yes
51 * Lynx Point-LP (PCH) 0x9c22 32 hard yes yes yes
52 * Avoton (SOC) 0x1f3c 32 hard yes yes yes
53 * Wellsburg (PCH) 0x8d22 32 hard yes yes yes
54 * Wellsburg (PCH) MS 0x8d7d 32 hard yes yes yes
55 * Wellsburg (PCH) MS 0x8d7e 32 hard yes yes yes
56 * Wellsburg (PCH) MS 0x8d7f 32 hard yes yes yes
57 * Coleto Creek (PCH) 0x23b0 32 hard yes yes yes
58 * Wildcat Point (PCH) 0x8ca2 32 hard yes yes yes
59 * Wildcat Point-LP (PCH) 0x9ca2 32 hard yes yes yes
60 * BayTrail (SOC) 0x0f12 32 hard yes yes yes
61 * Sunrise Point-H (PCH) 0xa123 32 hard yes yes yes
62 * Sunrise Point-LP (PCH) 0x9d23 32 hard yes yes yes
63 * DNV (SOC) 0x19df 32 hard yes yes yes
64 * Broxton (SOC) 0x5ad4 32 hard yes yes yes
65 * Lewisburg (PCH) 0xa1a3 32 hard yes yes yes
66 * Lewisburg Supersku (PCH) 0xa223 32 hard yes yes yes
67 * Kaby Lake PCH-H (PCH) 0xa2a3 32 hard yes yes yes
68 *
69 * Features supported by this driver:
70 * Software PEC no
71 * Hardware PEC yes
72 * Block buffer yes
73 * Block process call transaction no
74 * I2C block read transaction yes (doesn't use the block buffer)
75 * Slave mode no
76 * SMBus Host Notify yes
77 * Interrupt processing yes
78 *
79 * See the file Documentation/i2c/busses/i2c-i801 for details.
80 */
81
82 #include <linux/interrupt.h>
83 #include <linux/module.h>
84 #include <linux/pci.h>
85 #include <linux/kernel.h>
86 #include <linux/stddef.h>
87 #include <linux/delay.h>
88 #include <linux/ioport.h>
89 #include <linux/init.h>
90 #include <linux/i2c.h>
91 #include <linux/i2c-smbus.h>
92 #include <linux/acpi.h>
93 #include <linux/io.h>
94 #include <linux/dmi.h>
95 #include <linux/slab.h>
96 #include <linux/wait.h>
97 #include <linux/err.h>
98 #include <linux/platform_device.h>
99 #include <linux/platform_data/itco_wdt.h>
100 #include <linux/pm_runtime.h>
101
102 #if IS_ENABLED(CONFIG_I2C_MUX_GPIO) && defined CONFIG_DMI
103 #include <linux/gpio.h>
104 #include <linux/i2c-mux-gpio.h>
105 #endif
106
107 /* I801 SMBus address offsets */
108 #define SMBHSTSTS(p) (0 + (p)->smba)
109 #define SMBHSTCNT(p) (2 + (p)->smba)
110 #define SMBHSTCMD(p) (3 + (p)->smba)
111 #define SMBHSTADD(p) (4 + (p)->smba)
112 #define SMBHSTDAT0(p) (5 + (p)->smba)
113 #define SMBHSTDAT1(p) (6 + (p)->smba)
114 #define SMBBLKDAT(p) (7 + (p)->smba)
115 #define SMBPEC(p) (8 + (p)->smba) /* ICH3 and later */
116 #define SMBAUXSTS(p) (12 + (p)->smba) /* ICH4 and later */
117 #define SMBAUXCTL(p) (13 + (p)->smba) /* ICH4 and later */
118 #define SMBSLVSTS(p) (16 + (p)->smba) /* ICH3 and later */
119 #define SMBSLVCMD(p) (17 + (p)->smba) /* ICH3 and later */
120 #define SMBNTFDADD(p) (20 + (p)->smba) /* ICH3 and later */
121 #define SMBNTFDDAT(p) (22 + (p)->smba) /* ICH3 and later */
122
123 /* PCI Address Constants */
124 #define SMBBAR 4
125 #define SMBPCICTL 0x004
126 #define SMBPCISTS 0x006
127 #define SMBHSTCFG 0x040
128 #define TCOBASE 0x050
129 #define TCOCTL 0x054
130
131 #define ACPIBASE 0x040
132 #define ACPIBASE_SMI_OFF 0x030
133 #define ACPICTRL 0x044
134 #define ACPICTRL_EN 0x080
135
136 #define SBREG_BAR 0x10
137 #define SBREG_SMBCTRL 0xc6000c
138
139 /* Host status bits for SMBPCISTS */
140 #define SMBPCISTS_INTS 0x08
141
142 /* Control bits for SMBPCICTL */
143 #define SMBPCICTL_INTDIS 0x0400
144
145 /* Host configuration bits for SMBHSTCFG */
146 #define SMBHSTCFG_HST_EN 1
147 #define SMBHSTCFG_SMB_SMI_EN 2
148 #define SMBHSTCFG_I2C_EN 4
149 #define SMBHSTCFG_SPD_WD 0x10
150
151 /* TCO configuration bits for TCOCTL */
152 #define TCOCTL_EN 0x0100
153
154 /* Auxiliary status register bits, ICH4+ only */
155 #define SMBAUXSTS_CRCE 1
156 #define SMBAUXSTS_STCO 2
157
158 /* Auxiliary control register bits, ICH4+ only */
159 #define SMBAUXCTL_CRC 1
160 #define SMBAUXCTL_E32B 2
161
162 /* Other settings */
163 #define MAX_RETRIES 400
164
165 /* I801 command constants */
166 #define I801_QUICK 0x00
167 #define I801_BYTE 0x04
168 #define I801_BYTE_DATA 0x08
169 #define I801_WORD_DATA 0x0C
170 #define I801_PROC_CALL 0x10 /* unimplemented */
171 #define I801_BLOCK_DATA 0x14
172 #define I801_I2C_BLOCK_DATA 0x18 /* ICH5 and later */
173
174 /* I801 Host Control register bits */
175 #define SMBHSTCNT_INTREN 0x01
176 #define SMBHSTCNT_KILL 0x02
177 #define SMBHSTCNT_LAST_BYTE 0x20
178 #define SMBHSTCNT_START 0x40
179 #define SMBHSTCNT_PEC_EN 0x80 /* ICH3 and later */
180
181 /* I801 Hosts Status register bits */
182 #define SMBHSTSTS_BYTE_DONE 0x80
183 #define SMBHSTSTS_INUSE_STS 0x40
184 #define SMBHSTSTS_SMBALERT_STS 0x20
185 #define SMBHSTSTS_FAILED 0x10
186 #define SMBHSTSTS_BUS_ERR 0x08
187 #define SMBHSTSTS_DEV_ERR 0x04
188 #define SMBHSTSTS_INTR 0x02
189 #define SMBHSTSTS_HOST_BUSY 0x01
190
191 /* Host Notify Status registers bits */
192 #define SMBSLVSTS_HST_NTFY_STS 1
193
194 /* Host Notify Command registers bits */
195 #define SMBSLVCMD_HST_NTFY_INTREN 0x01
196
197 #define STATUS_ERROR_FLAGS (SMBHSTSTS_FAILED | SMBHSTSTS_BUS_ERR | \
198 SMBHSTSTS_DEV_ERR)
199
200 #define STATUS_FLAGS (SMBHSTSTS_BYTE_DONE | SMBHSTSTS_INTR | \
201 STATUS_ERROR_FLAGS)
202
203 /* Older devices have their ID defined in <linux/pci_ids.h> */
204 #define PCI_DEVICE_ID_INTEL_BAYTRAIL_SMBUS 0x0f12
205 #define PCI_DEVICE_ID_INTEL_DNV_SMBUS 0x19df
206 #define PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS 0x1c22
207 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS 0x1d22
208 /* Patsburg also has three 'Integrated Device Function' SMBus controllers */
209 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0 0x1d70
210 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1 0x1d71
211 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2 0x1d72
212 #define PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS 0x1e22
213 #define PCI_DEVICE_ID_INTEL_AVOTON_SMBUS 0x1f3c
214 #define PCI_DEVICE_ID_INTEL_BRASWELL_SMBUS 0x2292
215 #define PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS 0x2330
216 #define PCI_DEVICE_ID_INTEL_COLETOCREEK_SMBUS 0x23b0
217 #define PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS 0x3b30
218 #define PCI_DEVICE_ID_INTEL_BROXTON_SMBUS 0x5ad4
219 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS 0x8c22
220 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_SMBUS 0x8ca2
221 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS 0x8d22
222 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0 0x8d7d
223 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1 0x8d7e
224 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2 0x8d7f
225 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS 0x9c22
226 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_SMBUS 0x9ca2
227 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS 0x9d23
228 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS 0xa123
229 #define PCI_DEVICE_ID_INTEL_LEWISBURG_SMBUS 0xa1a3
230 #define PCI_DEVICE_ID_INTEL_LEWISBURG_SSKU_SMBUS 0xa223
231 #define PCI_DEVICE_ID_INTEL_KABYLAKE_PCH_H_SMBUS 0xa2a3
232
233 struct i801_mux_config {
234 char *gpio_chip;
235 unsigned values[3];
236 int n_values;
237 unsigned classes[3];
238 unsigned gpios[2]; /* Relative to gpio_chip->base */
239 int n_gpios;
240 };
241
242 struct i801_priv {
243 struct i2c_adapter adapter;
244 unsigned long smba;
245 unsigned char original_hstcfg;
246 struct pci_dev *pci_dev;
247 unsigned int features;
248
249 /* isr processing */
250 wait_queue_head_t waitq;
251 u8 status;
252
253 /* Command state used by isr for byte-by-byte block transactions */
254 u8 cmd;
255 bool is_read;
256 int count;
257 int len;
258 u8 *data;
259
260 #if IS_ENABLED(CONFIG_I2C_MUX_GPIO) && defined CONFIG_DMI
261 const struct i801_mux_config *mux_drvdata;
262 struct platform_device *mux_pdev;
263 #endif
264 struct platform_device *tco_pdev;
265
266 /*
267 * If set to true the host controller registers are reserved for
268 * ACPI AML use. Protected by acpi_lock.
269 */
270 bool acpi_reserved;
271 struct mutex acpi_lock;
272 struct smbus_host_notify *host_notify;
273 };
274
275 #define SMBHSTNTFY_SIZE 8
276
277 #define FEATURE_SMBUS_PEC (1 << 0)
278 #define FEATURE_BLOCK_BUFFER (1 << 1)
279 #define FEATURE_BLOCK_PROC (1 << 2)
280 #define FEATURE_I2C_BLOCK_READ (1 << 3)
281 #define FEATURE_IRQ (1 << 4)
282 #define FEATURE_HOST_NOTIFY (1 << 5)
283 /* Not really a feature, but it's convenient to handle it as such */
284 #define FEATURE_IDF (1 << 15)
285 #define FEATURE_TCO (1 << 16)
286
287 static const char *i801_feature_names[] = {
288 "SMBus PEC",
289 "Block buffer",
290 "Block process call",
291 "I2C block read",
292 "Interrupt",
293 "SMBus Host Notify",
294 };
295
296 static unsigned int disable_features;
297 module_param(disable_features, uint, S_IRUGO | S_IWUSR);
298 MODULE_PARM_DESC(disable_features, "Disable selected driver features:\n"
299 "\t\t 0x01 disable SMBus PEC\n"
300 "\t\t 0x02 disable the block buffer\n"
301 "\t\t 0x08 disable the I2C block read functionality\n"
302 "\t\t 0x10 don't use interrupts\n"
303 "\t\t 0x20 disable SMBus Host Notify ");
304
305 /* Make sure the SMBus host is ready to start transmitting.
306 Return 0 if it is, -EBUSY if it is not. */
307 static int i801_check_pre(struct i801_priv *priv)
308 {
309 int status;
310
311 status = inb_p(SMBHSTSTS(priv));
312 if (status & SMBHSTSTS_HOST_BUSY) {
313 dev_err(&priv->pci_dev->dev, "SMBus is busy, can't use it!\n");
314 return -EBUSY;
315 }
316
317 status &= STATUS_FLAGS;
318 if (status) {
319 dev_dbg(&priv->pci_dev->dev, "Clearing status flags (%02x)\n",
320 status);
321 outb_p(status, SMBHSTSTS(priv));
322 status = inb_p(SMBHSTSTS(priv)) & STATUS_FLAGS;
323 if (status) {
324 dev_err(&priv->pci_dev->dev,
325 "Failed clearing status flags (%02x)\n",
326 status);
327 return -EBUSY;
328 }
329 }
330
331 /*
332 * Clear CRC status if needed.
333 * During normal operation, i801_check_post() takes care
334 * of it after every operation. We do it here only in case
335 * the hardware was already in this state when the driver
336 * started.
337 */
338 if (priv->features & FEATURE_SMBUS_PEC) {
339 status = inb_p(SMBAUXSTS(priv)) & SMBAUXSTS_CRCE;
340 if (status) {
341 dev_dbg(&priv->pci_dev->dev,
342 "Clearing aux status flags (%02x)\n", status);
343 outb_p(status, SMBAUXSTS(priv));
344 status = inb_p(SMBAUXSTS(priv)) & SMBAUXSTS_CRCE;
345 if (status) {
346 dev_err(&priv->pci_dev->dev,
347 "Failed clearing aux status flags (%02x)\n",
348 status);
349 return -EBUSY;
350 }
351 }
352 }
353
354 return 0;
355 }
356
357 /*
358 * Convert the status register to an error code, and clear it.
359 * Note that status only contains the bits we want to clear, not the
360 * actual register value.
361 */
362 static int i801_check_post(struct i801_priv *priv, int status)
363 {
364 int result = 0;
365
366 /*
367 * If the SMBus is still busy, we give up
368 * Note: This timeout condition only happens when using polling
369 * transactions. For interrupt operation, NAK/timeout is indicated by
370 * DEV_ERR.
371 */
372 if (unlikely(status < 0)) {
373 dev_err(&priv->pci_dev->dev, "Transaction timeout\n");
374 /* try to stop the current command */
375 dev_dbg(&priv->pci_dev->dev, "Terminating the current operation\n");
376 outb_p(inb_p(SMBHSTCNT(priv)) | SMBHSTCNT_KILL,
377 SMBHSTCNT(priv));
378 usleep_range(1000, 2000);
379 outb_p(inb_p(SMBHSTCNT(priv)) & (~SMBHSTCNT_KILL),
380 SMBHSTCNT(priv));
381
382 /* Check if it worked */
383 status = inb_p(SMBHSTSTS(priv));
384 if ((status & SMBHSTSTS_HOST_BUSY) ||
385 !(status & SMBHSTSTS_FAILED))
386 dev_err(&priv->pci_dev->dev,
387 "Failed terminating the transaction\n");
388 outb_p(STATUS_FLAGS, SMBHSTSTS(priv));
389 return -ETIMEDOUT;
390 }
391
392 if (status & SMBHSTSTS_FAILED) {
393 result = -EIO;
394 dev_err(&priv->pci_dev->dev, "Transaction failed\n");
395 }
396 if (status & SMBHSTSTS_DEV_ERR) {
397 /*
398 * This may be a PEC error, check and clear it.
399 *
400 * AUXSTS is handled differently from HSTSTS.
401 * For HSTSTS, i801_isr() or i801_wait_intr()
402 * has already cleared the error bits in hardware,
403 * and we are passed a copy of the original value
404 * in "status".
405 * For AUXSTS, the hardware register is left
406 * for us to handle here.
407 * This is asymmetric, slightly iffy, but safe,
408 * since all this code is serialized and the CRCE
409 * bit is harmless as long as it's cleared before
410 * the next operation.
411 */
412 if ((priv->features & FEATURE_SMBUS_PEC) &&
413 (inb_p(SMBAUXSTS(priv)) & SMBAUXSTS_CRCE)) {
414 outb_p(SMBAUXSTS_CRCE, SMBAUXSTS(priv));
415 result = -EBADMSG;
416 dev_dbg(&priv->pci_dev->dev, "PEC error\n");
417 } else {
418 result = -ENXIO;
419 dev_dbg(&priv->pci_dev->dev, "No response\n");
420 }
421 }
422 if (status & SMBHSTSTS_BUS_ERR) {
423 result = -EAGAIN;
424 dev_dbg(&priv->pci_dev->dev, "Lost arbitration\n");
425 }
426
427 /* Clear status flags except BYTE_DONE, to be cleared by caller */
428 outb_p(status, SMBHSTSTS(priv));
429
430 return result;
431 }
432
433 /* Wait for BUSY being cleared and either INTR or an error flag being set */
434 static int i801_wait_intr(struct i801_priv *priv)
435 {
436 int timeout = 0;
437 int status;
438
439 /* We will always wait for a fraction of a second! */
440 do {
441 usleep_range(250, 500);
442 status = inb_p(SMBHSTSTS(priv));
443 } while (((status & SMBHSTSTS_HOST_BUSY) ||
444 !(status & (STATUS_ERROR_FLAGS | SMBHSTSTS_INTR))) &&
445 (timeout++ < MAX_RETRIES));
446
447 if (timeout > MAX_RETRIES) {
448 dev_dbg(&priv->pci_dev->dev, "INTR Timeout!\n");
449 return -ETIMEDOUT;
450 }
451 return status & (STATUS_ERROR_FLAGS | SMBHSTSTS_INTR);
452 }
453
454 /* Wait for either BYTE_DONE or an error flag being set */
455 static int i801_wait_byte_done(struct i801_priv *priv)
456 {
457 int timeout = 0;
458 int status;
459
460 /* We will always wait for a fraction of a second! */
461 do {
462 usleep_range(250, 500);
463 status = inb_p(SMBHSTSTS(priv));
464 } while (!(status & (STATUS_ERROR_FLAGS | SMBHSTSTS_BYTE_DONE)) &&
465 (timeout++ < MAX_RETRIES));
466
467 if (timeout > MAX_RETRIES) {
468 dev_dbg(&priv->pci_dev->dev, "BYTE_DONE Timeout!\n");
469 return -ETIMEDOUT;
470 }
471 return status & STATUS_ERROR_FLAGS;
472 }
473
474 static int i801_transaction(struct i801_priv *priv, int xact)
475 {
476 int status;
477 int result;
478 const struct i2c_adapter *adap = &priv->adapter;
479
480 result = i801_check_pre(priv);
481 if (result < 0)
482 return result;
483
484 if (priv->features & FEATURE_IRQ) {
485 outb_p(xact | SMBHSTCNT_INTREN | SMBHSTCNT_START,
486 SMBHSTCNT(priv));
487 result = wait_event_timeout(priv->waitq,
488 (status = priv->status),
489 adap->timeout);
490 if (!result) {
491 status = -ETIMEDOUT;
492 dev_warn(&priv->pci_dev->dev,
493 "Timeout waiting for interrupt!\n");
494 }
495 priv->status = 0;
496 return i801_check_post(priv, status);
497 }
498
499 /* the current contents of SMBHSTCNT can be overwritten, since PEC,
500 * SMBSCMD are passed in xact */
501 outb_p(xact | SMBHSTCNT_START, SMBHSTCNT(priv));
502
503 status = i801_wait_intr(priv);
504 return i801_check_post(priv, status);
505 }
506
507 static int i801_block_transaction_by_block(struct i801_priv *priv,
508 union i2c_smbus_data *data,
509 char read_write, int hwpec)
510 {
511 int i, len;
512 int status;
513
514 inb_p(SMBHSTCNT(priv)); /* reset the data buffer index */
515
516 /* Use 32-byte buffer to process this transaction */
517 if (read_write == I2C_SMBUS_WRITE) {
518 len = data->block[0];
519 outb_p(len, SMBHSTDAT0(priv));
520 for (i = 0; i < len; i++)
521 outb_p(data->block[i+1], SMBBLKDAT(priv));
522 }
523
524 status = i801_transaction(priv, I801_BLOCK_DATA |
525 (hwpec ? SMBHSTCNT_PEC_EN : 0));
526 if (status)
527 return status;
528
529 if (read_write == I2C_SMBUS_READ) {
530 len = inb_p(SMBHSTDAT0(priv));
531 if (len < 1 || len > I2C_SMBUS_BLOCK_MAX)
532 return -EPROTO;
533
534 data->block[0] = len;
535 for (i = 0; i < len; i++)
536 data->block[i + 1] = inb_p(SMBBLKDAT(priv));
537 }
538 return 0;
539 }
540
541 static void i801_isr_byte_done(struct i801_priv *priv)
542 {
543 if (priv->is_read) {
544 /* For SMBus block reads, length is received with first byte */
545 if (((priv->cmd & 0x1c) == I801_BLOCK_DATA) &&
546 (priv->count == 0)) {
547 priv->len = inb_p(SMBHSTDAT0(priv));
548 if (priv->len < 1 || priv->len > I2C_SMBUS_BLOCK_MAX) {
549 dev_err(&priv->pci_dev->dev,
550 "Illegal SMBus block read size %d\n",
551 priv->len);
552 /* FIXME: Recover */
553 priv->len = I2C_SMBUS_BLOCK_MAX;
554 } else {
555 dev_dbg(&priv->pci_dev->dev,
556 "SMBus block read size is %d\n",
557 priv->len);
558 }
559 priv->data[-1] = priv->len;
560 }
561
562 /* Read next byte */
563 if (priv->count < priv->len)
564 priv->data[priv->count++] = inb(SMBBLKDAT(priv));
565 else
566 dev_dbg(&priv->pci_dev->dev,
567 "Discarding extra byte on block read\n");
568
569 /* Set LAST_BYTE for last byte of read transaction */
570 if (priv->count == priv->len - 1)
571 outb_p(priv->cmd | SMBHSTCNT_LAST_BYTE,
572 SMBHSTCNT(priv));
573 } else if (priv->count < priv->len - 1) {
574 /* Write next byte, except for IRQ after last byte */
575 outb_p(priv->data[++priv->count], SMBBLKDAT(priv));
576 }
577
578 /* Clear BYTE_DONE to continue with next byte */
579 outb_p(SMBHSTSTS_BYTE_DONE, SMBHSTSTS(priv));
580 }
581
582 static irqreturn_t i801_host_notify_isr(struct i801_priv *priv)
583 {
584 unsigned short addr;
585 unsigned int data;
586
587 addr = inb_p(SMBNTFDADD(priv)) >> 1;
588 data = inw_p(SMBNTFDDAT(priv));
589
590 i2c_handle_smbus_host_notify(priv->host_notify, addr, data);
591
592 /* clear Host Notify bit and return */
593 outb_p(SMBSLVSTS_HST_NTFY_STS, SMBSLVSTS(priv));
594 return IRQ_HANDLED;
595 }
596
597 /*
598 * There are three kinds of interrupts:
599 *
600 * 1) i801 signals transaction completion with one of these interrupts:
601 * INTR - Success
602 * DEV_ERR - Invalid command, NAK or communication timeout
603 * BUS_ERR - SMI# transaction collision
604 * FAILED - transaction was canceled due to a KILL request
605 * When any of these occur, update ->status and wake up the waitq.
606 * ->status must be cleared before kicking off the next transaction.
607 *
608 * 2) For byte-by-byte (I2C read/write) transactions, one BYTE_DONE interrupt
609 * occurs for each byte of a byte-by-byte to prepare the next byte.
610 *
611 * 3) Host Notify interrupts
612 */
613 static irqreturn_t i801_isr(int irq, void *dev_id)
614 {
615 struct i801_priv *priv = dev_id;
616 u16 pcists;
617 u8 status;
618
619 /* Confirm this is our interrupt */
620 pci_read_config_word(priv->pci_dev, SMBPCISTS, &pcists);
621 if (!(pcists & SMBPCISTS_INTS))
622 return IRQ_NONE;
623
624 if (priv->features & FEATURE_HOST_NOTIFY) {
625 status = inb_p(SMBSLVSTS(priv));
626 if (status & SMBSLVSTS_HST_NTFY_STS)
627 return i801_host_notify_isr(priv);
628 }
629
630 status = inb_p(SMBHSTSTS(priv));
631 if (status & SMBHSTSTS_BYTE_DONE)
632 i801_isr_byte_done(priv);
633
634 /*
635 * Clear irq sources and report transaction result.
636 * ->status must be cleared before the next transaction is started.
637 */
638 status &= SMBHSTSTS_INTR | STATUS_ERROR_FLAGS;
639 if (status) {
640 outb_p(status, SMBHSTSTS(priv));
641 priv->status = status;
642 wake_up(&priv->waitq);
643 }
644
645 return IRQ_HANDLED;
646 }
647
648 /*
649 * For "byte-by-byte" block transactions:
650 * I2C write uses cmd=I801_BLOCK_DATA, I2C_EN=1
651 * I2C read uses cmd=I801_I2C_BLOCK_DATA
652 */
653 static int i801_block_transaction_byte_by_byte(struct i801_priv *priv,
654 union i2c_smbus_data *data,
655 char read_write, int command,
656 int hwpec)
657 {
658 int i, len;
659 int smbcmd;
660 int status;
661 int result;
662 const struct i2c_adapter *adap = &priv->adapter;
663
664 result = i801_check_pre(priv);
665 if (result < 0)
666 return result;
667
668 len = data->block[0];
669
670 if (read_write == I2C_SMBUS_WRITE) {
671 outb_p(len, SMBHSTDAT0(priv));
672 outb_p(data->block[1], SMBBLKDAT(priv));
673 }
674
675 if (command == I2C_SMBUS_I2C_BLOCK_DATA &&
676 read_write == I2C_SMBUS_READ)
677 smbcmd = I801_I2C_BLOCK_DATA;
678 else
679 smbcmd = I801_BLOCK_DATA;
680
681 if (priv->features & FEATURE_IRQ) {
682 priv->is_read = (read_write == I2C_SMBUS_READ);
683 if (len == 1 && priv->is_read)
684 smbcmd |= SMBHSTCNT_LAST_BYTE;
685 priv->cmd = smbcmd | SMBHSTCNT_INTREN;
686 priv->len = len;
687 priv->count = 0;
688 priv->data = &data->block[1];
689
690 outb_p(priv->cmd | SMBHSTCNT_START, SMBHSTCNT(priv));
691 result = wait_event_timeout(priv->waitq,
692 (status = priv->status),
693 adap->timeout);
694 if (!result) {
695 status = -ETIMEDOUT;
696 dev_warn(&priv->pci_dev->dev,
697 "Timeout waiting for interrupt!\n");
698 }
699 priv->status = 0;
700 return i801_check_post(priv, status);
701 }
702
703 for (i = 1; i <= len; i++) {
704 if (i == len && read_write == I2C_SMBUS_READ)
705 smbcmd |= SMBHSTCNT_LAST_BYTE;
706 outb_p(smbcmd, SMBHSTCNT(priv));
707
708 if (i == 1)
709 outb_p(inb(SMBHSTCNT(priv)) | SMBHSTCNT_START,
710 SMBHSTCNT(priv));
711
712 status = i801_wait_byte_done(priv);
713 if (status)
714 goto exit;
715
716 if (i == 1 && read_write == I2C_SMBUS_READ
717 && command != I2C_SMBUS_I2C_BLOCK_DATA) {
718 len = inb_p(SMBHSTDAT0(priv));
719 if (len < 1 || len > I2C_SMBUS_BLOCK_MAX) {
720 dev_err(&priv->pci_dev->dev,
721 "Illegal SMBus block read size %d\n",
722 len);
723 /* Recover */
724 while (inb_p(SMBHSTSTS(priv)) &
725 SMBHSTSTS_HOST_BUSY)
726 outb_p(SMBHSTSTS_BYTE_DONE,
727 SMBHSTSTS(priv));
728 outb_p(SMBHSTSTS_INTR, SMBHSTSTS(priv));
729 return -EPROTO;
730 }
731 data->block[0] = len;
732 }
733
734 /* Retrieve/store value in SMBBLKDAT */
735 if (read_write == I2C_SMBUS_READ)
736 data->block[i] = inb_p(SMBBLKDAT(priv));
737 if (read_write == I2C_SMBUS_WRITE && i+1 <= len)
738 outb_p(data->block[i+1], SMBBLKDAT(priv));
739
740 /* signals SMBBLKDAT ready */
741 outb_p(SMBHSTSTS_BYTE_DONE, SMBHSTSTS(priv));
742 }
743
744 status = i801_wait_intr(priv);
745 exit:
746 return i801_check_post(priv, status);
747 }
748
749 static int i801_set_block_buffer_mode(struct i801_priv *priv)
750 {
751 outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_E32B, SMBAUXCTL(priv));
752 if ((inb_p(SMBAUXCTL(priv)) & SMBAUXCTL_E32B) == 0)
753 return -EIO;
754 return 0;
755 }
756
757 /* Block transaction function */
758 static int i801_block_transaction(struct i801_priv *priv,
759 union i2c_smbus_data *data, char read_write,
760 int command, int hwpec)
761 {
762 int result = 0;
763 unsigned char hostc;
764
765 if (command == I2C_SMBUS_I2C_BLOCK_DATA) {
766 if (read_write == I2C_SMBUS_WRITE) {
767 /* set I2C_EN bit in configuration register */
768 pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &hostc);
769 pci_write_config_byte(priv->pci_dev, SMBHSTCFG,
770 hostc | SMBHSTCFG_I2C_EN);
771 } else if (!(priv->features & FEATURE_I2C_BLOCK_READ)) {
772 dev_err(&priv->pci_dev->dev,
773 "I2C block read is unsupported!\n");
774 return -EOPNOTSUPP;
775 }
776 }
777
778 if (read_write == I2C_SMBUS_WRITE
779 || command == I2C_SMBUS_I2C_BLOCK_DATA) {
780 if (data->block[0] < 1)
781 data->block[0] = 1;
782 if (data->block[0] > I2C_SMBUS_BLOCK_MAX)
783 data->block[0] = I2C_SMBUS_BLOCK_MAX;
784 } else {
785 data->block[0] = 32; /* max for SMBus block reads */
786 }
787
788 /* Experience has shown that the block buffer can only be used for
789 SMBus (not I2C) block transactions, even though the datasheet
790 doesn't mention this limitation. */
791 if ((priv->features & FEATURE_BLOCK_BUFFER)
792 && command != I2C_SMBUS_I2C_BLOCK_DATA
793 && i801_set_block_buffer_mode(priv) == 0)
794 result = i801_block_transaction_by_block(priv, data,
795 read_write, hwpec);
796 else
797 result = i801_block_transaction_byte_by_byte(priv, data,
798 read_write,
799 command, hwpec);
800
801 if (command == I2C_SMBUS_I2C_BLOCK_DATA
802 && read_write == I2C_SMBUS_WRITE) {
803 /* restore saved configuration register value */
804 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, hostc);
805 }
806 return result;
807 }
808
809 /* Return negative errno on error. */
810 static s32 i801_access(struct i2c_adapter *adap, u16 addr,
811 unsigned short flags, char read_write, u8 command,
812 int size, union i2c_smbus_data *data)
813 {
814 int hwpec;
815 int block = 0;
816 int ret = 0, xact = 0;
817 struct i801_priv *priv = i2c_get_adapdata(adap);
818
819 mutex_lock(&priv->acpi_lock);
820 if (priv->acpi_reserved) {
821 mutex_unlock(&priv->acpi_lock);
822 return -EBUSY;
823 }
824
825 pm_runtime_get_sync(&priv->pci_dev->dev);
826
827 hwpec = (priv->features & FEATURE_SMBUS_PEC) && (flags & I2C_CLIENT_PEC)
828 && size != I2C_SMBUS_QUICK
829 && size != I2C_SMBUS_I2C_BLOCK_DATA;
830
831 switch (size) {
832 case I2C_SMBUS_QUICK:
833 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
834 SMBHSTADD(priv));
835 xact = I801_QUICK;
836 break;
837 case I2C_SMBUS_BYTE:
838 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
839 SMBHSTADD(priv));
840 if (read_write == I2C_SMBUS_WRITE)
841 outb_p(command, SMBHSTCMD(priv));
842 xact = I801_BYTE;
843 break;
844 case I2C_SMBUS_BYTE_DATA:
845 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
846 SMBHSTADD(priv));
847 outb_p(command, SMBHSTCMD(priv));
848 if (read_write == I2C_SMBUS_WRITE)
849 outb_p(data->byte, SMBHSTDAT0(priv));
850 xact = I801_BYTE_DATA;
851 break;
852 case I2C_SMBUS_WORD_DATA:
853 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
854 SMBHSTADD(priv));
855 outb_p(command, SMBHSTCMD(priv));
856 if (read_write == I2C_SMBUS_WRITE) {
857 outb_p(data->word & 0xff, SMBHSTDAT0(priv));
858 outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1(priv));
859 }
860 xact = I801_WORD_DATA;
861 break;
862 case I2C_SMBUS_BLOCK_DATA:
863 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
864 SMBHSTADD(priv));
865 outb_p(command, SMBHSTCMD(priv));
866 block = 1;
867 break;
868 case I2C_SMBUS_I2C_BLOCK_DATA:
869 /*
870 * NB: page 240 of ICH5 datasheet shows that the R/#W
871 * bit should be cleared here, even when reading.
872 * However if SPD Write Disable is set (Lynx Point and later),
873 * the read will fail if we don't set the R/#W bit.
874 */
875 outb_p(((addr & 0x7f) << 1) |
876 ((priv->original_hstcfg & SMBHSTCFG_SPD_WD) ?
877 (read_write & 0x01) : 0),
878 SMBHSTADD(priv));
879 if (read_write == I2C_SMBUS_READ) {
880 /* NB: page 240 of ICH5 datasheet also shows
881 * that DATA1 is the cmd field when reading */
882 outb_p(command, SMBHSTDAT1(priv));
883 } else
884 outb_p(command, SMBHSTCMD(priv));
885 block = 1;
886 break;
887 default:
888 dev_err(&priv->pci_dev->dev, "Unsupported transaction %d\n",
889 size);
890 ret = -EOPNOTSUPP;
891 goto out;
892 }
893
894 if (hwpec) /* enable/disable hardware PEC */
895 outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_CRC, SMBAUXCTL(priv));
896 else
897 outb_p(inb_p(SMBAUXCTL(priv)) & (~SMBAUXCTL_CRC),
898 SMBAUXCTL(priv));
899
900 if (block)
901 ret = i801_block_transaction(priv, data, read_write, size,
902 hwpec);
903 else
904 ret = i801_transaction(priv, xact);
905
906 /* Some BIOSes don't like it when PEC is enabled at reboot or resume
907 time, so we forcibly disable it after every transaction. Turn off
908 E32B for the same reason. */
909 if (hwpec || block)
910 outb_p(inb_p(SMBAUXCTL(priv)) &
911 ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv));
912
913 if (block)
914 goto out;
915 if (ret)
916 goto out;
917 if ((read_write == I2C_SMBUS_WRITE) || (xact == I801_QUICK))
918 goto out;
919
920 switch (xact & 0x7f) {
921 case I801_BYTE: /* Result put in SMBHSTDAT0 */
922 case I801_BYTE_DATA:
923 data->byte = inb_p(SMBHSTDAT0(priv));
924 break;
925 case I801_WORD_DATA:
926 data->word = inb_p(SMBHSTDAT0(priv)) +
927 (inb_p(SMBHSTDAT1(priv)) << 8);
928 break;
929 }
930
931 out:
932 pm_runtime_mark_last_busy(&priv->pci_dev->dev);
933 pm_runtime_put_autosuspend(&priv->pci_dev->dev);
934 mutex_unlock(&priv->acpi_lock);
935 return ret;
936 }
937
938
939 static u32 i801_func(struct i2c_adapter *adapter)
940 {
941 struct i801_priv *priv = i2c_get_adapdata(adapter);
942
943 return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
944 I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
945 I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_WRITE_I2C_BLOCK |
946 ((priv->features & FEATURE_SMBUS_PEC) ? I2C_FUNC_SMBUS_PEC : 0) |
947 ((priv->features & FEATURE_I2C_BLOCK_READ) ?
948 I2C_FUNC_SMBUS_READ_I2C_BLOCK : 0) |
949 ((priv->features & FEATURE_HOST_NOTIFY) ?
950 I2C_FUNC_SMBUS_HOST_NOTIFY : 0);
951 }
952
953 static int i801_enable_host_notify(struct i2c_adapter *adapter)
954 {
955 struct i801_priv *priv = i2c_get_adapdata(adapter);
956
957 if (!(priv->features & FEATURE_HOST_NOTIFY))
958 return -ENOTSUPP;
959
960 if (!priv->host_notify)
961 priv->host_notify = i2c_setup_smbus_host_notify(adapter);
962 if (!priv->host_notify)
963 return -ENOMEM;
964
965 outb_p(SMBSLVCMD_HST_NTFY_INTREN, SMBSLVCMD(priv));
966 /* clear Host Notify bit to allow a new notification */
967 outb_p(SMBSLVSTS_HST_NTFY_STS, SMBSLVSTS(priv));
968
969 return 0;
970 }
971
972 static const struct i2c_algorithm smbus_algorithm = {
973 .smbus_xfer = i801_access,
974 .functionality = i801_func,
975 };
976
977 static const struct pci_device_id i801_ids[] = {
978 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_3) },
979 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_3) },
980 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_2) },
981 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_3) },
982 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_3) },
983 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_3) },
984 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_4) },
985 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_16) },
986 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_17) },
987 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_17) },
988 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_5) },
989 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_6) },
990 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EP80579_1) },
991 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_4) },
992 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_5) },
993 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS) },
994 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS) },
995 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS) },
996 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0) },
997 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1) },
998 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2) },
999 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS) },
1000 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS) },
1001 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS) },
1002 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS) },
1003 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_AVOTON_SMBUS) },
1004 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS) },
1005 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0) },
1006 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1) },
1007 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2) },
1008 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COLETOCREEK_SMBUS) },
1009 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WILDCATPOINT_SMBUS) },
1010 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_SMBUS) },
1011 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BAYTRAIL_SMBUS) },
1012 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BRASWELL_SMBUS) },
1013 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS) },
1014 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS) },
1015 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_DNV_SMBUS) },
1016 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BROXTON_SMBUS) },
1017 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LEWISBURG_SMBUS) },
1018 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LEWISBURG_SSKU_SMBUS) },
1019 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_KABYLAKE_PCH_H_SMBUS) },
1020 { 0, }
1021 };
1022
1023 MODULE_DEVICE_TABLE(pci, i801_ids);
1024
1025 #if defined CONFIG_X86 && defined CONFIG_DMI
1026 static unsigned char apanel_addr;
1027
1028 /* Scan the system ROM for the signature "FJKEYINF" */
1029 static __init const void __iomem *bios_signature(const void __iomem *bios)
1030 {
1031 ssize_t offset;
1032 const unsigned char signature[] = "FJKEYINF";
1033
1034 for (offset = 0; offset < 0x10000; offset += 0x10) {
1035 if (check_signature(bios + offset, signature,
1036 sizeof(signature)-1))
1037 return bios + offset;
1038 }
1039 return NULL;
1040 }
1041
1042 static void __init input_apanel_init(void)
1043 {
1044 void __iomem *bios;
1045 const void __iomem *p;
1046
1047 bios = ioremap(0xF0000, 0x10000); /* Can't fail */
1048 p = bios_signature(bios);
1049 if (p) {
1050 /* just use the first address */
1051 apanel_addr = readb(p + 8 + 3) >> 1;
1052 }
1053 iounmap(bios);
1054 }
1055
1056 struct dmi_onboard_device_info {
1057 const char *name;
1058 u8 type;
1059 unsigned short i2c_addr;
1060 const char *i2c_type;
1061 };
1062
1063 static const struct dmi_onboard_device_info dmi_devices[] = {
1064 { "Syleus", DMI_DEV_TYPE_OTHER, 0x73, "fscsyl" },
1065 { "Hermes", DMI_DEV_TYPE_OTHER, 0x73, "fscher" },
1066 { "Hades", DMI_DEV_TYPE_OTHER, 0x73, "fschds" },
1067 };
1068
1069 static void dmi_check_onboard_device(u8 type, const char *name,
1070 struct i2c_adapter *adap)
1071 {
1072 int i;
1073 struct i2c_board_info info;
1074
1075 for (i = 0; i < ARRAY_SIZE(dmi_devices); i++) {
1076 /* & ~0x80, ignore enabled/disabled bit */
1077 if ((type & ~0x80) != dmi_devices[i].type)
1078 continue;
1079 if (strcasecmp(name, dmi_devices[i].name))
1080 continue;
1081
1082 memset(&info, 0, sizeof(struct i2c_board_info));
1083 info.addr = dmi_devices[i].i2c_addr;
1084 strlcpy(info.type, dmi_devices[i].i2c_type, I2C_NAME_SIZE);
1085 i2c_new_device(adap, &info);
1086 break;
1087 }
1088 }
1089
1090 /* We use our own function to check for onboard devices instead of
1091 dmi_find_device() as some buggy BIOS's have the devices we are interested
1092 in marked as disabled */
1093 static void dmi_check_onboard_devices(const struct dmi_header *dm, void *adap)
1094 {
1095 int i, count;
1096
1097 if (dm->type != 10)
1098 return;
1099
1100 count = (dm->length - sizeof(struct dmi_header)) / 2;
1101 for (i = 0; i < count; i++) {
1102 const u8 *d = (char *)(dm + 1) + (i * 2);
1103 const char *name = ((char *) dm) + dm->length;
1104 u8 type = d[0];
1105 u8 s = d[1];
1106
1107 if (!s)
1108 continue;
1109 s--;
1110 while (s > 0 && name[0]) {
1111 name += strlen(name) + 1;
1112 s--;
1113 }
1114 if (name[0] == 0) /* Bogus string reference */
1115 continue;
1116
1117 dmi_check_onboard_device(type, name, adap);
1118 }
1119 }
1120
1121 /* Register optional slaves */
1122 static void i801_probe_optional_slaves(struct i801_priv *priv)
1123 {
1124 /* Only register slaves on main SMBus channel */
1125 if (priv->features & FEATURE_IDF)
1126 return;
1127
1128 if (apanel_addr) {
1129 struct i2c_board_info info;
1130
1131 memset(&info, 0, sizeof(struct i2c_board_info));
1132 info.addr = apanel_addr;
1133 strlcpy(info.type, "fujitsu_apanel", I2C_NAME_SIZE);
1134 i2c_new_device(&priv->adapter, &info);
1135 }
1136
1137 if (dmi_name_in_vendors("FUJITSU"))
1138 dmi_walk(dmi_check_onboard_devices, &priv->adapter);
1139 }
1140 #else
1141 static void __init input_apanel_init(void) {}
1142 static void i801_probe_optional_slaves(struct i801_priv *priv) {}
1143 #endif /* CONFIG_X86 && CONFIG_DMI */
1144
1145 #if IS_ENABLED(CONFIG_I2C_MUX_GPIO) && defined CONFIG_DMI
1146 static struct i801_mux_config i801_mux_config_asus_z8_d12 = {
1147 .gpio_chip = "gpio_ich",
1148 .values = { 0x02, 0x03 },
1149 .n_values = 2,
1150 .classes = { I2C_CLASS_SPD, I2C_CLASS_SPD },
1151 .gpios = { 52, 53 },
1152 .n_gpios = 2,
1153 };
1154
1155 static struct i801_mux_config i801_mux_config_asus_z8_d18 = {
1156 .gpio_chip = "gpio_ich",
1157 .values = { 0x02, 0x03, 0x01 },
1158 .n_values = 3,
1159 .classes = { I2C_CLASS_SPD, I2C_CLASS_SPD, I2C_CLASS_SPD },
1160 .gpios = { 52, 53 },
1161 .n_gpios = 2,
1162 };
1163
1164 static const struct dmi_system_id mux_dmi_table[] = {
1165 {
1166 .matches = {
1167 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1168 DMI_MATCH(DMI_BOARD_NAME, "Z8NA-D6(C)"),
1169 },
1170 .driver_data = &i801_mux_config_asus_z8_d12,
1171 },
1172 {
1173 .matches = {
1174 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1175 DMI_MATCH(DMI_BOARD_NAME, "Z8P(N)E-D12(X)"),
1176 },
1177 .driver_data = &i801_mux_config_asus_z8_d12,
1178 },
1179 {
1180 .matches = {
1181 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1182 DMI_MATCH(DMI_BOARD_NAME, "Z8NH-D12"),
1183 },
1184 .driver_data = &i801_mux_config_asus_z8_d12,
1185 },
1186 {
1187 .matches = {
1188 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1189 DMI_MATCH(DMI_BOARD_NAME, "Z8PH-D12/IFB"),
1190 },
1191 .driver_data = &i801_mux_config_asus_z8_d12,
1192 },
1193 {
1194 .matches = {
1195 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1196 DMI_MATCH(DMI_BOARD_NAME, "Z8NR-D12"),
1197 },
1198 .driver_data = &i801_mux_config_asus_z8_d12,
1199 },
1200 {
1201 .matches = {
1202 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1203 DMI_MATCH(DMI_BOARD_NAME, "Z8P(N)H-D12"),
1204 },
1205 .driver_data = &i801_mux_config_asus_z8_d12,
1206 },
1207 {
1208 .matches = {
1209 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1210 DMI_MATCH(DMI_BOARD_NAME, "Z8PG-D18"),
1211 },
1212 .driver_data = &i801_mux_config_asus_z8_d18,
1213 },
1214 {
1215 .matches = {
1216 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1217 DMI_MATCH(DMI_BOARD_NAME, "Z8PE-D18"),
1218 },
1219 .driver_data = &i801_mux_config_asus_z8_d18,
1220 },
1221 {
1222 .matches = {
1223 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1224 DMI_MATCH(DMI_BOARD_NAME, "Z8PS-D12"),
1225 },
1226 .driver_data = &i801_mux_config_asus_z8_d12,
1227 },
1228 { }
1229 };
1230
1231 /* Setup multiplexing if needed */
1232 static int i801_add_mux(struct i801_priv *priv)
1233 {
1234 struct device *dev = &priv->adapter.dev;
1235 const struct i801_mux_config *mux_config;
1236 struct i2c_mux_gpio_platform_data gpio_data;
1237 int err;
1238
1239 if (!priv->mux_drvdata)
1240 return 0;
1241 mux_config = priv->mux_drvdata;
1242
1243 /* Prepare the platform data */
1244 memset(&gpio_data, 0, sizeof(struct i2c_mux_gpio_platform_data));
1245 gpio_data.parent = priv->adapter.nr;
1246 gpio_data.values = mux_config->values;
1247 gpio_data.n_values = mux_config->n_values;
1248 gpio_data.classes = mux_config->classes;
1249 gpio_data.gpio_chip = mux_config->gpio_chip;
1250 gpio_data.gpios = mux_config->gpios;
1251 gpio_data.n_gpios = mux_config->n_gpios;
1252 gpio_data.idle = I2C_MUX_GPIO_NO_IDLE;
1253
1254 /* Register the mux device */
1255 priv->mux_pdev = platform_device_register_data(dev, "i2c-mux-gpio",
1256 PLATFORM_DEVID_AUTO, &gpio_data,
1257 sizeof(struct i2c_mux_gpio_platform_data));
1258 if (IS_ERR(priv->mux_pdev)) {
1259 err = PTR_ERR(priv->mux_pdev);
1260 priv->mux_pdev = NULL;
1261 dev_err(dev, "Failed to register i2c-mux-gpio device\n");
1262 return err;
1263 }
1264
1265 return 0;
1266 }
1267
1268 static void i801_del_mux(struct i801_priv *priv)
1269 {
1270 if (priv->mux_pdev)
1271 platform_device_unregister(priv->mux_pdev);
1272 }
1273
1274 static unsigned int i801_get_adapter_class(struct i801_priv *priv)
1275 {
1276 const struct dmi_system_id *id;
1277 const struct i801_mux_config *mux_config;
1278 unsigned int class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
1279 int i;
1280
1281 id = dmi_first_match(mux_dmi_table);
1282 if (id) {
1283 /* Remove branch classes from trunk */
1284 mux_config = id->driver_data;
1285 for (i = 0; i < mux_config->n_values; i++)
1286 class &= ~mux_config->classes[i];
1287
1288 /* Remember for later */
1289 priv->mux_drvdata = mux_config;
1290 }
1291
1292 return class;
1293 }
1294 #else
1295 static inline int i801_add_mux(struct i801_priv *priv) { return 0; }
1296 static inline void i801_del_mux(struct i801_priv *priv) { }
1297
1298 static inline unsigned int i801_get_adapter_class(struct i801_priv *priv)
1299 {
1300 return I2C_CLASS_HWMON | I2C_CLASS_SPD;
1301 }
1302 #endif
1303
1304 static const struct itco_wdt_platform_data tco_platform_data = {
1305 .name = "Intel PCH",
1306 .version = 4,
1307 };
1308
1309 static DEFINE_SPINLOCK(p2sb_spinlock);
1310
1311 static void i801_add_tco(struct i801_priv *priv)
1312 {
1313 struct pci_dev *pci_dev = priv->pci_dev;
1314 struct resource tco_res[3], *res;
1315 struct platform_device *pdev;
1316 unsigned int devfn;
1317 u32 tco_base, tco_ctl;
1318 u32 base_addr, ctrl_val;
1319 u64 base64_addr;
1320
1321 if (!(priv->features & FEATURE_TCO))
1322 return;
1323
1324 pci_read_config_dword(pci_dev, TCOBASE, &tco_base);
1325 pci_read_config_dword(pci_dev, TCOCTL, &tco_ctl);
1326 if (!(tco_ctl & TCOCTL_EN))
1327 return;
1328
1329 memset(tco_res, 0, sizeof(tco_res));
1330
1331 res = &tco_res[ICH_RES_IO_TCO];
1332 res->start = tco_base & ~1;
1333 res->end = res->start + 32 - 1;
1334 res->flags = IORESOURCE_IO;
1335
1336 /*
1337 * Power Management registers.
1338 */
1339 devfn = PCI_DEVFN(PCI_SLOT(pci_dev->devfn), 2);
1340 pci_bus_read_config_dword(pci_dev->bus, devfn, ACPIBASE, &base_addr);
1341
1342 res = &tco_res[ICH_RES_IO_SMI];
1343 res->start = (base_addr & ~1) + ACPIBASE_SMI_OFF;
1344 res->end = res->start + 3;
1345 res->flags = IORESOURCE_IO;
1346
1347 /*
1348 * Enable the ACPI I/O space.
1349 */
1350 pci_bus_read_config_dword(pci_dev->bus, devfn, ACPICTRL, &ctrl_val);
1351 ctrl_val |= ACPICTRL_EN;
1352 pci_bus_write_config_dword(pci_dev->bus, devfn, ACPICTRL, ctrl_val);
1353
1354 /*
1355 * We must access the NO_REBOOT bit over the Primary to Sideband
1356 * bridge (P2SB). The BIOS prevents the P2SB device from being
1357 * enumerated by the PCI subsystem, so we need to unhide/hide it
1358 * to lookup the P2SB BAR.
1359 */
1360 spin_lock(&p2sb_spinlock);
1361
1362 devfn = PCI_DEVFN(PCI_SLOT(pci_dev->devfn), 1);
1363
1364 /* Unhide the P2SB device */
1365 pci_bus_write_config_byte(pci_dev->bus, devfn, 0xe1, 0x0);
1366
1367 pci_bus_read_config_dword(pci_dev->bus, devfn, SBREG_BAR, &base_addr);
1368 base64_addr = base_addr & 0xfffffff0;
1369
1370 pci_bus_read_config_dword(pci_dev->bus, devfn, SBREG_BAR + 0x4, &base_addr);
1371 base64_addr |= (u64)base_addr << 32;
1372
1373 /* Hide the P2SB device */
1374 pci_bus_write_config_byte(pci_dev->bus, devfn, 0xe1, 0x1);
1375 spin_unlock(&p2sb_spinlock);
1376
1377 res = &tco_res[ICH_RES_MEM_OFF];
1378 res->start = (resource_size_t)base64_addr + SBREG_SMBCTRL;
1379 res->end = res->start + 3;
1380 res->flags = IORESOURCE_MEM;
1381
1382 pdev = platform_device_register_resndata(&pci_dev->dev, "iTCO_wdt", -1,
1383 tco_res, 3, &tco_platform_data,
1384 sizeof(tco_platform_data));
1385 if (IS_ERR(pdev)) {
1386 dev_warn(&pci_dev->dev, "failed to create iTCO device\n");
1387 return;
1388 }
1389
1390 priv->tco_pdev = pdev;
1391 }
1392
1393 #ifdef CONFIG_ACPI
1394 static acpi_status
1395 i801_acpi_io_handler(u32 function, acpi_physical_address address, u32 bits,
1396 u64 *value, void *handler_context, void *region_context)
1397 {
1398 struct i801_priv *priv = handler_context;
1399 struct pci_dev *pdev = priv->pci_dev;
1400 acpi_status status;
1401
1402 /*
1403 * Once BIOS AML code touches the OpRegion we warn and inhibit any
1404 * further access from the driver itself. This device is now owned
1405 * by the system firmware.
1406 */
1407 mutex_lock(&priv->acpi_lock);
1408
1409 if (!priv->acpi_reserved) {
1410 priv->acpi_reserved = true;
1411
1412 dev_warn(&pdev->dev, "BIOS is accessing SMBus registers\n");
1413 dev_warn(&pdev->dev, "Driver SMBus register access inhibited\n");
1414
1415 /*
1416 * BIOS is accessing the host controller so prevent it from
1417 * suspending automatically from now on.
1418 */
1419 pm_runtime_get_sync(&pdev->dev);
1420 }
1421
1422 if ((function & ACPI_IO_MASK) == ACPI_READ)
1423 status = acpi_os_read_port(address, (u32 *)value, bits);
1424 else
1425 status = acpi_os_write_port(address, (u32)*value, bits);
1426
1427 mutex_unlock(&priv->acpi_lock);
1428
1429 return status;
1430 }
1431
1432 static int i801_acpi_probe(struct i801_priv *priv)
1433 {
1434 struct acpi_device *adev;
1435 acpi_status status;
1436
1437 adev = ACPI_COMPANION(&priv->pci_dev->dev);
1438 if (adev) {
1439 status = acpi_install_address_space_handler(adev->handle,
1440 ACPI_ADR_SPACE_SYSTEM_IO, i801_acpi_io_handler,
1441 NULL, priv);
1442 if (ACPI_SUCCESS(status))
1443 return 0;
1444 }
1445
1446 return acpi_check_resource_conflict(&priv->pci_dev->resource[SMBBAR]);
1447 }
1448
1449 static void i801_acpi_remove(struct i801_priv *priv)
1450 {
1451 struct acpi_device *adev;
1452
1453 adev = ACPI_COMPANION(&priv->pci_dev->dev);
1454 if (!adev)
1455 return;
1456
1457 acpi_remove_address_space_handler(adev->handle,
1458 ACPI_ADR_SPACE_SYSTEM_IO, i801_acpi_io_handler);
1459
1460 mutex_lock(&priv->acpi_lock);
1461 if (priv->acpi_reserved)
1462 pm_runtime_put(&priv->pci_dev->dev);
1463 mutex_unlock(&priv->acpi_lock);
1464 }
1465 #else
1466 static inline int i801_acpi_probe(struct i801_priv *priv) { return 0; }
1467 static inline void i801_acpi_remove(struct i801_priv *priv) { }
1468 #endif
1469
1470 static int i801_probe(struct pci_dev *dev, const struct pci_device_id *id)
1471 {
1472 unsigned char temp;
1473 int err, i;
1474 struct i801_priv *priv;
1475
1476 priv = devm_kzalloc(&dev->dev, sizeof(*priv), GFP_KERNEL);
1477 if (!priv)
1478 return -ENOMEM;
1479
1480 i2c_set_adapdata(&priv->adapter, priv);
1481 priv->adapter.owner = THIS_MODULE;
1482 priv->adapter.class = i801_get_adapter_class(priv);
1483 priv->adapter.algo = &smbus_algorithm;
1484 priv->adapter.dev.parent = &dev->dev;
1485 ACPI_COMPANION_SET(&priv->adapter.dev, ACPI_COMPANION(&dev->dev));
1486 priv->adapter.retries = 3;
1487 mutex_init(&priv->acpi_lock);
1488
1489 priv->pci_dev = dev;
1490 switch (dev->device) {
1491 case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS:
1492 case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS:
1493 case PCI_DEVICE_ID_INTEL_LEWISBURG_SMBUS:
1494 case PCI_DEVICE_ID_INTEL_LEWISBURG_SSKU_SMBUS:
1495 case PCI_DEVICE_ID_INTEL_DNV_SMBUS:
1496 case PCI_DEVICE_ID_INTEL_KABYLAKE_PCH_H_SMBUS:
1497 priv->features |= FEATURE_I2C_BLOCK_READ;
1498 priv->features |= FEATURE_IRQ;
1499 priv->features |= FEATURE_SMBUS_PEC;
1500 priv->features |= FEATURE_BLOCK_BUFFER;
1501 /* If we have ACPI based watchdog use that instead */
1502 if (!acpi_has_watchdog())
1503 priv->features |= FEATURE_TCO;
1504 priv->features |= FEATURE_HOST_NOTIFY;
1505 break;
1506
1507 case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0:
1508 case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1:
1509 case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2:
1510 case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0:
1511 case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1:
1512 case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2:
1513 priv->features |= FEATURE_IDF;
1514 /* fall through */
1515 default:
1516 priv->features |= FEATURE_I2C_BLOCK_READ;
1517 priv->features |= FEATURE_IRQ;
1518 /* fall through */
1519 case PCI_DEVICE_ID_INTEL_82801DB_3:
1520 priv->features |= FEATURE_SMBUS_PEC;
1521 priv->features |= FEATURE_BLOCK_BUFFER;
1522 /* fall through */
1523 case PCI_DEVICE_ID_INTEL_82801CA_3:
1524 priv->features |= FEATURE_HOST_NOTIFY;
1525 /* fall through */
1526 case PCI_DEVICE_ID_INTEL_82801BA_2:
1527 case PCI_DEVICE_ID_INTEL_82801AB_3:
1528 case PCI_DEVICE_ID_INTEL_82801AA_3:
1529 break;
1530 }
1531
1532 /* Disable features on user request */
1533 for (i = 0; i < ARRAY_SIZE(i801_feature_names); i++) {
1534 if (priv->features & disable_features & (1 << i))
1535 dev_notice(&dev->dev, "%s disabled by user\n",
1536 i801_feature_names[i]);
1537 }
1538 priv->features &= ~disable_features;
1539
1540 err = pcim_enable_device(dev);
1541 if (err) {
1542 dev_err(&dev->dev, "Failed to enable SMBus PCI device (%d)\n",
1543 err);
1544 return err;
1545 }
1546 pcim_pin_device(dev);
1547
1548 /* Determine the address of the SMBus area */
1549 priv->smba = pci_resource_start(dev, SMBBAR);
1550 if (!priv->smba) {
1551 dev_err(&dev->dev,
1552 "SMBus base address uninitialized, upgrade BIOS\n");
1553 return -ENODEV;
1554 }
1555
1556 if (i801_acpi_probe(priv))
1557 return -ENODEV;
1558
1559 err = pcim_iomap_regions(dev, 1 << SMBBAR,
1560 dev_driver_string(&dev->dev));
1561 if (err) {
1562 dev_err(&dev->dev,
1563 "Failed to request SMBus region 0x%lx-0x%Lx\n",
1564 priv->smba,
1565 (unsigned long long)pci_resource_end(dev, SMBBAR));
1566 i801_acpi_remove(priv);
1567 return err;
1568 }
1569
1570 pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &temp);
1571 priv->original_hstcfg = temp;
1572 temp &= ~SMBHSTCFG_I2C_EN; /* SMBus timing */
1573 if (!(temp & SMBHSTCFG_HST_EN)) {
1574 dev_info(&dev->dev, "Enabling SMBus device\n");
1575 temp |= SMBHSTCFG_HST_EN;
1576 }
1577 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, temp);
1578
1579 if (temp & SMBHSTCFG_SMB_SMI_EN) {
1580 dev_dbg(&dev->dev, "SMBus using interrupt SMI#\n");
1581 /* Disable SMBus interrupt feature if SMBus using SMI# */
1582 priv->features &= ~FEATURE_IRQ;
1583 }
1584 if (temp & SMBHSTCFG_SPD_WD)
1585 dev_info(&dev->dev, "SPD Write Disable is set\n");
1586
1587 /* Clear special mode bits */
1588 if (priv->features & (FEATURE_SMBUS_PEC | FEATURE_BLOCK_BUFFER))
1589 outb_p(inb_p(SMBAUXCTL(priv)) &
1590 ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv));
1591
1592 /* Default timeout in interrupt mode: 200 ms */
1593 priv->adapter.timeout = HZ / 5;
1594
1595 if (priv->features & FEATURE_IRQ) {
1596 u16 pcictl, pcists;
1597
1598 /* Complain if an interrupt is already pending */
1599 pci_read_config_word(priv->pci_dev, SMBPCISTS, &pcists);
1600 if (pcists & SMBPCISTS_INTS)
1601 dev_warn(&dev->dev, "An interrupt is pending!\n");
1602
1603 /* Check if interrupts have been disabled */
1604 pci_read_config_word(priv->pci_dev, SMBPCICTL, &pcictl);
1605 if (pcictl & SMBPCICTL_INTDIS) {
1606 dev_info(&dev->dev, "Interrupts are disabled\n");
1607 priv->features &= ~FEATURE_IRQ;
1608 }
1609 }
1610
1611 if (priv->features & FEATURE_IRQ) {
1612 init_waitqueue_head(&priv->waitq);
1613
1614 err = devm_request_irq(&dev->dev, dev->irq, i801_isr,
1615 IRQF_SHARED,
1616 dev_driver_string(&dev->dev), priv);
1617 if (err) {
1618 dev_err(&dev->dev, "Failed to allocate irq %d: %d\n",
1619 dev->irq, err);
1620 priv->features &= ~FEATURE_IRQ;
1621 }
1622 }
1623 dev_info(&dev->dev, "SMBus using %s\n",
1624 priv->features & FEATURE_IRQ ? "PCI interrupt" : "polling");
1625
1626 i801_add_tco(priv);
1627
1628 snprintf(priv->adapter.name, sizeof(priv->adapter.name),
1629 "SMBus I801 adapter at %04lx", priv->smba);
1630 err = i2c_add_adapter(&priv->adapter);
1631 if (err) {
1632 i801_acpi_remove(priv);
1633 return err;
1634 }
1635
1636 /*
1637 * Enable Host Notify for chips that supports it.
1638 * It is done after i2c_add_adapter() so that we are sure the work queue
1639 * is not used if i2c_add_adapter() fails.
1640 */
1641 err = i801_enable_host_notify(&priv->adapter);
1642 if (err && err != -ENOTSUPP)
1643 dev_warn(&dev->dev, "Unable to enable SMBus Host Notify\n");
1644
1645 i801_probe_optional_slaves(priv);
1646 /* We ignore errors - multiplexing is optional */
1647 i801_add_mux(priv);
1648
1649 pci_set_drvdata(dev, priv);
1650
1651 pm_runtime_set_autosuspend_delay(&dev->dev, 1000);
1652 pm_runtime_use_autosuspend(&dev->dev);
1653 pm_runtime_put_autosuspend(&dev->dev);
1654 pm_runtime_allow(&dev->dev);
1655
1656 return 0;
1657 }
1658
1659 static void i801_remove(struct pci_dev *dev)
1660 {
1661 struct i801_priv *priv = pci_get_drvdata(dev);
1662
1663 pm_runtime_forbid(&dev->dev);
1664 pm_runtime_get_noresume(&dev->dev);
1665
1666 i801_del_mux(priv);
1667 i2c_del_adapter(&priv->adapter);
1668 i801_acpi_remove(priv);
1669 pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg);
1670
1671 platform_device_unregister(priv->tco_pdev);
1672
1673 /*
1674 * do not call pci_disable_device(dev) since it can cause hard hangs on
1675 * some systems during power-off (eg. Fujitsu-Siemens Lifebook E8010)
1676 */
1677 }
1678
1679 #ifdef CONFIG_PM
1680 static int i801_suspend(struct device *dev)
1681 {
1682 struct pci_dev *pci_dev = to_pci_dev(dev);
1683 struct i801_priv *priv = pci_get_drvdata(pci_dev);
1684
1685 pci_write_config_byte(pci_dev, SMBHSTCFG, priv->original_hstcfg);
1686 return 0;
1687 }
1688
1689 static int i801_resume(struct device *dev)
1690 {
1691 struct pci_dev *pci_dev = to_pci_dev(dev);
1692 struct i801_priv *priv = pci_get_drvdata(pci_dev);
1693 int err;
1694
1695 err = i801_enable_host_notify(&priv->adapter);
1696 if (err && err != -ENOTSUPP)
1697 dev_warn(dev, "Unable to enable SMBus Host Notify\n");
1698
1699 return 0;
1700 }
1701 #endif
1702
1703 static UNIVERSAL_DEV_PM_OPS(i801_pm_ops, i801_suspend,
1704 i801_resume, NULL);
1705
1706 static struct pci_driver i801_driver = {
1707 .name = "i801_smbus",
1708 .id_table = i801_ids,
1709 .probe = i801_probe,
1710 .remove = i801_remove,
1711 .driver = {
1712 .pm = &i801_pm_ops,
1713 },
1714 };
1715
1716 static int __init i2c_i801_init(void)
1717 {
1718 if (dmi_name_in_vendors("FUJITSU"))
1719 input_apanel_init();
1720 return pci_register_driver(&i801_driver);
1721 }
1722
1723 static void __exit i2c_i801_exit(void)
1724 {
1725 pci_unregister_driver(&i801_driver);
1726 }
1727
1728 MODULE_AUTHOR("Mark D. Studebaker <mdsxyz123@yahoo.com>, Jean Delvare <jdelvare@suse.de>");
1729 MODULE_DESCRIPTION("I801 SMBus driver");
1730 MODULE_LICENSE("GPL");
1731
1732 module_init(i2c_i801_init);
1733 module_exit(i2c_i801_exit);
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