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Merge tag 'upstream-4.4-rc7' of git://git.infradead.org/linux-ubifs
[mirror_ubuntu-zesty-kernel.git] / drivers / i2c / busses / i2c-imx.c
1 /*
2 * Copyright (C) 2002 Motorola GSG-China
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version 2
7 * of the License, or (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * Author:
15 * Darius Augulis, Teltonika Inc.
16 *
17 * Desc.:
18 * Implementation of I2C Adapter/Algorithm Driver
19 * for I2C Bus integrated in Freescale i.MX/MXC processors
20 *
21 * Derived from Motorola GSG China I2C example driver
22 *
23 * Copyright (C) 2005 Torsten Koschorrek <koschorrek at synertronixx.de
24 * Copyright (C) 2005 Matthias Blaschke <blaschke at synertronixx.de
25 * Copyright (C) 2007 RightHand Technologies, Inc.
26 * Copyright (C) 2008 Darius Augulis <darius.augulis at teltonika.lt>
27 *
28 * Copyright 2013 Freescale Semiconductor, Inc.
29 *
30 */
31
32 /** Includes *******************************************************************
33 *******************************************************************************/
34
35 #include <linux/clk.h>
36 #include <linux/completion.h>
37 #include <linux/delay.h>
38 #include <linux/dma-mapping.h>
39 #include <linux/dmaengine.h>
40 #include <linux/dmapool.h>
41 #include <linux/err.h>
42 #include <linux/errno.h>
43 #include <linux/i2c.h>
44 #include <linux/init.h>
45 #include <linux/interrupt.h>
46 #include <linux/io.h>
47 #include <linux/kernel.h>
48 #include <linux/module.h>
49 #include <linux/of.h>
50 #include <linux/of_device.h>
51 #include <linux/of_dma.h>
52 #include <linux/of_gpio.h>
53 #include <linux/pinctrl/consumer.h>
54 #include <linux/platform_data/i2c-imx.h>
55 #include <linux/platform_device.h>
56 #include <linux/sched.h>
57 #include <linux/slab.h>
58
59 /** Defines ********************************************************************
60 *******************************************************************************/
61
62 /* This will be the driver name the kernel reports */
63 #define DRIVER_NAME "imx-i2c"
64
65 /* Default value */
66 #define IMX_I2C_BIT_RATE 100000 /* 100kHz */
67
68 /*
69 * Enable DMA if transfer byte size is bigger than this threshold.
70 * As the hardware request, it must bigger than 4 bytes.\
71 * I have set '16' here, maybe it's not the best but I think it's
72 * the appropriate.
73 */
74 #define DMA_THRESHOLD 16
75 #define DMA_TIMEOUT 1000
76
77 /* IMX I2C registers:
78 * the I2C register offset is different between SoCs,
79 * to provid support for all these chips, split the
80 * register offset into a fixed base address and a
81 * variable shift value, then the full register offset
82 * will be calculated by
83 * reg_off = ( reg_base_addr << reg_shift)
84 */
85 #define IMX_I2C_IADR 0x00 /* i2c slave address */
86 #define IMX_I2C_IFDR 0x01 /* i2c frequency divider */
87 #define IMX_I2C_I2CR 0x02 /* i2c control */
88 #define IMX_I2C_I2SR 0x03 /* i2c status */
89 #define IMX_I2C_I2DR 0x04 /* i2c transfer data */
90
91 #define IMX_I2C_REGSHIFT 2
92 #define VF610_I2C_REGSHIFT 0
93
94 /* Bits of IMX I2C registers */
95 #define I2SR_RXAK 0x01
96 #define I2SR_IIF 0x02
97 #define I2SR_SRW 0x04
98 #define I2SR_IAL 0x10
99 #define I2SR_IBB 0x20
100 #define I2SR_IAAS 0x40
101 #define I2SR_ICF 0x80
102 #define I2CR_DMAEN 0x02
103 #define I2CR_RSTA 0x04
104 #define I2CR_TXAK 0x08
105 #define I2CR_MTX 0x10
106 #define I2CR_MSTA 0x20
107 #define I2CR_IIEN 0x40
108 #define I2CR_IEN 0x80
109
110 /* register bits different operating codes definition:
111 * 1) I2SR: Interrupt flags clear operation differ between SoCs:
112 * - write zero to clear(w0c) INT flag on i.MX,
113 * - but write one to clear(w1c) INT flag on Vybrid.
114 * 2) I2CR: I2C module enable operation also differ between SoCs:
115 * - set I2CR_IEN bit enable the module on i.MX,
116 * - but clear I2CR_IEN bit enable the module on Vybrid.
117 */
118 #define I2SR_CLR_OPCODE_W0C 0x0
119 #define I2SR_CLR_OPCODE_W1C (I2SR_IAL | I2SR_IIF)
120 #define I2CR_IEN_OPCODE_0 0x0
121 #define I2CR_IEN_OPCODE_1 I2CR_IEN
122
123 /** Variables ******************************************************************
124 *******************************************************************************/
125
126 /*
127 * sorted list of clock divider, register value pairs
128 * taken from table 26-5, p.26-9, Freescale i.MX
129 * Integrated Portable System Processor Reference Manual
130 * Document Number: MC9328MXLRM, Rev. 5.1, 06/2007
131 *
132 * Duplicated divider values removed from list
133 */
134 struct imx_i2c_clk_pair {
135 u16 div;
136 u16 val;
137 };
138
139 static struct imx_i2c_clk_pair imx_i2c_clk_div[] = {
140 { 22, 0x20 }, { 24, 0x21 }, { 26, 0x22 }, { 28, 0x23 },
141 { 30, 0x00 }, { 32, 0x24 }, { 36, 0x25 }, { 40, 0x26 },
142 { 42, 0x03 }, { 44, 0x27 }, { 48, 0x28 }, { 52, 0x05 },
143 { 56, 0x29 }, { 60, 0x06 }, { 64, 0x2A }, { 72, 0x2B },
144 { 80, 0x2C }, { 88, 0x09 }, { 96, 0x2D }, { 104, 0x0A },
145 { 112, 0x2E }, { 128, 0x2F }, { 144, 0x0C }, { 160, 0x30 },
146 { 192, 0x31 }, { 224, 0x32 }, { 240, 0x0F }, { 256, 0x33 },
147 { 288, 0x10 }, { 320, 0x34 }, { 384, 0x35 }, { 448, 0x36 },
148 { 480, 0x13 }, { 512, 0x37 }, { 576, 0x14 }, { 640, 0x38 },
149 { 768, 0x39 }, { 896, 0x3A }, { 960, 0x17 }, { 1024, 0x3B },
150 { 1152, 0x18 }, { 1280, 0x3C }, { 1536, 0x3D }, { 1792, 0x3E },
151 { 1920, 0x1B }, { 2048, 0x3F }, { 2304, 0x1C }, { 2560, 0x1D },
152 { 3072, 0x1E }, { 3840, 0x1F }
153 };
154
155 /* Vybrid VF610 clock divider, register value pairs */
156 static struct imx_i2c_clk_pair vf610_i2c_clk_div[] = {
157 { 20, 0x00 }, { 22, 0x01 }, { 24, 0x02 }, { 26, 0x03 },
158 { 28, 0x04 }, { 30, 0x05 }, { 32, 0x09 }, { 34, 0x06 },
159 { 36, 0x0A }, { 40, 0x07 }, { 44, 0x0C }, { 48, 0x0D },
160 { 52, 0x43 }, { 56, 0x0E }, { 60, 0x45 }, { 64, 0x12 },
161 { 68, 0x0F }, { 72, 0x13 }, { 80, 0x14 }, { 88, 0x15 },
162 { 96, 0x19 }, { 104, 0x16 }, { 112, 0x1A }, { 128, 0x17 },
163 { 136, 0x4F }, { 144, 0x1C }, { 160, 0x1D }, { 176, 0x55 },
164 { 192, 0x1E }, { 208, 0x56 }, { 224, 0x22 }, { 228, 0x24 },
165 { 240, 0x1F }, { 256, 0x23 }, { 288, 0x5C }, { 320, 0x25 },
166 { 384, 0x26 }, { 448, 0x2A }, { 480, 0x27 }, { 512, 0x2B },
167 { 576, 0x2C }, { 640, 0x2D }, { 768, 0x31 }, { 896, 0x32 },
168 { 960, 0x2F }, { 1024, 0x33 }, { 1152, 0x34 }, { 1280, 0x35 },
169 { 1536, 0x36 }, { 1792, 0x3A }, { 1920, 0x37 }, { 2048, 0x3B },
170 { 2304, 0x3C }, { 2560, 0x3D }, { 3072, 0x3E }, { 3584, 0x7A },
171 { 3840, 0x3F }, { 4096, 0x7B }, { 5120, 0x7D }, { 6144, 0x7E },
172 };
173
174 enum imx_i2c_type {
175 IMX1_I2C,
176 IMX21_I2C,
177 VF610_I2C,
178 };
179
180 struct imx_i2c_hwdata {
181 enum imx_i2c_type devtype;
182 unsigned regshift;
183 struct imx_i2c_clk_pair *clk_div;
184 unsigned ndivs;
185 unsigned i2sr_clr_opcode;
186 unsigned i2cr_ien_opcode;
187 };
188
189 struct imx_i2c_dma {
190 struct dma_chan *chan_tx;
191 struct dma_chan *chan_rx;
192 struct dma_chan *chan_using;
193 struct completion cmd_complete;
194 dma_addr_t dma_buf;
195 unsigned int dma_len;
196 enum dma_transfer_direction dma_transfer_dir;
197 enum dma_data_direction dma_data_dir;
198 };
199
200 struct imx_i2c_struct {
201 struct i2c_adapter adapter;
202 struct clk *clk;
203 void __iomem *base;
204 wait_queue_head_t queue;
205 unsigned long i2csr;
206 unsigned int disable_delay;
207 int stopped;
208 unsigned int ifdr; /* IMX_I2C_IFDR */
209 unsigned int cur_clk;
210 unsigned int bitrate;
211 const struct imx_i2c_hwdata *hwdata;
212 struct i2c_bus_recovery_info rinfo;
213
214 struct pinctrl *pinctrl;
215 struct pinctrl_state *pinctrl_pins_default;
216 struct pinctrl_state *pinctrl_pins_gpio;
217
218 struct imx_i2c_dma *dma;
219 };
220
221 static const struct imx_i2c_hwdata imx1_i2c_hwdata = {
222 .devtype = IMX1_I2C,
223 .regshift = IMX_I2C_REGSHIFT,
224 .clk_div = imx_i2c_clk_div,
225 .ndivs = ARRAY_SIZE(imx_i2c_clk_div),
226 .i2sr_clr_opcode = I2SR_CLR_OPCODE_W0C,
227 .i2cr_ien_opcode = I2CR_IEN_OPCODE_1,
228
229 };
230
231 static const struct imx_i2c_hwdata imx21_i2c_hwdata = {
232 .devtype = IMX21_I2C,
233 .regshift = IMX_I2C_REGSHIFT,
234 .clk_div = imx_i2c_clk_div,
235 .ndivs = ARRAY_SIZE(imx_i2c_clk_div),
236 .i2sr_clr_opcode = I2SR_CLR_OPCODE_W0C,
237 .i2cr_ien_opcode = I2CR_IEN_OPCODE_1,
238
239 };
240
241 static struct imx_i2c_hwdata vf610_i2c_hwdata = {
242 .devtype = VF610_I2C,
243 .regshift = VF610_I2C_REGSHIFT,
244 .clk_div = vf610_i2c_clk_div,
245 .ndivs = ARRAY_SIZE(vf610_i2c_clk_div),
246 .i2sr_clr_opcode = I2SR_CLR_OPCODE_W1C,
247 .i2cr_ien_opcode = I2CR_IEN_OPCODE_0,
248
249 };
250
251 static const struct platform_device_id imx_i2c_devtype[] = {
252 {
253 .name = "imx1-i2c",
254 .driver_data = (kernel_ulong_t)&imx1_i2c_hwdata,
255 }, {
256 .name = "imx21-i2c",
257 .driver_data = (kernel_ulong_t)&imx21_i2c_hwdata,
258 }, {
259 /* sentinel */
260 }
261 };
262 MODULE_DEVICE_TABLE(platform, imx_i2c_devtype);
263
264 static const struct of_device_id i2c_imx_dt_ids[] = {
265 { .compatible = "fsl,imx1-i2c", .data = &imx1_i2c_hwdata, },
266 { .compatible = "fsl,imx21-i2c", .data = &imx21_i2c_hwdata, },
267 { .compatible = "fsl,vf610-i2c", .data = &vf610_i2c_hwdata, },
268 { /* sentinel */ }
269 };
270 MODULE_DEVICE_TABLE(of, i2c_imx_dt_ids);
271
272 static inline int is_imx1_i2c(struct imx_i2c_struct *i2c_imx)
273 {
274 return i2c_imx->hwdata->devtype == IMX1_I2C;
275 }
276
277 static inline void imx_i2c_write_reg(unsigned int val,
278 struct imx_i2c_struct *i2c_imx, unsigned int reg)
279 {
280 writeb(val, i2c_imx->base + (reg << i2c_imx->hwdata->regshift));
281 }
282
283 static inline unsigned char imx_i2c_read_reg(struct imx_i2c_struct *i2c_imx,
284 unsigned int reg)
285 {
286 return readb(i2c_imx->base + (reg << i2c_imx->hwdata->regshift));
287 }
288
289 /* Functions for DMA support */
290 static void i2c_imx_dma_request(struct imx_i2c_struct *i2c_imx,
291 dma_addr_t phy_addr)
292 {
293 struct imx_i2c_dma *dma;
294 struct dma_slave_config dma_sconfig;
295 struct device *dev = &i2c_imx->adapter.dev;
296 int ret;
297
298 dma = devm_kzalloc(dev, sizeof(*dma), GFP_KERNEL);
299 if (!dma)
300 return;
301
302 dma->chan_tx = dma_request_slave_channel(dev, "tx");
303 if (!dma->chan_tx) {
304 dev_dbg(dev, "can't request DMA tx channel\n");
305 goto fail_al;
306 }
307
308 dma_sconfig.dst_addr = phy_addr +
309 (IMX_I2C_I2DR << i2c_imx->hwdata->regshift);
310 dma_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
311 dma_sconfig.dst_maxburst = 1;
312 dma_sconfig.direction = DMA_MEM_TO_DEV;
313 ret = dmaengine_slave_config(dma->chan_tx, &dma_sconfig);
314 if (ret < 0) {
315 dev_dbg(dev, "can't configure tx channel\n");
316 goto fail_tx;
317 }
318
319 dma->chan_rx = dma_request_slave_channel(dev, "rx");
320 if (!dma->chan_rx) {
321 dev_dbg(dev, "can't request DMA rx channel\n");
322 goto fail_tx;
323 }
324
325 dma_sconfig.src_addr = phy_addr +
326 (IMX_I2C_I2DR << i2c_imx->hwdata->regshift);
327 dma_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
328 dma_sconfig.src_maxburst = 1;
329 dma_sconfig.direction = DMA_DEV_TO_MEM;
330 ret = dmaengine_slave_config(dma->chan_rx, &dma_sconfig);
331 if (ret < 0) {
332 dev_dbg(dev, "can't configure rx channel\n");
333 goto fail_rx;
334 }
335
336 i2c_imx->dma = dma;
337 init_completion(&dma->cmd_complete);
338 dev_info(dev, "using %s (tx) and %s (rx) for DMA transfers\n",
339 dma_chan_name(dma->chan_tx), dma_chan_name(dma->chan_rx));
340
341 return;
342
343 fail_rx:
344 dma_release_channel(dma->chan_rx);
345 fail_tx:
346 dma_release_channel(dma->chan_tx);
347 fail_al:
348 devm_kfree(dev, dma);
349 dev_info(dev, "can't use DMA\n");
350 }
351
352 static void i2c_imx_dma_callback(void *arg)
353 {
354 struct imx_i2c_struct *i2c_imx = (struct imx_i2c_struct *)arg;
355 struct imx_i2c_dma *dma = i2c_imx->dma;
356
357 dma_unmap_single(dma->chan_using->device->dev, dma->dma_buf,
358 dma->dma_len, dma->dma_data_dir);
359 complete(&dma->cmd_complete);
360 }
361
362 static int i2c_imx_dma_xfer(struct imx_i2c_struct *i2c_imx,
363 struct i2c_msg *msgs)
364 {
365 struct imx_i2c_dma *dma = i2c_imx->dma;
366 struct dma_async_tx_descriptor *txdesc;
367 struct device *dev = &i2c_imx->adapter.dev;
368 struct device *chan_dev = dma->chan_using->device->dev;
369
370 dma->dma_buf = dma_map_single(chan_dev, msgs->buf,
371 dma->dma_len, dma->dma_data_dir);
372 if (dma_mapping_error(chan_dev, dma->dma_buf)) {
373 dev_err(dev, "DMA mapping failed\n");
374 goto err_map;
375 }
376
377 txdesc = dmaengine_prep_slave_single(dma->chan_using, dma->dma_buf,
378 dma->dma_len, dma->dma_transfer_dir,
379 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
380 if (!txdesc) {
381 dev_err(dev, "Not able to get desc for DMA xfer\n");
382 goto err_desc;
383 }
384
385 txdesc->callback = i2c_imx_dma_callback;
386 txdesc->callback_param = i2c_imx;
387 if (dma_submit_error(dmaengine_submit(txdesc))) {
388 dev_err(dev, "DMA submit failed\n");
389 goto err_submit;
390 }
391
392 dma_async_issue_pending(dma->chan_using);
393 return 0;
394
395 err_submit:
396 err_desc:
397 dma_unmap_single(chan_dev, dma->dma_buf,
398 dma->dma_len, dma->dma_data_dir);
399 err_map:
400 return -EINVAL;
401 }
402
403 static void i2c_imx_dma_free(struct imx_i2c_struct *i2c_imx)
404 {
405 struct imx_i2c_dma *dma = i2c_imx->dma;
406
407 dma->dma_buf = 0;
408 dma->dma_len = 0;
409
410 dma_release_channel(dma->chan_tx);
411 dma->chan_tx = NULL;
412
413 dma_release_channel(dma->chan_rx);
414 dma->chan_rx = NULL;
415
416 dma->chan_using = NULL;
417 }
418
419 /** Functions for IMX I2C adapter driver ***************************************
420 *******************************************************************************/
421
422 static int i2c_imx_bus_busy(struct imx_i2c_struct *i2c_imx, int for_busy)
423 {
424 unsigned long orig_jiffies = jiffies;
425 unsigned int temp;
426
427 dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__);
428
429 while (1) {
430 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR);
431
432 /* check for arbitration lost */
433 if (temp & I2SR_IAL) {
434 temp &= ~I2SR_IAL;
435 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2SR);
436 return -EAGAIN;
437 }
438
439 if (for_busy && (temp & I2SR_IBB))
440 break;
441 if (!for_busy && !(temp & I2SR_IBB))
442 break;
443 if (time_after(jiffies, orig_jiffies + msecs_to_jiffies(500))) {
444 dev_dbg(&i2c_imx->adapter.dev,
445 "<%s> I2C bus is busy\n", __func__);
446 return -ETIMEDOUT;
447 }
448 schedule();
449 }
450
451 return 0;
452 }
453
454 static int i2c_imx_trx_complete(struct imx_i2c_struct *i2c_imx)
455 {
456 wait_event_timeout(i2c_imx->queue, i2c_imx->i2csr & I2SR_IIF, HZ / 10);
457
458 if (unlikely(!(i2c_imx->i2csr & I2SR_IIF))) {
459 dev_dbg(&i2c_imx->adapter.dev, "<%s> Timeout\n", __func__);
460 return -ETIMEDOUT;
461 }
462 dev_dbg(&i2c_imx->adapter.dev, "<%s> TRX complete\n", __func__);
463 i2c_imx->i2csr = 0;
464 return 0;
465 }
466
467 static int i2c_imx_acked(struct imx_i2c_struct *i2c_imx)
468 {
469 if (imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR) & I2SR_RXAK) {
470 dev_dbg(&i2c_imx->adapter.dev, "<%s> No ACK\n", __func__);
471 return -ENXIO; /* No ACK */
472 }
473
474 dev_dbg(&i2c_imx->adapter.dev, "<%s> ACK received\n", __func__);
475 return 0;
476 }
477
478 static void i2c_imx_set_clk(struct imx_i2c_struct *i2c_imx)
479 {
480 struct imx_i2c_clk_pair *i2c_clk_div = i2c_imx->hwdata->clk_div;
481 unsigned int i2c_clk_rate;
482 unsigned int div;
483 int i;
484
485 /* Divider value calculation */
486 i2c_clk_rate = clk_get_rate(i2c_imx->clk);
487 if (i2c_imx->cur_clk == i2c_clk_rate)
488 return;
489
490 i2c_imx->cur_clk = i2c_clk_rate;
491
492 div = (i2c_clk_rate + i2c_imx->bitrate - 1) / i2c_imx->bitrate;
493 if (div < i2c_clk_div[0].div)
494 i = 0;
495 else if (div > i2c_clk_div[i2c_imx->hwdata->ndivs - 1].div)
496 i = i2c_imx->hwdata->ndivs - 1;
497 else
498 for (i = 0; i2c_clk_div[i].div < div; i++)
499 ;
500
501 /* Store divider value */
502 i2c_imx->ifdr = i2c_clk_div[i].val;
503
504 /*
505 * There dummy delay is calculated.
506 * It should be about one I2C clock period long.
507 * This delay is used in I2C bus disable function
508 * to fix chip hardware bug.
509 */
510 i2c_imx->disable_delay = (500000U * i2c_clk_div[i].div
511 + (i2c_clk_rate / 2) - 1) / (i2c_clk_rate / 2);
512
513 #ifdef CONFIG_I2C_DEBUG_BUS
514 dev_dbg(&i2c_imx->adapter.dev, "I2C_CLK=%d, REQ DIV=%d\n",
515 i2c_clk_rate, div);
516 dev_dbg(&i2c_imx->adapter.dev, "IFDR[IC]=0x%x, REAL DIV=%d\n",
517 i2c_clk_div[i].val, i2c_clk_div[i].div);
518 #endif
519 }
520
521 static int i2c_imx_start(struct imx_i2c_struct *i2c_imx)
522 {
523 unsigned int temp = 0;
524 int result;
525
526 dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__);
527
528 i2c_imx_set_clk(i2c_imx);
529
530 result = clk_prepare_enable(i2c_imx->clk);
531 if (result)
532 return result;
533 imx_i2c_write_reg(i2c_imx->ifdr, i2c_imx, IMX_I2C_IFDR);
534 /* Enable I2C controller */
535 imx_i2c_write_reg(i2c_imx->hwdata->i2sr_clr_opcode, i2c_imx, IMX_I2C_I2SR);
536 imx_i2c_write_reg(i2c_imx->hwdata->i2cr_ien_opcode, i2c_imx, IMX_I2C_I2CR);
537
538 /* Wait controller to be stable */
539 udelay(50);
540
541 /* Start I2C transaction */
542 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
543 temp |= I2CR_MSTA;
544 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
545 result = i2c_imx_bus_busy(i2c_imx, 1);
546 if (result)
547 return result;
548 i2c_imx->stopped = 0;
549
550 temp |= I2CR_IIEN | I2CR_MTX | I2CR_TXAK;
551 temp &= ~I2CR_DMAEN;
552 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
553 return result;
554 }
555
556 static void i2c_imx_stop(struct imx_i2c_struct *i2c_imx)
557 {
558 unsigned int temp = 0;
559
560 if (!i2c_imx->stopped) {
561 /* Stop I2C transaction */
562 dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__);
563 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
564 temp &= ~(I2CR_MSTA | I2CR_MTX);
565 if (i2c_imx->dma)
566 temp &= ~I2CR_DMAEN;
567 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
568 }
569 if (is_imx1_i2c(i2c_imx)) {
570 /*
571 * This delay caused by an i.MXL hardware bug.
572 * If no (or too short) delay, no "STOP" bit will be generated.
573 */
574 udelay(i2c_imx->disable_delay);
575 }
576
577 if (!i2c_imx->stopped) {
578 i2c_imx_bus_busy(i2c_imx, 0);
579 i2c_imx->stopped = 1;
580 }
581
582 /* Disable I2C controller */
583 temp = i2c_imx->hwdata->i2cr_ien_opcode ^ I2CR_IEN,
584 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
585 clk_disable_unprepare(i2c_imx->clk);
586 }
587
588 static irqreturn_t i2c_imx_isr(int irq, void *dev_id)
589 {
590 struct imx_i2c_struct *i2c_imx = dev_id;
591 unsigned int temp;
592
593 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR);
594 if (temp & I2SR_IIF) {
595 /* save status register */
596 i2c_imx->i2csr = temp;
597 temp &= ~I2SR_IIF;
598 temp |= (i2c_imx->hwdata->i2sr_clr_opcode & I2SR_IIF);
599 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2SR);
600 wake_up(&i2c_imx->queue);
601 return IRQ_HANDLED;
602 }
603
604 return IRQ_NONE;
605 }
606
607 static int i2c_imx_dma_write(struct imx_i2c_struct *i2c_imx,
608 struct i2c_msg *msgs)
609 {
610 int result;
611 unsigned long time_left;
612 unsigned int temp = 0;
613 unsigned long orig_jiffies = jiffies;
614 struct imx_i2c_dma *dma = i2c_imx->dma;
615 struct device *dev = &i2c_imx->adapter.dev;
616
617 dma->chan_using = dma->chan_tx;
618 dma->dma_transfer_dir = DMA_MEM_TO_DEV;
619 dma->dma_data_dir = DMA_TO_DEVICE;
620 dma->dma_len = msgs->len - 1;
621 result = i2c_imx_dma_xfer(i2c_imx, msgs);
622 if (result)
623 return result;
624
625 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
626 temp |= I2CR_DMAEN;
627 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
628
629 /*
630 * Write slave address.
631 * The first byte must be transmitted by the CPU.
632 */
633 imx_i2c_write_reg(msgs->addr << 1, i2c_imx, IMX_I2C_I2DR);
634 reinit_completion(&i2c_imx->dma->cmd_complete);
635 time_left = wait_for_completion_timeout(
636 &i2c_imx->dma->cmd_complete,
637 msecs_to_jiffies(DMA_TIMEOUT));
638 if (time_left == 0) {
639 dmaengine_terminate_all(dma->chan_using);
640 return -ETIMEDOUT;
641 }
642
643 /* Waiting for transfer complete. */
644 while (1) {
645 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR);
646 if (temp & I2SR_ICF)
647 break;
648 if (time_after(jiffies, orig_jiffies +
649 msecs_to_jiffies(DMA_TIMEOUT))) {
650 dev_dbg(dev, "<%s> Timeout\n", __func__);
651 return -ETIMEDOUT;
652 }
653 schedule();
654 }
655
656 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
657 temp &= ~I2CR_DMAEN;
658 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
659
660 /* The last data byte must be transferred by the CPU. */
661 imx_i2c_write_reg(msgs->buf[msgs->len-1],
662 i2c_imx, IMX_I2C_I2DR);
663 result = i2c_imx_trx_complete(i2c_imx);
664 if (result)
665 return result;
666
667 return i2c_imx_acked(i2c_imx);
668 }
669
670 static int i2c_imx_dma_read(struct imx_i2c_struct *i2c_imx,
671 struct i2c_msg *msgs, bool is_lastmsg)
672 {
673 int result;
674 unsigned long time_left;
675 unsigned int temp;
676 unsigned long orig_jiffies = jiffies;
677 struct imx_i2c_dma *dma = i2c_imx->dma;
678 struct device *dev = &i2c_imx->adapter.dev;
679
680 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
681 temp |= I2CR_DMAEN;
682 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
683
684 dma->chan_using = dma->chan_rx;
685 dma->dma_transfer_dir = DMA_DEV_TO_MEM;
686 dma->dma_data_dir = DMA_FROM_DEVICE;
687 /* The last two data bytes must be transferred by the CPU. */
688 dma->dma_len = msgs->len - 2;
689 result = i2c_imx_dma_xfer(i2c_imx, msgs);
690 if (result)
691 return result;
692
693 reinit_completion(&i2c_imx->dma->cmd_complete);
694 time_left = wait_for_completion_timeout(
695 &i2c_imx->dma->cmd_complete,
696 msecs_to_jiffies(DMA_TIMEOUT));
697 if (time_left == 0) {
698 dmaengine_terminate_all(dma->chan_using);
699 return -ETIMEDOUT;
700 }
701
702 /* waiting for transfer complete. */
703 while (1) {
704 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR);
705 if (temp & I2SR_ICF)
706 break;
707 if (time_after(jiffies, orig_jiffies +
708 msecs_to_jiffies(DMA_TIMEOUT))) {
709 dev_dbg(dev, "<%s> Timeout\n", __func__);
710 return -ETIMEDOUT;
711 }
712 schedule();
713 }
714
715 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
716 temp &= ~I2CR_DMAEN;
717 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
718
719 /* read n-1 byte data */
720 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
721 temp |= I2CR_TXAK;
722 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
723
724 msgs->buf[msgs->len-2] = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR);
725 /* read n byte data */
726 result = i2c_imx_trx_complete(i2c_imx);
727 if (result)
728 return result;
729
730 if (is_lastmsg) {
731 /*
732 * It must generate STOP before read I2DR to prevent
733 * controller from generating another clock cycle
734 */
735 dev_dbg(dev, "<%s> clear MSTA\n", __func__);
736 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
737 temp &= ~(I2CR_MSTA | I2CR_MTX);
738 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
739 i2c_imx_bus_busy(i2c_imx, 0);
740 i2c_imx->stopped = 1;
741 } else {
742 /*
743 * For i2c master receiver repeat restart operation like:
744 * read -> repeat MSTA -> read/write
745 * The controller must set MTX before read the last byte in
746 * the first read operation, otherwise the first read cost
747 * one extra clock cycle.
748 */
749 temp = readb(i2c_imx->base + IMX_I2C_I2CR);
750 temp |= I2CR_MTX;
751 writeb(temp, i2c_imx->base + IMX_I2C_I2CR);
752 }
753 msgs->buf[msgs->len-1] = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR);
754
755 return 0;
756 }
757
758 static int i2c_imx_write(struct imx_i2c_struct *i2c_imx, struct i2c_msg *msgs)
759 {
760 int i, result;
761
762 dev_dbg(&i2c_imx->adapter.dev, "<%s> write slave address: addr=0x%x\n",
763 __func__, msgs->addr << 1);
764
765 /* write slave address */
766 imx_i2c_write_reg(msgs->addr << 1, i2c_imx, IMX_I2C_I2DR);
767 result = i2c_imx_trx_complete(i2c_imx);
768 if (result)
769 return result;
770 result = i2c_imx_acked(i2c_imx);
771 if (result)
772 return result;
773 dev_dbg(&i2c_imx->adapter.dev, "<%s> write data\n", __func__);
774
775 /* write data */
776 for (i = 0; i < msgs->len; i++) {
777 dev_dbg(&i2c_imx->adapter.dev,
778 "<%s> write byte: B%d=0x%X\n",
779 __func__, i, msgs->buf[i]);
780 imx_i2c_write_reg(msgs->buf[i], i2c_imx, IMX_I2C_I2DR);
781 result = i2c_imx_trx_complete(i2c_imx);
782 if (result)
783 return result;
784 result = i2c_imx_acked(i2c_imx);
785 if (result)
786 return result;
787 }
788 return 0;
789 }
790
791 static int i2c_imx_read(struct imx_i2c_struct *i2c_imx, struct i2c_msg *msgs, bool is_lastmsg)
792 {
793 int i, result;
794 unsigned int temp;
795 int block_data = msgs->flags & I2C_M_RECV_LEN;
796
797 dev_dbg(&i2c_imx->adapter.dev,
798 "<%s> write slave address: addr=0x%x\n",
799 __func__, (msgs->addr << 1) | 0x01);
800
801 /* write slave address */
802 imx_i2c_write_reg((msgs->addr << 1) | 0x01, i2c_imx, IMX_I2C_I2DR);
803 result = i2c_imx_trx_complete(i2c_imx);
804 if (result)
805 return result;
806 result = i2c_imx_acked(i2c_imx);
807 if (result)
808 return result;
809
810 dev_dbg(&i2c_imx->adapter.dev, "<%s> setup bus\n", __func__);
811
812 /* setup bus to read data */
813 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
814 temp &= ~I2CR_MTX;
815
816 /*
817 * Reset the I2CR_TXAK flag initially for SMBus block read since the
818 * length is unknown
819 */
820 if ((msgs->len - 1) || block_data)
821 temp &= ~I2CR_TXAK;
822 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
823 imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR); /* dummy read */
824
825 dev_dbg(&i2c_imx->adapter.dev, "<%s> read data\n", __func__);
826
827 if (i2c_imx->dma && msgs->len >= DMA_THRESHOLD && !block_data)
828 return i2c_imx_dma_read(i2c_imx, msgs, is_lastmsg);
829
830 /* read data */
831 for (i = 0; i < msgs->len; i++) {
832 u8 len = 0;
833
834 result = i2c_imx_trx_complete(i2c_imx);
835 if (result)
836 return result;
837 /*
838 * First byte is the length of remaining packet
839 * in the SMBus block data read. Add it to
840 * msgs->len.
841 */
842 if ((!i) && block_data) {
843 len = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR);
844 if ((len == 0) || (len > I2C_SMBUS_BLOCK_MAX))
845 return -EPROTO;
846 dev_dbg(&i2c_imx->adapter.dev,
847 "<%s> read length: 0x%X\n",
848 __func__, len);
849 msgs->len += len;
850 }
851 if (i == (msgs->len - 1)) {
852 if (is_lastmsg) {
853 /*
854 * It must generate STOP before read I2DR to prevent
855 * controller from generating another clock cycle
856 */
857 dev_dbg(&i2c_imx->adapter.dev,
858 "<%s> clear MSTA\n", __func__);
859 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
860 temp &= ~(I2CR_MSTA | I2CR_MTX);
861 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
862 i2c_imx_bus_busy(i2c_imx, 0);
863 i2c_imx->stopped = 1;
864 } else {
865 /*
866 * For i2c master receiver repeat restart operation like:
867 * read -> repeat MSTA -> read/write
868 * The controller must set MTX before read the last byte in
869 * the first read operation, otherwise the first read cost
870 * one extra clock cycle.
871 */
872 temp = readb(i2c_imx->base + IMX_I2C_I2CR);
873 temp |= I2CR_MTX;
874 writeb(temp, i2c_imx->base + IMX_I2C_I2CR);
875 }
876 } else if (i == (msgs->len - 2)) {
877 dev_dbg(&i2c_imx->adapter.dev,
878 "<%s> set TXAK\n", __func__);
879 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
880 temp |= I2CR_TXAK;
881 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
882 }
883 if ((!i) && block_data)
884 msgs->buf[0] = len;
885 else
886 msgs->buf[i] = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR);
887 dev_dbg(&i2c_imx->adapter.dev,
888 "<%s> read byte: B%d=0x%X\n",
889 __func__, i, msgs->buf[i]);
890 }
891 return 0;
892 }
893
894 static int i2c_imx_xfer(struct i2c_adapter *adapter,
895 struct i2c_msg *msgs, int num)
896 {
897 unsigned int i, temp;
898 int result;
899 bool is_lastmsg = false;
900 struct imx_i2c_struct *i2c_imx = i2c_get_adapdata(adapter);
901
902 dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__);
903
904 /* Start I2C transfer */
905 result = i2c_imx_start(i2c_imx);
906 if (result) {
907 if (i2c_imx->adapter.bus_recovery_info) {
908 i2c_recover_bus(&i2c_imx->adapter);
909 result = i2c_imx_start(i2c_imx);
910 }
911 }
912
913 if (result)
914 goto fail0;
915
916 /* read/write data */
917 for (i = 0; i < num; i++) {
918 if (i == num - 1)
919 is_lastmsg = true;
920
921 if (i) {
922 dev_dbg(&i2c_imx->adapter.dev,
923 "<%s> repeated start\n", __func__);
924 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
925 temp |= I2CR_RSTA;
926 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
927 result = i2c_imx_bus_busy(i2c_imx, 1);
928 if (result)
929 goto fail0;
930 }
931 dev_dbg(&i2c_imx->adapter.dev,
932 "<%s> transfer message: %d\n", __func__, i);
933 /* write/read data */
934 #ifdef CONFIG_I2C_DEBUG_BUS
935 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
936 dev_dbg(&i2c_imx->adapter.dev,
937 "<%s> CONTROL: IEN=%d, IIEN=%d, MSTA=%d, MTX=%d, TXAK=%d, RSTA=%d\n",
938 __func__,
939 (temp & I2CR_IEN ? 1 : 0), (temp & I2CR_IIEN ? 1 : 0),
940 (temp & I2CR_MSTA ? 1 : 0), (temp & I2CR_MTX ? 1 : 0),
941 (temp & I2CR_TXAK ? 1 : 0), (temp & I2CR_RSTA ? 1 : 0));
942 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR);
943 dev_dbg(&i2c_imx->adapter.dev,
944 "<%s> STATUS: ICF=%d, IAAS=%d, IBB=%d, IAL=%d, SRW=%d, IIF=%d, RXAK=%d\n",
945 __func__,
946 (temp & I2SR_ICF ? 1 : 0), (temp & I2SR_IAAS ? 1 : 0),
947 (temp & I2SR_IBB ? 1 : 0), (temp & I2SR_IAL ? 1 : 0),
948 (temp & I2SR_SRW ? 1 : 0), (temp & I2SR_IIF ? 1 : 0),
949 (temp & I2SR_RXAK ? 1 : 0));
950 #endif
951 if (msgs[i].flags & I2C_M_RD)
952 result = i2c_imx_read(i2c_imx, &msgs[i], is_lastmsg);
953 else {
954 if (i2c_imx->dma && msgs[i].len >= DMA_THRESHOLD)
955 result = i2c_imx_dma_write(i2c_imx, &msgs[i]);
956 else
957 result = i2c_imx_write(i2c_imx, &msgs[i]);
958 }
959 if (result)
960 goto fail0;
961 }
962
963 fail0:
964 /* Stop I2C transfer */
965 i2c_imx_stop(i2c_imx);
966
967 dev_dbg(&i2c_imx->adapter.dev, "<%s> exit with: %s: %d\n", __func__,
968 (result < 0) ? "error" : "success msg",
969 (result < 0) ? result : num);
970 return (result < 0) ? result : num;
971 }
972
973 static void i2c_imx_prepare_recovery(struct i2c_adapter *adap)
974 {
975 struct imx_i2c_struct *i2c_imx;
976
977 i2c_imx = container_of(adap, struct imx_i2c_struct, adapter);
978
979 pinctrl_select_state(i2c_imx->pinctrl, i2c_imx->pinctrl_pins_gpio);
980 }
981
982 static void i2c_imx_unprepare_recovery(struct i2c_adapter *adap)
983 {
984 struct imx_i2c_struct *i2c_imx;
985
986 i2c_imx = container_of(adap, struct imx_i2c_struct, adapter);
987
988 pinctrl_select_state(i2c_imx->pinctrl, i2c_imx->pinctrl_pins_default);
989 }
990
991 static void i2c_imx_init_recovery_info(struct imx_i2c_struct *i2c_imx,
992 struct platform_device *pdev)
993 {
994 struct i2c_bus_recovery_info *rinfo = &i2c_imx->rinfo;
995
996 i2c_imx->pinctrl_pins_default = pinctrl_lookup_state(i2c_imx->pinctrl,
997 PINCTRL_STATE_DEFAULT);
998 i2c_imx->pinctrl_pins_gpio = pinctrl_lookup_state(i2c_imx->pinctrl,
999 "gpio");
1000 rinfo->sda_gpio = of_get_named_gpio_flags(pdev->dev.of_node,
1001 "sda-gpios", 0, NULL);
1002 rinfo->scl_gpio = of_get_named_gpio_flags(pdev->dev.of_node,
1003 "scl-gpios", 0, NULL);
1004
1005 if (!gpio_is_valid(rinfo->sda_gpio) ||
1006 !gpio_is_valid(rinfo->scl_gpio) ||
1007 IS_ERR(i2c_imx->pinctrl_pins_default) ||
1008 IS_ERR(i2c_imx->pinctrl_pins_gpio)) {
1009 dev_dbg(&pdev->dev, "recovery information incomplete\n");
1010 return;
1011 }
1012
1013 dev_dbg(&pdev->dev, "using scl-gpio %d and sda-gpio %d for recovery\n",
1014 rinfo->sda_gpio, rinfo->scl_gpio);
1015
1016 rinfo->prepare_recovery = i2c_imx_prepare_recovery;
1017 rinfo->unprepare_recovery = i2c_imx_unprepare_recovery;
1018 rinfo->recover_bus = i2c_generic_gpio_recovery;
1019 i2c_imx->adapter.bus_recovery_info = rinfo;
1020 }
1021
1022 static u32 i2c_imx_func(struct i2c_adapter *adapter)
1023 {
1024 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL
1025 | I2C_FUNC_SMBUS_READ_BLOCK_DATA;
1026 }
1027
1028 static struct i2c_algorithm i2c_imx_algo = {
1029 .master_xfer = i2c_imx_xfer,
1030 .functionality = i2c_imx_func,
1031 };
1032
1033 static int i2c_imx_probe(struct platform_device *pdev)
1034 {
1035 const struct of_device_id *of_id = of_match_device(i2c_imx_dt_ids,
1036 &pdev->dev);
1037 struct imx_i2c_struct *i2c_imx;
1038 struct resource *res;
1039 struct imxi2c_platform_data *pdata = dev_get_platdata(&pdev->dev);
1040 void __iomem *base;
1041 int irq, ret;
1042 dma_addr_t phy_addr;
1043
1044 dev_dbg(&pdev->dev, "<%s>\n", __func__);
1045
1046 irq = platform_get_irq(pdev, 0);
1047 if (irq < 0) {
1048 dev_err(&pdev->dev, "can't get irq number\n");
1049 return irq;
1050 }
1051
1052 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1053 base = devm_ioremap_resource(&pdev->dev, res);
1054 if (IS_ERR(base))
1055 return PTR_ERR(base);
1056
1057 phy_addr = (dma_addr_t)res->start;
1058 i2c_imx = devm_kzalloc(&pdev->dev, sizeof(*i2c_imx), GFP_KERNEL);
1059 if (!i2c_imx)
1060 return -ENOMEM;
1061
1062 if (of_id)
1063 i2c_imx->hwdata = of_id->data;
1064 else
1065 i2c_imx->hwdata = (struct imx_i2c_hwdata *)
1066 platform_get_device_id(pdev)->driver_data;
1067
1068 /* Setup i2c_imx driver structure */
1069 strlcpy(i2c_imx->adapter.name, pdev->name, sizeof(i2c_imx->adapter.name));
1070 i2c_imx->adapter.owner = THIS_MODULE;
1071 i2c_imx->adapter.algo = &i2c_imx_algo;
1072 i2c_imx->adapter.dev.parent = &pdev->dev;
1073 i2c_imx->adapter.nr = pdev->id;
1074 i2c_imx->adapter.dev.of_node = pdev->dev.of_node;
1075 i2c_imx->base = base;
1076
1077 /* Get I2C clock */
1078 i2c_imx->clk = devm_clk_get(&pdev->dev, NULL);
1079 if (IS_ERR(i2c_imx->clk)) {
1080 dev_err(&pdev->dev, "can't get I2C clock\n");
1081 return PTR_ERR(i2c_imx->clk);
1082 }
1083
1084 ret = clk_prepare_enable(i2c_imx->clk);
1085 if (ret) {
1086 dev_err(&pdev->dev, "can't enable I2C clock\n");
1087 return ret;
1088 }
1089
1090 i2c_imx->pinctrl = devm_pinctrl_get(&pdev->dev);
1091 if (IS_ERR(i2c_imx->pinctrl)) {
1092 ret = PTR_ERR(i2c_imx->pinctrl);
1093 goto clk_disable;
1094 }
1095
1096 /* Request IRQ */
1097 ret = devm_request_irq(&pdev->dev, irq, i2c_imx_isr, 0,
1098 pdev->name, i2c_imx);
1099 if (ret) {
1100 dev_err(&pdev->dev, "can't claim irq %d\n", irq);
1101 goto clk_disable;
1102 }
1103
1104 /* Init queue */
1105 init_waitqueue_head(&i2c_imx->queue);
1106
1107 /* Set up adapter data */
1108 i2c_set_adapdata(&i2c_imx->adapter, i2c_imx);
1109
1110 /* Set up clock divider */
1111 i2c_imx->bitrate = IMX_I2C_BIT_RATE;
1112 ret = of_property_read_u32(pdev->dev.of_node,
1113 "clock-frequency", &i2c_imx->bitrate);
1114 if (ret < 0 && pdata && pdata->bitrate)
1115 i2c_imx->bitrate = pdata->bitrate;
1116
1117 /* Set up chip registers to defaults */
1118 imx_i2c_write_reg(i2c_imx->hwdata->i2cr_ien_opcode ^ I2CR_IEN,
1119 i2c_imx, IMX_I2C_I2CR);
1120 imx_i2c_write_reg(i2c_imx->hwdata->i2sr_clr_opcode, i2c_imx, IMX_I2C_I2SR);
1121
1122 i2c_imx_init_recovery_info(i2c_imx, pdev);
1123
1124 /* Add I2C adapter */
1125 ret = i2c_add_numbered_adapter(&i2c_imx->adapter);
1126 if (ret < 0) {
1127 dev_err(&pdev->dev, "registration failed\n");
1128 goto clk_disable;
1129 }
1130
1131 /* Set up platform driver data */
1132 platform_set_drvdata(pdev, i2c_imx);
1133 clk_disable_unprepare(i2c_imx->clk);
1134
1135 dev_dbg(&i2c_imx->adapter.dev, "claimed irq %d\n", irq);
1136 dev_dbg(&i2c_imx->adapter.dev, "device resources: %pR\n", res);
1137 dev_dbg(&i2c_imx->adapter.dev, "adapter name: \"%s\"\n",
1138 i2c_imx->adapter.name);
1139 dev_info(&i2c_imx->adapter.dev, "IMX I2C adapter registered\n");
1140
1141 /* Init DMA config if supported */
1142 i2c_imx_dma_request(i2c_imx, phy_addr);
1143
1144 return 0; /* Return OK */
1145
1146 clk_disable:
1147 clk_disable_unprepare(i2c_imx->clk);
1148 return ret;
1149 }
1150
1151 static int i2c_imx_remove(struct platform_device *pdev)
1152 {
1153 struct imx_i2c_struct *i2c_imx = platform_get_drvdata(pdev);
1154
1155 /* remove adapter */
1156 dev_dbg(&i2c_imx->adapter.dev, "adapter removed\n");
1157 i2c_del_adapter(&i2c_imx->adapter);
1158
1159 if (i2c_imx->dma)
1160 i2c_imx_dma_free(i2c_imx);
1161
1162 /* setup chip registers to defaults */
1163 imx_i2c_write_reg(0, i2c_imx, IMX_I2C_IADR);
1164 imx_i2c_write_reg(0, i2c_imx, IMX_I2C_IFDR);
1165 imx_i2c_write_reg(0, i2c_imx, IMX_I2C_I2CR);
1166 imx_i2c_write_reg(0, i2c_imx, IMX_I2C_I2SR);
1167
1168 return 0;
1169 }
1170
1171 static struct platform_driver i2c_imx_driver = {
1172 .probe = i2c_imx_probe,
1173 .remove = i2c_imx_remove,
1174 .driver = {
1175 .name = DRIVER_NAME,
1176 .of_match_table = i2c_imx_dt_ids,
1177 },
1178 .id_table = imx_i2c_devtype,
1179 };
1180
1181 static int __init i2c_adap_imx_init(void)
1182 {
1183 return platform_driver_register(&i2c_imx_driver);
1184 }
1185 subsys_initcall(i2c_adap_imx_init);
1186
1187 static void __exit i2c_adap_imx_exit(void)
1188 {
1189 platform_driver_unregister(&i2c_imx_driver);
1190 }
1191 module_exit(i2c_adap_imx_exit);
1192
1193 MODULE_LICENSE("GPL");
1194 MODULE_AUTHOR("Darius Augulis");
1195 MODULE_DESCRIPTION("I2C adapter driver for IMX I2C bus");
1196 MODULE_ALIAS("platform:" DRIVER_NAME);
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