2 * (C) Copyright 2003-2004
3 * Humboldt Solutions Ltd, adrian@humboldt.co.uk.
5 * This is a combined i2c adapter and algorithm driver for the
6 * MPC107/Tsi107 PowerPC northbridge and processors that include
7 * the same I2C unit (8240, 8245, 85xx).
11 * This file is licensed under the terms of the GNU General Public
12 * License version 2. This program is licensed "as is" without any
13 * warranty of any kind, whether express or implied.
16 #include <linux/kernel.h>
17 #include <linux/module.h>
18 #include <linux/sched.h>
19 #include <linux/init.h>
20 #include <linux/of_platform.h>
21 #include <linux/of_i2c.h>
24 #include <linux/fsl_devices.h>
25 #include <linux/i2c.h>
26 #include <linux/interrupt.h>
27 #include <linux/delay.h>
29 #define DRV_NAME "mpc-i2c"
31 #define MPC_I2C_FDR 0x04
32 #define MPC_I2C_CR 0x08
33 #define MPC_I2C_SR 0x0c
34 #define MPC_I2C_DR 0x10
35 #define MPC_I2C_DFSRR 0x14
55 wait_queue_head_t queue
;
56 struct i2c_adapter adap
;
61 static __inline__
void writeccr(struct mpc_i2c
*i2c
, u32 x
)
63 writeb(x
, i2c
->base
+ MPC_I2C_CR
);
66 static irqreturn_t
mpc_i2c_isr(int irq
, void *dev_id
)
68 struct mpc_i2c
*i2c
= dev_id
;
69 if (readb(i2c
->base
+ MPC_I2C_SR
) & CSR_MIF
) {
70 /* Read again to allow register to stabilise */
71 i2c
->interrupt
= readb(i2c
->base
+ MPC_I2C_SR
);
72 writeb(0, i2c
->base
+ MPC_I2C_SR
);
78 /* Sometimes 9th clock pulse isn't generated, and slave doesn't release
79 * the bus, because it wants to send ACK.
80 * Following sequence of enabling/disabling and sending start/stop generates
81 * the pulse, so it's all OK.
83 static void mpc_i2c_fixup(struct mpc_i2c
*i2c
)
87 writeccr(i2c
, CCR_MEN
);
89 writeccr(i2c
, CCR_MSTA
| CCR_MTX
);
91 writeccr(i2c
, CCR_MSTA
| CCR_MTX
| CCR_MEN
);
93 writeccr(i2c
, CCR_MEN
);
97 static int i2c_wait(struct mpc_i2c
*i2c
, unsigned timeout
, int writing
)
99 unsigned long orig_jiffies
= jiffies
;
103 if (i2c
->irq
== NO_IRQ
)
105 while (!(readb(i2c
->base
+ MPC_I2C_SR
) & CSR_MIF
)) {
107 if (time_after(jiffies
, orig_jiffies
+ timeout
)) {
108 pr_debug("I2C: timeout\n");
114 x
= readb(i2c
->base
+ MPC_I2C_SR
);
115 writeb(0, i2c
->base
+ MPC_I2C_SR
);
118 result
= wait_event_timeout(i2c
->queue
,
119 (i2c
->interrupt
& CSR_MIF
), timeout
);
121 if (unlikely(!(i2c
->interrupt
& CSR_MIF
))) {
122 pr_debug("I2C: wait timeout\n");
134 if (!(x
& CSR_MCF
)) {
135 pr_debug("I2C: unfinished\n");
140 pr_debug("I2C: MAL\n");
144 if (writing
&& (x
& CSR_RXAK
)) {
145 pr_debug("I2C: No RXAK\n");
147 writeccr(i2c
, CCR_MEN
);
153 static void mpc_i2c_setclock(struct mpc_i2c
*i2c
)
155 /* Set clock and filters */
156 if (i2c
->flags
& FSL_I2C_DEV_SEPARATE_DFSRR
) {
157 writeb(0x31, i2c
->base
+ MPC_I2C_FDR
);
158 writeb(0x10, i2c
->base
+ MPC_I2C_DFSRR
);
159 } else if (i2c
->flags
& FSL_I2C_DEV_CLOCK_5200
)
160 writeb(0x3f, i2c
->base
+ MPC_I2C_FDR
);
162 writel(0x1031, i2c
->base
+ MPC_I2C_FDR
);
165 static void mpc_i2c_start(struct mpc_i2c
*i2c
)
167 /* Clear arbitration */
168 writeb(0, i2c
->base
+ MPC_I2C_SR
);
170 writeccr(i2c
, CCR_MEN
);
173 static void mpc_i2c_stop(struct mpc_i2c
*i2c
)
175 writeccr(i2c
, CCR_MEN
);
178 static int mpc_write(struct mpc_i2c
*i2c
, int target
,
179 const u8
* data
, int length
, int restart
)
182 unsigned timeout
= i2c
->adap
.timeout
;
183 u32 flags
= restart
? CCR_RSTA
: 0;
187 writeccr(i2c
, CCR_MEN
);
188 /* Start as master */
189 writeccr(i2c
, CCR_MIEN
| CCR_MEN
| CCR_MSTA
| CCR_MTX
| flags
);
190 /* Write target byte */
191 writeb((target
<< 1), i2c
->base
+ MPC_I2C_DR
);
193 result
= i2c_wait(i2c
, timeout
, 1);
197 for (i
= 0; i
< length
; i
++) {
198 /* Write data byte */
199 writeb(data
[i
], i2c
->base
+ MPC_I2C_DR
);
201 result
= i2c_wait(i2c
, timeout
, 1);
209 static int mpc_read(struct mpc_i2c
*i2c
, int target
,
210 u8
* data
, int length
, int restart
)
212 unsigned timeout
= i2c
->adap
.timeout
;
214 u32 flags
= restart
? CCR_RSTA
: 0;
218 writeccr(i2c
, CCR_MEN
);
219 /* Switch to read - restart */
220 writeccr(i2c
, CCR_MIEN
| CCR_MEN
| CCR_MSTA
| CCR_MTX
| flags
);
221 /* Write target address byte - this time with the read flag set */
222 writeb((target
<< 1) | 1, i2c
->base
+ MPC_I2C_DR
);
224 result
= i2c_wait(i2c
, timeout
, 1);
230 writeccr(i2c
, CCR_MIEN
| CCR_MEN
| CCR_MSTA
| CCR_TXAK
);
232 writeccr(i2c
, CCR_MIEN
| CCR_MEN
| CCR_MSTA
);
234 readb(i2c
->base
+ MPC_I2C_DR
);
237 for (i
= 0; i
< length
; i
++) {
238 result
= i2c_wait(i2c
, timeout
, 0);
242 /* Generate txack on next to last byte */
244 writeccr(i2c
, CCR_MIEN
| CCR_MEN
| CCR_MSTA
| CCR_TXAK
);
245 /* Generate stop on last byte */
247 writeccr(i2c
, CCR_MIEN
| CCR_MEN
| CCR_TXAK
);
248 data
[i
] = readb(i2c
->base
+ MPC_I2C_DR
);
254 static int mpc_xfer(struct i2c_adapter
*adap
, struct i2c_msg
*msgs
, int num
)
256 struct i2c_msg
*pmsg
;
259 unsigned long orig_jiffies
= jiffies
;
260 struct mpc_i2c
*i2c
= i2c_get_adapdata(adap
);
264 /* Allow bus up to 1s to become not busy */
265 while (readb(i2c
->base
+ MPC_I2C_SR
) & CSR_MBB
) {
266 if (signal_pending(current
)) {
267 pr_debug("I2C: Interrupted\n");
271 if (time_after(jiffies
, orig_jiffies
+ HZ
)) {
272 pr_debug("I2C: timeout\n");
273 if (readb(i2c
->base
+ MPC_I2C_SR
) ==
274 (CSR_MCF
| CSR_MBB
| CSR_RXAK
))
281 for (i
= 0; ret
>= 0 && i
< num
; i
++) {
283 pr_debug("Doing %s %d bytes to 0x%02x - %d of %d messages\n",
284 pmsg
->flags
& I2C_M_RD
? "read" : "write",
285 pmsg
->len
, pmsg
->addr
, i
+ 1, num
);
286 if (pmsg
->flags
& I2C_M_RD
)
288 mpc_read(i2c
, pmsg
->addr
, pmsg
->buf
, pmsg
->len
, i
);
291 mpc_write(i2c
, pmsg
->addr
, pmsg
->buf
, pmsg
->len
, i
);
294 return (ret
< 0) ? ret
: num
;
297 static u32
mpc_functionality(struct i2c_adapter
*adap
)
299 return I2C_FUNC_I2C
| I2C_FUNC_SMBUS_EMUL
;
302 static const struct i2c_algorithm mpc_algo
= {
303 .master_xfer
= mpc_xfer
,
304 .functionality
= mpc_functionality
,
307 static struct i2c_adapter mpc_ops
= {
308 .owner
= THIS_MODULE
,
309 .name
= "MPC adapter",
314 static int __devinit
fsl_i2c_probe(struct of_device
*op
, const struct of_device_id
*match
)
319 i2c
= kzalloc(sizeof(*i2c
), GFP_KERNEL
);
323 if (of_get_property(op
->node
, "dfsrr", NULL
))
324 i2c
->flags
|= FSL_I2C_DEV_SEPARATE_DFSRR
;
326 if (of_device_is_compatible(op
->node
, "fsl,mpc5200-i2c") ||
327 of_device_is_compatible(op
->node
, "mpc5200-i2c"))
328 i2c
->flags
|= FSL_I2C_DEV_CLOCK_5200
;
330 init_waitqueue_head(&i2c
->queue
);
332 i2c
->base
= of_iomap(op
->node
, 0);
334 printk(KERN_ERR
"i2c-mpc - failed to map controller\n");
339 i2c
->irq
= irq_of_parse_and_map(op
->node
, 0);
340 if (i2c
->irq
!= NO_IRQ
) { /* i2c->irq = NO_IRQ implies polling */
341 result
= request_irq(i2c
->irq
, mpc_i2c_isr
,
342 IRQF_SHARED
, "i2c-mpc", i2c
);
344 printk(KERN_ERR
"i2c-mpc - failed to attach interrupt\n");
349 mpc_i2c_setclock(i2c
);
351 dev_set_drvdata(&op
->dev
, i2c
);
354 i2c_set_adapdata(&i2c
->adap
, i2c
);
355 i2c
->adap
.dev
.parent
= &op
->dev
;
357 result
= i2c_add_adapter(&i2c
->adap
);
359 printk(KERN_ERR
"i2c-mpc - failed to add adapter\n");
362 of_register_i2c_devices(&i2c
->adap
, op
->node
);
367 dev_set_drvdata(&op
->dev
, NULL
);
368 free_irq(i2c
->irq
, i2c
);
370 irq_dispose_mapping(i2c
->irq
);
377 static int __devexit
fsl_i2c_remove(struct of_device
*op
)
379 struct mpc_i2c
*i2c
= dev_get_drvdata(&op
->dev
);
381 i2c_del_adapter(&i2c
->adap
);
382 dev_set_drvdata(&op
->dev
, NULL
);
384 if (i2c
->irq
!= NO_IRQ
)
385 free_irq(i2c
->irq
, i2c
);
387 irq_dispose_mapping(i2c
->irq
);
393 static const struct of_device_id mpc_i2c_of_match
[] = {
394 {.compatible
= "fsl-i2c",},
397 MODULE_DEVICE_TABLE(of
, mpc_i2c_of_match
);
400 /* Structure for a device driver */
401 static struct of_platform_driver mpc_i2c_driver
= {
402 .match_table
= mpc_i2c_of_match
,
403 .probe
= fsl_i2c_probe
,
404 .remove
= __devexit_p(fsl_i2c_remove
),
406 .owner
= THIS_MODULE
,
411 static int __init
fsl_i2c_init(void)
415 rv
= of_register_platform_driver(&mpc_i2c_driver
);
417 printk(KERN_ERR DRV_NAME
418 " of_register_platform_driver failed (%i)\n", rv
);
422 static void __exit
fsl_i2c_exit(void)
424 of_unregister_platform_driver(&mpc_i2c_driver
);
427 module_init(fsl_i2c_init
);
428 module_exit(fsl_i2c_exit
);
430 MODULE_AUTHOR("Adrian Cox <adrian@humboldt.co.uk>");
432 ("I2C-Bus adapter for MPC107 bridge and MPC824x/85xx/52xx processors");
433 MODULE_LICENSE("GPL");