drivers/i2c/busses/i2c-mt65xx.c

   1 /*
   2  * Copyright (c) 2014 MediaTek Inc.
   3  * Author: Xudong Chen <xudong.chen@mediatek.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  */
  14
  15 #include <linux/clk.h>
  16 #include <linux/completion.h>
  17 #include <linux/delay.h>
  18 #include <linux/device.h>
  19 #include <linux/dma-mapping.h>
  20 #include <linux/err.h>
  21 #include <linux/errno.h>
  22 #include <linux/i2c.h>
  23 #include <linux/init.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/io.h>
  26 #include <linux/kernel.h>
  27 #include <linux/mm.h>
  28 #include <linux/module.h>
  29 #include <linux/of_address.h>
  30 #include <linux/of_irq.h>
  31 #include <linux/platform_device.h>
  32 #include <linux/scatterlist.h>
  33 #include <linux/sched.h>
  34 #include <linux/slab.h>
  35
  36 #define I2C_RS_TRANSFER                 (1 << 4)
  37 #define I2C_HS_NACKERR                  (1 << 2)
  38 #define I2C_ACKERR                      (1 << 1)
  39 #define I2C_TRANSAC_COMP                (1 << 0)
  40 #define I2C_TRANSAC_START               (1 << 0)
  41 #define I2C_RS_MUL_CNFG                 (1 << 15)
  42 #define I2C_RS_MUL_TRIG                 (1 << 14)
  43 #define I2C_DCM_DISABLE                 0x0000
  44 #define I2C_IO_CONFIG_OPEN_DRAIN        0x0003
  45 #define I2C_IO_CONFIG_PUSH_PULL         0x0000
  46 #define I2C_SOFT_RST                    0x0001
  47 #define I2C_FIFO_ADDR_CLR               0x0001
  48 #define I2C_DELAY_LEN                   0x0002
  49 #define I2C_ST_START_CON                0x8001
  50 #define I2C_FS_START_CON                0x1800
  51 #define I2C_TIME_CLR_VALUE              0x0000
  52 #define I2C_TIME_DEFAULT_VALUE          0x0003
  53 #define I2C_FS_TIME_INIT_VALUE          0x1303
  54 #define I2C_WRRD_TRANAC_VALUE           0x0002
  55 #define I2C_RD_TRANAC_VALUE             0x0001
  56
  57 #define I2C_DMA_CON_TX                  0x0000
  58 #define I2C_DMA_CON_RX                  0x0001
  59 #define I2C_DMA_START_EN                0x0001
  60 #define I2C_DMA_INT_FLAG_NONE           0x0000
  61 #define I2C_DMA_CLR_FLAG                0x0000
  62 #define I2C_DMA_HARD_RST                0x0002
  63
  64 #define I2C_DEFAULT_SPEED               100000  /* hz */
  65 #define MAX_FS_MODE_SPEED               400000
  66 #define MAX_HS_MODE_SPEED               3400000
  67 #define MAX_SAMPLE_CNT_DIV              8
  68 #define MAX_STEP_CNT_DIV                64
  69 #define MAX_HS_STEP_CNT_DIV             8
  70
  71 #define I2C_CONTROL_RS                  (0x1 << 1)
  72 #define I2C_CONTROL_DMA_EN              (0x1 << 2)
  73 #define I2C_CONTROL_CLK_EXT_EN          (0x1 << 3)
  74 #define I2C_CONTROL_DIR_CHANGE          (0x1 << 4)
  75 #define I2C_CONTROL_ACKERR_DET_EN       (0x1 << 5)
  76 #define I2C_CONTROL_TRANSFER_LEN_CHANGE (0x1 << 6)
  77 #define I2C_CONTROL_WRAPPER             (0x1 << 0)
  78
  79 #define I2C_DRV_NAME            "i2c-mt65xx"
  80
  81 enum DMA_REGS_OFFSET {
  82         OFFSET_INT_FLAG = 0x0,
  83         OFFSET_INT_EN = 0x04,
  84         OFFSET_EN = 0x08,
  85         OFFSET_RST = 0x0c,
  86         OFFSET_CON = 0x18,
  87         OFFSET_TX_MEM_ADDR = 0x1c,
  88         OFFSET_RX_MEM_ADDR = 0x20,
  89         OFFSET_TX_LEN = 0x24,
  90         OFFSET_RX_LEN = 0x28,
  91 };
  92
  93 enum i2c_trans_st_rs {
  94         I2C_TRANS_STOP = 0,
  95         I2C_TRANS_REPEATED_START,
  96 };
  97
  98 enum mtk_trans_op {
  99         I2C_MASTER_WR = 1,
 100         I2C_MASTER_RD,
 101         I2C_MASTER_WRRD,
 102 };
 103
 104 enum I2C_REGS_OFFSET {
 105         OFFSET_DATA_PORT = 0x0,
 106         OFFSET_SLAVE_ADDR = 0x04,
 107         OFFSET_INTR_MASK = 0x08,
 108         OFFSET_INTR_STAT = 0x0c,
 109         OFFSET_CONTROL = 0x10,
 110         OFFSET_TRANSFER_LEN = 0x14,
 111         OFFSET_TRANSAC_LEN = 0x18,
 112         OFFSET_DELAY_LEN = 0x1c,
 113         OFFSET_TIMING = 0x20,
 114         OFFSET_START = 0x24,
 115         OFFSET_EXT_CONF = 0x28,
 116         OFFSET_FIFO_STAT = 0x30,
 117         OFFSET_FIFO_THRESH = 0x34,
 118         OFFSET_FIFO_ADDR_CLR = 0x38,
 119         OFFSET_IO_CONFIG = 0x40,
 120         OFFSET_RSV_DEBUG = 0x44,
 121         OFFSET_HS = 0x48,
 122         OFFSET_SOFTRESET = 0x50,
 123         OFFSET_DCM_EN = 0x54,
 124         OFFSET_PATH_DIR = 0x60,
 125         OFFSET_DEBUGSTAT = 0x64,
 126         OFFSET_DEBUGCTRL = 0x68,
 127         OFFSET_TRANSFER_LEN_AUX = 0x6c,
 128 };
 129
 130 struct mtk_i2c_compatible {
 131         const struct i2c_adapter_quirks *quirks;
 132         unsigned char pmic_i2c: 1;
 133         unsigned char dcm: 1;
 134         unsigned char auto_restart: 1;
 135 };
 136
 137 struct mtk_i2c {
 138         struct i2c_adapter adap;        /* i2c host adapter */
 139         struct device *dev;
 140         struct completion msg_complete;
 141
 142         /* set in i2c probe */
 143         void __iomem *base;             /* i2c base addr */
 144         void __iomem *pdmabase;         /* dma base address*/
 145         struct clk *clk_main;           /* main clock for i2c bus */
 146         struct clk *clk_dma;            /* DMA clock for i2c via DMA */
 147         struct clk *clk_pmic;           /* PMIC clock for i2c from PMIC */
 148         bool have_pmic;                 /* can use i2c pins from PMIC */
 149         bool use_push_pull;             /* IO config push-pull mode */
 150
 151         u16 irq_stat;                   /* interrupt status */
 152         unsigned int speed_hz;          /* The speed in transfer */
 153         enum mtk_trans_op op;
 154         u16 timing_reg;
 155         u16 high_speed_reg;
 156         const struct mtk_i2c_compatible *dev_comp;
 157 };
 158
 159 static const struct i2c_adapter_quirks mt6577_i2c_quirks = {
 160         .flags = I2C_AQ_COMB_WRITE_THEN_READ,
 161         .max_num_msgs = 1,
 162         .max_write_len = 255,
 163         .max_read_len = 255,
 164         .max_comb_1st_msg_len = 255,
 165         .max_comb_2nd_msg_len = 31,
 166 };
 167
 168 static const struct i2c_adapter_quirks mt8173_i2c_quirks = {
 169         .max_num_msgs = 65535,
 170         .max_write_len = 65535,
 171         .max_read_len = 65535,
 172         .max_comb_1st_msg_len = 65535,
 173         .max_comb_2nd_msg_len = 65535,
 174 };
 175
 176 static const struct mtk_i2c_compatible mt6577_compat = {
 177         .quirks = &mt6577_i2c_quirks,
 178         .pmic_i2c = 0,
 179         .dcm = 1,
 180         .auto_restart = 0,
 181 };
 182
 183 static const struct mtk_i2c_compatible mt6589_compat = {
 184         .quirks = &mt6577_i2c_quirks,
 185         .pmic_i2c = 1,
 186         .dcm = 0,
 187         .auto_restart = 0,
 188 };
 189
 190 static const struct mtk_i2c_compatible mt8173_compat = {
 191         .quirks = &mt8173_i2c_quirks,
 192         .pmic_i2c = 0,
 193         .dcm = 1,
 194         .auto_restart = 1,
 195 };
 196
 197 static const struct of_device_id mtk_i2c_of_match[] = {
 198         { .compatible = "mediatek,mt6577-i2c", .data = &mt6577_compat },
 199         { .compatible = "mediatek,mt6589-i2c", .data = &mt6589_compat },
 200         { .compatible = "mediatek,mt8173-i2c", .data = &mt8173_compat },
 201         {}
 202 };
 203 MODULE_DEVICE_TABLE(of, mtk_i2c_of_match);
 204
 205 static int mtk_i2c_clock_enable(struct mtk_i2c *i2c)
 206 {
 207         int ret;
 208
 209         ret = clk_prepare_enable(i2c->clk_dma);
 210         if (ret)
 211                 return ret;
 212
 213         ret = clk_prepare_enable(i2c->clk_main);
 214         if (ret)
 215                 goto err_main;
 216
 217         if (i2c->have_pmic) {
 218                 ret = clk_prepare_enable(i2c->clk_pmic);
 219                 if (ret)
 220                         goto err_pmic;
 221         }
 222         return 0;
 223
 224 err_pmic:
 225         clk_disable_unprepare(i2c->clk_main);
 226 err_main:
 227         clk_disable_unprepare(i2c->clk_dma);
 228
 229         return ret;
 230 }
 231
 232 static void mtk_i2c_clock_disable(struct mtk_i2c *i2c)
 233 {
 234         if (i2c->have_pmic)
 235                 clk_disable_unprepare(i2c->clk_pmic);
 236
 237         clk_disable_unprepare(i2c->clk_main);
 238         clk_disable_unprepare(i2c->clk_dma);
 239 }
 240
 241 static void mtk_i2c_init_hw(struct mtk_i2c *i2c)
 242 {
 243         u16 control_reg;
 244
 245         writew(I2C_SOFT_RST, i2c->base + OFFSET_SOFTRESET);
 246
 247         /* Set ioconfig */
 248         if (i2c->use_push_pull)
 249                 writew(I2C_IO_CONFIG_PUSH_PULL, i2c->base + OFFSET_IO_CONFIG);
 250         else
 251                 writew(I2C_IO_CONFIG_OPEN_DRAIN, i2c->base + OFFSET_IO_CONFIG);
 252
 253         if (i2c->dev_comp->dcm)
 254                 writew(I2C_DCM_DISABLE, i2c->base + OFFSET_DCM_EN);
 255
 256         writew(i2c->timing_reg, i2c->base + OFFSET_TIMING);
 257         writew(i2c->high_speed_reg, i2c->base + OFFSET_HS);
 258
 259         /* If use i2c pin from PMIC mt6397 side, need set PATH_DIR first */
 260         if (i2c->have_pmic)
 261                 writew(I2C_CONTROL_WRAPPER, i2c->base + OFFSET_PATH_DIR);
 262
 263         control_reg = I2C_CONTROL_ACKERR_DET_EN |
 264                       I2C_CONTROL_CLK_EXT_EN | I2C_CONTROL_DMA_EN;
 265         writew(control_reg, i2c->base + OFFSET_CONTROL);
 266         writew(I2C_DELAY_LEN, i2c->base + OFFSET_DELAY_LEN);
 267
 268         writel(I2C_DMA_HARD_RST, i2c->pdmabase + OFFSET_RST);
 269         udelay(50);
 270         writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_RST);
 271 }
 272
 273 /*
 274  * Calculate i2c port speed
 275  *
 276  * Hardware design:
 277  * i2c_bus_freq = parent_clk / (clock_div * 2 * sample_cnt * step_cnt)
 278  * clock_div: fixed in hardware, but may be various in different SoCs
 279  *
 280  * The calculation want to pick the highest bus frequency that is still
 281  * less than or equal to i2c->speed_hz. The calculation try to get
 282  * sample_cnt and step_cn
 283  */
 284 static int mtk_i2c_set_speed(struct mtk_i2c *i2c, unsigned int parent_clk,
 285                              unsigned int clock_div)
 286 {
 287         unsigned int clk_src;
 288         unsigned int step_cnt;
 289         unsigned int sample_cnt;
 290         unsigned int max_step_cnt;
 291         unsigned int target_speed;
 292         unsigned int base_sample_cnt = MAX_SAMPLE_CNT_DIV;
 293         unsigned int base_step_cnt;
 294         unsigned int opt_div;
 295         unsigned int best_mul;
 296         unsigned int cnt_mul;
 297
 298         clk_src = parent_clk / clock_div;
 299         target_speed = i2c->speed_hz;
 300
 301         if (target_speed > MAX_HS_MODE_SPEED)
 302                 target_speed = MAX_HS_MODE_SPEED;
 303
 304         if (target_speed > MAX_FS_MODE_SPEED)
 305                 max_step_cnt = MAX_HS_STEP_CNT_DIV;
 306         else
 307                 max_step_cnt = MAX_STEP_CNT_DIV;
 308
 309         base_step_cnt = max_step_cnt;
 310         /* Find the best combination */
 311         opt_div = DIV_ROUND_UP(clk_src >> 1, target_speed);
 312         best_mul = MAX_SAMPLE_CNT_DIV * max_step_cnt;
 313
 314         /* Search for the best pair (sample_cnt, step_cnt) with
 315          * 0 < sample_cnt < MAX_SAMPLE_CNT_DIV
 316          * 0 < step_cnt < max_step_cnt
 317          * sample_cnt * step_cnt >= opt_div
 318          * optimizing for sample_cnt * step_cnt being minimal
 319          */
 320         for (sample_cnt = 1; sample_cnt <= MAX_SAMPLE_CNT_DIV; sample_cnt++) {
 321                 step_cnt = DIV_ROUND_UP(opt_div, sample_cnt);
 322                 cnt_mul = step_cnt * sample_cnt;
 323                 if (step_cnt > max_step_cnt)
 324                         continue;
 325
 326                 if (cnt_mul < best_mul) {
 327                         best_mul = cnt_mul;
 328                         base_sample_cnt = sample_cnt;
 329                         base_step_cnt = step_cnt;
 330                         if (best_mul == opt_div)
 331                                 break;
 332                 }
 333         }
 334
 335         sample_cnt = base_sample_cnt;
 336         step_cnt = base_step_cnt;
 337
 338         if ((clk_src / (2 * sample_cnt * step_cnt)) > target_speed) {
 339                 /* In this case, hardware can't support such
 340                  * low i2c_bus_freq
 341                  */
 342                 dev_dbg(i2c->dev, "Unsupported speed (%uhz)\n", target_speed);
 343                 return -EINVAL;
 344         }
 345
 346         step_cnt--;
 347         sample_cnt--;
 348
 349         if (target_speed > MAX_FS_MODE_SPEED) {
 350                 /* Set the high speed mode register */
 351                 i2c->timing_reg = I2C_FS_TIME_INIT_VALUE;
 352                 i2c->high_speed_reg = I2C_TIME_DEFAULT_VALUE |
 353                         (sample_cnt << 12) | (step_cnt << 8);
 354         } else {
 355                 i2c->timing_reg = (sample_cnt << 8) | (step_cnt << 0);
 356                 /* Disable the high speed transaction */
 357                 i2c->high_speed_reg = I2C_TIME_CLR_VALUE;
 358         }
 359
 360         return 0;
 361 }
 362
 363 static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct i2c_msg *msgs,
 364                                int num, int left_num)
 365 {
 366         u16 addr_reg;
 367         u16 start_reg;
 368         u16 control_reg;
 369         u16 restart_flag = 0;
 370         dma_addr_t rpaddr = 0;
 371         dma_addr_t wpaddr = 0;
 372         int ret;
 373
 374         i2c->irq_stat = 0;
 375
 376         if (i2c->dev_comp->auto_restart)
 377                 restart_flag = I2C_RS_TRANSFER;
 378
 379         reinit_completion(&i2c->msg_complete);
 380
 381         control_reg = readw(i2c->base + OFFSET_CONTROL) &
 382                         ~(I2C_CONTROL_DIR_CHANGE | I2C_CONTROL_RS);
 383         if ((i2c->speed_hz > 400000) || (left_num >= 1))
 384                 control_reg |= I2C_CONTROL_RS;
 385
 386         if (i2c->op == I2C_MASTER_WRRD)
 387                 control_reg |= I2C_CONTROL_DIR_CHANGE | I2C_CONTROL_RS;
 388
 389         writew(control_reg, i2c->base + OFFSET_CONTROL);
 390
 391         /* set start condition */
 392         if (i2c->speed_hz <= 100000)
 393                 writew(I2C_ST_START_CON, i2c->base + OFFSET_EXT_CONF);
 394         else
 395                 writew(I2C_FS_START_CON, i2c->base + OFFSET_EXT_CONF);
 396
 397         addr_reg = msgs->addr << 1;
 398         if (i2c->op == I2C_MASTER_RD)
 399                 addr_reg |= 0x1;
 400
 401         writew(addr_reg, i2c->base + OFFSET_SLAVE_ADDR);
 402
 403         /* Clear interrupt status */
 404         writew(restart_flag | I2C_HS_NACKERR | I2C_ACKERR |
 405                I2C_TRANSAC_COMP, i2c->base + OFFSET_INTR_STAT);
 406         writew(I2C_FIFO_ADDR_CLR, i2c->base + OFFSET_FIFO_ADDR_CLR);
 407
 408         /* Enable interrupt */
 409         writew(restart_flag | I2C_HS_NACKERR | I2C_ACKERR |
 410                I2C_TRANSAC_COMP, i2c->base + OFFSET_INTR_MASK);
 411
 412         /* Set transfer and transaction len */
 413         if (i2c->op == I2C_MASTER_WRRD) {
 414                 writew(msgs->len | ((msgs + 1)->len) << 8,
 415                        i2c->base + OFFSET_TRANSFER_LEN);
 416                 writew(I2C_WRRD_TRANAC_VALUE, i2c->base + OFFSET_TRANSAC_LEN);
 417         } else {
 418                 writew(msgs->len, i2c->base + OFFSET_TRANSFER_LEN);
 419                 writew(num, i2c->base + OFFSET_TRANSAC_LEN);
 420         }
 421
 422         /* Prepare buffer data to start transfer */
 423         if (i2c->op == I2C_MASTER_RD) {
 424                 writel(I2C_DMA_INT_FLAG_NONE, i2c->pdmabase + OFFSET_INT_FLAG);
 425                 writel(I2C_DMA_CON_RX, i2c->pdmabase + OFFSET_CON);
 426                 rpaddr = dma_map_single(i2c->dev, msgs->buf,
 427                                         msgs->len, DMA_FROM_DEVICE);
 428                 if (dma_mapping_error(i2c->dev, rpaddr))
 429                         return -ENOMEM;
 430                 writel((u32)rpaddr, i2c->pdmabase + OFFSET_RX_MEM_ADDR);
 431                 writel(msgs->len, i2c->pdmabase + OFFSET_RX_LEN);
 432         } else if (i2c->op == I2C_MASTER_WR) {
 433                 writel(I2C_DMA_INT_FLAG_NONE, i2c->pdmabase + OFFSET_INT_FLAG);
 434                 writel(I2C_DMA_CON_TX, i2c->pdmabase + OFFSET_CON);
 435                 wpaddr = dma_map_single(i2c->dev, msgs->buf,
 436                                         msgs->len, DMA_TO_DEVICE);
 437                 if (dma_mapping_error(i2c->dev, wpaddr))
 438                         return -ENOMEM;
 439                 writel((u32)wpaddr, i2c->pdmabase + OFFSET_TX_MEM_ADDR);
 440                 writel(msgs->len, i2c->pdmabase + OFFSET_TX_LEN);
 441         } else {
 442                 writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_INT_FLAG);
 443                 writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_CON);
 444                 wpaddr = dma_map_single(i2c->dev, msgs->buf,
 445                                         msgs->len, DMA_TO_DEVICE);
 446                 if (dma_mapping_error(i2c->dev, wpaddr))
 447                         return -ENOMEM;
 448                 rpaddr = dma_map_single(i2c->dev, (msgs + 1)->buf,
 449                                         (msgs + 1)->len,
 450                                         DMA_FROM_DEVICE);
 451                 if (dma_mapping_error(i2c->dev, rpaddr)) {
 452                         dma_unmap_single(i2c->dev, wpaddr,
 453                                          msgs->len, DMA_TO_DEVICE);
 454                         return -ENOMEM;
 455                 }
 456                 writel((u32)wpaddr, i2c->pdmabase + OFFSET_TX_MEM_ADDR);
 457                 writel((u32)rpaddr, i2c->pdmabase + OFFSET_RX_MEM_ADDR);
 458                 writel(msgs->len, i2c->pdmabase + OFFSET_TX_LEN);
 459                 writel((msgs + 1)->len, i2c->pdmabase + OFFSET_RX_LEN);
 460         }
 461
 462         writel(I2C_DMA_START_EN, i2c->pdmabase + OFFSET_EN);
 463
 464         if (!i2c->dev_comp->auto_restart) {
 465                 start_reg = I2C_TRANSAC_START;
 466         } else {
 467                 start_reg = I2C_TRANSAC_START | I2C_RS_MUL_TRIG;
 468                 if (left_num >= 1)
 469                         start_reg |= I2C_RS_MUL_CNFG;
 470         }
 471         writew(start_reg, i2c->base + OFFSET_START);
 472
 473         ret = wait_for_completion_timeout(&i2c->msg_complete,
 474                                           i2c->adap.timeout);
 475
 476         /* Clear interrupt mask */
 477         writew(~(restart_flag | I2C_HS_NACKERR | I2C_ACKERR |
 478                I2C_TRANSAC_COMP), i2c->base + OFFSET_INTR_MASK);
 479
 480         if (i2c->op == I2C_MASTER_WR) {
 481                 dma_unmap_single(i2c->dev, wpaddr,
 482                                  msgs->len, DMA_TO_DEVICE);
 483         } else if (i2c->op == I2C_MASTER_RD) {
 484                 dma_unmap_single(i2c->dev, rpaddr,
 485                                  msgs->len, DMA_FROM_DEVICE);
 486         } else {
 487                 dma_unmap_single(i2c->dev, wpaddr, msgs->len,
 488                                  DMA_TO_DEVICE);
 489                 dma_unmap_single(i2c->dev, rpaddr, (msgs + 1)->len,
 490                                  DMA_FROM_DEVICE);
 491         }
 492
 493         if (ret == 0) {
 494                 dev_dbg(i2c->dev, "addr: %x, transfer timeout\n", msgs->addr);
 495                 mtk_i2c_init_hw(i2c);
 496                 return -ETIMEDOUT;
 497         }
 498
 499         completion_done(&i2c->msg_complete);
 500
 501         if (i2c->irq_stat & (I2C_HS_NACKERR | I2C_ACKERR)) {
 502                 dev_dbg(i2c->dev, "addr: %x, transfer ACK error\n", msgs->addr);
 503                 mtk_i2c_init_hw(i2c);
 504                 return -ENXIO;
 505         }
 506
 507         return 0;
 508 }
 509
 510 static int mtk_i2c_transfer(struct i2c_adapter *adap,
 511                             struct i2c_msg msgs[], int num)
 512 {
 513         int ret;
 514         int left_num = num;
 515         struct mtk_i2c *i2c = i2c_get_adapdata(adap);
 516
 517         ret = mtk_i2c_clock_enable(i2c);
 518         if (ret)
 519                 return ret;
 520
 521         while (left_num--) {
 522                 if (!msgs->buf) {
 523                         dev_dbg(i2c->dev, "data buffer is NULL.\n");
 524                         ret = -EINVAL;
 525                         goto err_exit;
 526                 }
 527
 528                 if (msgs->flags & I2C_M_RD)
 529                         i2c->op = I2C_MASTER_RD;
 530                 else
 531                         i2c->op = I2C_MASTER_WR;
 532
 533                 if (!i2c->dev_comp->auto_restart) {
 534                         if (num > 1) {
 535                                 /* combined two messages into one transaction */
 536                                 i2c->op = I2C_MASTER_WRRD;
 537                                 left_num--;
 538                         }
 539                 }
 540
 541                 /* always use DMA mode. */
 542                 ret = mtk_i2c_do_transfer(i2c, msgs, num, left_num);
 543                 if (ret < 0)
 544                         goto err_exit;
 545
 546                 msgs++;
 547         }
 548         /* the return value is number of executed messages */
 549         ret = num;
 550
 551 err_exit:
 552         mtk_i2c_clock_disable(i2c);
 553         return ret;
 554 }
 555
 556 static irqreturn_t mtk_i2c_irq(int irqno, void *dev_id)
 557 {
 558         struct mtk_i2c *i2c = dev_id;
 559         u16 restart_flag = 0;
 560         u16 intr_stat;
 561
 562         if (i2c->dev_comp->auto_restart)
 563                 restart_flag = I2C_RS_TRANSFER;
 564
 565         intr_stat = readw(i2c->base + OFFSET_INTR_STAT);
 566         writew(intr_stat, i2c->base + OFFSET_INTR_STAT);
 567
 568         /*
 569          * when occurs ack error, i2c controller generate two interrupts
 570          * first is the ack error interrupt, then the complete interrupt
 571          * i2c->irq_stat need keep the two interrupt value.
 572          */
 573         i2c->irq_stat |= intr_stat;
 574         if (i2c->irq_stat & (I2C_TRANSAC_COMP | restart_flag))
 575                 complete(&i2c->msg_complete);
 576
 577         return IRQ_HANDLED;
 578 }
 579
 580 static u32 mtk_i2c_functionality(struct i2c_adapter *adap)
 581 {
 582         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
 583 }
 584
 585 static const struct i2c_algorithm mtk_i2c_algorithm = {
 586         .master_xfer = mtk_i2c_transfer,
 587         .functionality = mtk_i2c_functionality,
 588 };
 589
 590 static int mtk_i2c_parse_dt(struct device_node *np, struct mtk_i2c *i2c,
 591                             unsigned int *clk_src_div)
 592 {
 593         int ret;
 594
 595         ret = of_property_read_u32(np, "clock-frequency", &i2c->speed_hz);
 596         if (ret < 0)
 597                 i2c->speed_hz = I2C_DEFAULT_SPEED;
 598
 599         ret = of_property_read_u32(np, "clock-div", clk_src_div);
 600         if (ret < 0)
 601                 return ret;
 602
 603         if (*clk_src_div == 0)
 604                 return -EINVAL;
 605
 606         i2c->have_pmic = of_property_read_bool(np, "mediatek,have-pmic");
 607         i2c->use_push_pull =
 608                 of_property_read_bool(np, "mediatek,use-push-pull");
 609
 610         return 0;
 611 }
 612
 613 static int mtk_i2c_probe(struct platform_device *pdev)
 614 {
 615         const struct of_device_id *of_id;
 616         int ret = 0;
 617         struct mtk_i2c *i2c;
 618         struct clk *clk;
 619         unsigned int clk_src_div;
 620         struct resource *res;
 621         int irq;
 622
 623         i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL);
 624         if (!i2c)
 625                 return -ENOMEM;
 626
 627         ret = mtk_i2c_parse_dt(pdev->dev.of_node, i2c, &clk_src_div);
 628         if (ret)
 629                 return -EINVAL;
 630
 631         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 632         i2c->base = devm_ioremap_resource(&pdev->dev, res);
 633         if (IS_ERR(i2c->base))
 634                 return PTR_ERR(i2c->base);
 635
 636         res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
 637         i2c->pdmabase = devm_ioremap_resource(&pdev->dev, res);
 638         if (IS_ERR(i2c->pdmabase))
 639                 return PTR_ERR(i2c->pdmabase);
 640
 641         irq = platform_get_irq(pdev, 0);
 642         if (irq <= 0)
 643                 return irq;
 644
 645         init_completion(&i2c->msg_complete);
 646
 647         of_id = of_match_node(mtk_i2c_of_match, pdev->dev.of_node);
 648         if (!of_id)
 649                 return -EINVAL;
 650
 651         i2c->dev_comp = of_id->data;
 652         i2c->adap.dev.of_node = pdev->dev.of_node;
 653         i2c->dev = &pdev->dev;
 654         i2c->adap.dev.parent = &pdev->dev;
 655         i2c->adap.owner = THIS_MODULE;
 656         i2c->adap.algo = &mtk_i2c_algorithm;
 657         i2c->adap.quirks = i2c->dev_comp->quirks;
 658         i2c->adap.timeout = 2 * HZ;
 659         i2c->adap.retries = 1;
 660
 661         if (i2c->have_pmic && !i2c->dev_comp->pmic_i2c)
 662                 return -EINVAL;
 663
 664         i2c->clk_main = devm_clk_get(&pdev->dev, "main");
 665         if (IS_ERR(i2c->clk_main)) {
 666                 dev_err(&pdev->dev, "cannot get main clock\n");
 667                 return PTR_ERR(i2c->clk_main);
 668         }
 669
 670         i2c->clk_dma = devm_clk_get(&pdev->dev, "dma");
 671         if (IS_ERR(i2c->clk_dma)) {
 672                 dev_err(&pdev->dev, "cannot get dma clock\n");
 673                 return PTR_ERR(i2c->clk_dma);
 674         }
 675
 676         clk = i2c->clk_main;
 677         if (i2c->have_pmic) {
 678                 i2c->clk_pmic = devm_clk_get(&pdev->dev, "pmic");
 679                 if (IS_ERR(i2c->clk_pmic)) {
 680                         dev_err(&pdev->dev, "cannot get pmic clock\n");
 681                         return PTR_ERR(i2c->clk_pmic);
 682                 }
 683                 clk = i2c->clk_pmic;
 684         }
 685
 686         strlcpy(i2c->adap.name, I2C_DRV_NAME, sizeof(i2c->adap.name));
 687
 688         ret = mtk_i2c_set_speed(i2c, clk_get_rate(clk), clk_src_div);
 689         if (ret) {
 690                 dev_err(&pdev->dev, "Failed to set the speed.\n");
 691                 return -EINVAL;
 692         }
 693
 694         ret = mtk_i2c_clock_enable(i2c);
 695         if (ret) {
 696                 dev_err(&pdev->dev, "clock enable failed!\n");
 697                 return ret;
 698         }
 699         mtk_i2c_init_hw(i2c);
 700         mtk_i2c_clock_disable(i2c);
 701
 702         ret = devm_request_irq(&pdev->dev, irq, mtk_i2c_irq,
 703                                IRQF_TRIGGER_NONE, I2C_DRV_NAME, i2c);
 704         if (ret < 0) {
 705                 dev_err(&pdev->dev,
 706                         "Request I2C IRQ %d fail\n", irq);
 707                 return ret;
 708         }
 709
 710         i2c_set_adapdata(&i2c->adap, i2c);
 711         ret = i2c_add_adapter(&i2c->adap);
 712         if (ret) {
 713                 dev_err(&pdev->dev, "Failed to add i2c bus to i2c core\n");
 714                 return ret;
 715         }
 716
 717         platform_set_drvdata(pdev, i2c);
 718
 719         return 0;
 720 }
 721
 722 static int mtk_i2c_remove(struct platform_device *pdev)
 723 {
 724         struct mtk_i2c *i2c = platform_get_drvdata(pdev);
 725
 726         i2c_del_adapter(&i2c->adap);
 727
 728         return 0;
 729 }
 730
 731 #ifdef CONFIG_PM_SLEEP
 732 static int mtk_i2c_resume(struct device *dev)
 733 {
 734         struct mtk_i2c *i2c = dev_get_drvdata(dev);
 735
 736         mtk_i2c_init_hw(i2c);
 737
 738         return 0;
 739 }
 740 #endif
 741
 742 static const struct dev_pm_ops mtk_i2c_pm = {
 743         SET_SYSTEM_SLEEP_PM_OPS(NULL, mtk_i2c_resume)
 744 };
 745
 746 static struct platform_driver mtk_i2c_driver = {
 747         .probe = mtk_i2c_probe,
 748         .remove = mtk_i2c_remove,
 749         .driver = {
 750                 .name = I2C_DRV_NAME,
 751                 .pm = &mtk_i2c_pm,
 752                 .of_match_table = of_match_ptr(mtk_i2c_of_match),
 753         },
 754 };
 755
 756 module_platform_driver(mtk_i2c_driver);
 757
 758 MODULE_LICENSE("GPL v2");
 759 MODULE_DESCRIPTION("MediaTek I2C Bus Driver");
 760 MODULE_AUTHOR("Xudong Chen <xudong.chen@mediatek.com>");