2 * Copyright (C) 2009 ST-Ericsson SA
3 * Copyright (C) 2009 STMicroelectronics
5 * I2C master mode controller driver, used in Nomadik 8815
8 * Author: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com>
9 * Author: Sachin Verma <sachin.verma@st.com>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2, as
13 * published by the Free Software Foundation.
15 #include <linux/init.h>
16 #include <linux/module.h>
17 #include <linux/platform_device.h>
18 #include <linux/delay.h>
19 #include <linux/slab.h>
20 #include <linux/interrupt.h>
21 #include <linux/i2c.h>
22 #include <linux/err.h>
23 #include <linux/clk.h>
25 #include <linux/regulator/consumer.h>
29 #define DRIVER_NAME "nmk-i2c"
31 /* I2C Controller register offsets */
32 #define I2C_CR (0x000)
33 #define I2C_SCR (0x004)
34 #define I2C_HSMCR (0x008)
35 #define I2C_MCR (0x00C)
36 #define I2C_TFR (0x010)
37 #define I2C_SR (0x014)
38 #define I2C_RFR (0x018)
39 #define I2C_TFTR (0x01C)
40 #define I2C_RFTR (0x020)
41 #define I2C_DMAR (0x024)
42 #define I2C_BRCR (0x028)
43 #define I2C_IMSCR (0x02C)
44 #define I2C_RISR (0x030)
45 #define I2C_MISR (0x034)
46 #define I2C_ICR (0x038)
48 /* Control registers */
49 #define I2C_CR_PE (0x1 << 0) /* Peripheral Enable */
50 #define I2C_CR_OM (0x3 << 1) /* Operating mode */
51 #define I2C_CR_SAM (0x1 << 3) /* Slave addressing mode */
52 #define I2C_CR_SM (0x3 << 4) /* Speed mode */
53 #define I2C_CR_SGCM (0x1 << 6) /* Slave general call mode */
54 #define I2C_CR_FTX (0x1 << 7) /* Flush Transmit */
55 #define I2C_CR_FRX (0x1 << 8) /* Flush Receive */
56 #define I2C_CR_DMA_TX_EN (0x1 << 9) /* DMA Tx enable */
57 #define I2C_CR_DMA_RX_EN (0x1 << 10) /* DMA Rx Enable */
58 #define I2C_CR_DMA_SLE (0x1 << 11) /* DMA sync. logic enable */
59 #define I2C_CR_LM (0x1 << 12) /* Loopback mode */
60 #define I2C_CR_FON (0x3 << 13) /* Filtering on */
61 #define I2C_CR_FS (0x3 << 15) /* Force stop enable */
63 /* Master controller (MCR) register */
64 #define I2C_MCR_OP (0x1 << 0) /* Operation */
65 #define I2C_MCR_A7 (0x7f << 1) /* 7-bit address */
66 #define I2C_MCR_EA10 (0x7 << 8) /* 10-bit Extended address */
67 #define I2C_MCR_SB (0x1 << 11) /* Extended address */
68 #define I2C_MCR_AM (0x3 << 12) /* Address type */
69 #define I2C_MCR_STOP (0x1 << 14) /* Stop condition */
70 #define I2C_MCR_LENGTH (0x7ff << 15) /* Transaction length */
72 /* Status register (SR) */
73 #define I2C_SR_OP (0x3 << 0) /* Operation */
74 #define I2C_SR_STATUS (0x3 << 2) /* controller status */
75 #define I2C_SR_CAUSE (0x7 << 4) /* Abort cause */
76 #define I2C_SR_TYPE (0x3 << 7) /* Receive type */
77 #define I2C_SR_LENGTH (0x7ff << 9) /* Transfer length */
79 /* Interrupt mask set/clear (IMSCR) bits */
80 #define I2C_IT_TXFE (0x1 << 0)
81 #define I2C_IT_TXFNE (0x1 << 1)
82 #define I2C_IT_TXFF (0x1 << 2)
83 #define I2C_IT_TXFOVR (0x1 << 3)
84 #define I2C_IT_RXFE (0x1 << 4)
85 #define I2C_IT_RXFNF (0x1 << 5)
86 #define I2C_IT_RXFF (0x1 << 6)
87 #define I2C_IT_RFSR (0x1 << 16)
88 #define I2C_IT_RFSE (0x1 << 17)
89 #define I2C_IT_WTSR (0x1 << 18)
90 #define I2C_IT_MTD (0x1 << 19)
91 #define I2C_IT_STD (0x1 << 20)
92 #define I2C_IT_MAL (0x1 << 24)
93 #define I2C_IT_BERR (0x1 << 25)
94 #define I2C_IT_MTDWS (0x1 << 28)
96 #define GEN_MASK(val, mask, sb) (((val) << (sb)) & (mask))
98 /* some bits in ICR are reserved */
99 #define I2C_CLEAR_ALL_INTS 0x131f007f
101 /* first three msb bits are reserved */
102 #define IRQ_MASK(mask) (mask & 0x1fffffff)
104 /* maximum threshold value */
105 #define MAX_I2C_FIFO_THRESHOLD 15
107 /* per-transfer delay, required for the hardware to stabilize */
108 #define I2C_DELAY 150
119 I2C_NO_OPERATION
= 0xff,
124 /* controller response timeout in ms */
125 #define I2C_TIMEOUT_MS 2000
128 * struct i2c_nmk_client - client specific data
129 * @slave_adr: 7-bit slave address
130 * @count: no. bytes to be transferred
131 * @buffer: client data buffer
132 * @xfer_bytes: bytes transferred till now
133 * @operation: current I2C operation
135 struct i2c_nmk_client
{
136 unsigned short slave_adr
;
138 unsigned char *buffer
;
139 unsigned long xfer_bytes
;
140 enum i2c_operation operation
;
144 * struct nmk_i2c_dev - private data structure of the controller
145 * @pdev: parent platform device
146 * @adap: corresponding I2C adapter
147 * @irq: interrupt line for the controller
148 * @virtbase: virtual io memory area
149 * @clk: hardware i2c block clock
150 * @cfg: machine provided controller configuration
151 * @cli: holder of client specific data
152 * @stop: stop condition
153 * @xfer_complete: acknowledge completion for a I2C message
154 * @result: controller propogated result
155 * @busy: Busy doing transfer
158 struct platform_device
*pdev
;
159 struct i2c_adapter adap
;
161 void __iomem
*virtbase
;
163 struct nmk_i2c_controller cfg
;
164 struct i2c_nmk_client cli
;
166 struct completion xfer_complete
;
168 struct regulator
*regulator
;
172 /* controller's abort causes */
173 static const char *abort_causes
[] = {
174 "no ack received after address transmission",
175 "no ack received during data phase",
176 "ack received after xmission of master code",
177 "master lost arbitration",
180 "overflow, maxsize is 2047 bytes",
183 static inline void i2c_set_bit(void __iomem
*reg
, u32 mask
)
185 writel(readl(reg
) | mask
, reg
);
188 static inline void i2c_clr_bit(void __iomem
*reg
, u32 mask
)
190 writel(readl(reg
) & ~mask
, reg
);
194 * flush_i2c_fifo() - This function flushes the I2C FIFO
195 * @dev: private data of I2C Driver
197 * This function flushes the I2C Tx and Rx FIFOs. It returns
198 * 0 on successful flushing of FIFO
200 static int flush_i2c_fifo(struct nmk_i2c_dev
*dev
)
202 #define LOOP_ATTEMPTS 10
204 unsigned long timeout
;
207 * flush the transmit and receive FIFO. The flushing
208 * operation takes several cycles before to be completed.
209 * On the completion, the I2C internal logic clears these
210 * bits, until then no one must access Tx, Rx FIFO and
211 * should poll on these bits waiting for the completion.
213 writel((I2C_CR_FTX
| I2C_CR_FRX
), dev
->virtbase
+ I2C_CR
);
215 for (i
= 0; i
< LOOP_ATTEMPTS
; i
++) {
216 timeout
= jiffies
+ msecs_to_jiffies(I2C_TIMEOUT_MS
);
218 while (!time_after(jiffies
, timeout
)) {
219 if ((readl(dev
->virtbase
+ I2C_CR
) &
220 (I2C_CR_FTX
| I2C_CR_FRX
)) == 0)
225 dev_err(&dev
->pdev
->dev
, "flushing operation timed out "
226 "giving up after %d attempts", LOOP_ATTEMPTS
);
232 * disable_all_interrupts() - Disable all interrupts of this I2c Bus
233 * @dev: private data of I2C Driver
235 static void disable_all_interrupts(struct nmk_i2c_dev
*dev
)
237 u32 mask
= IRQ_MASK(0);
238 writel(mask
, dev
->virtbase
+ I2C_IMSCR
);
242 * clear_all_interrupts() - Clear all interrupts of I2C Controller
243 * @dev: private data of I2C Driver
245 static void clear_all_interrupts(struct nmk_i2c_dev
*dev
)
248 mask
= IRQ_MASK(I2C_CLEAR_ALL_INTS
);
249 writel(mask
, dev
->virtbase
+ I2C_ICR
);
253 * init_hw() - initialize the I2C hardware
254 * @dev: private data of I2C Driver
256 static int init_hw(struct nmk_i2c_dev
*dev
)
260 clk_enable(dev
->clk
);
262 stat
= flush_i2c_fifo(dev
);
266 /* disable the controller */
267 i2c_clr_bit(dev
->virtbase
+ I2C_CR
, I2C_CR_PE
);
269 disable_all_interrupts(dev
);
271 clear_all_interrupts(dev
);
273 dev
->cli
.operation
= I2C_NO_OPERATION
;
276 /* TODO: Why disable clocks after init hw? */
277 clk_disable(dev
->clk
);
279 * TODO: What is this delay for?
280 * Must be pretty pointless since the hw block
287 /* enable peripheral, master mode operation */
288 #define DEFAULT_I2C_REG_CR ((1 << 1) | I2C_CR_PE)
291 * load_i2c_mcr_reg() - load the MCR register
292 * @dev: private data of controller
294 static u32
load_i2c_mcr_reg(struct nmk_i2c_dev
*dev
)
298 /* 7-bit address transaction */
299 mcr
|= GEN_MASK(1, I2C_MCR_AM
, 12);
300 mcr
|= GEN_MASK(dev
->cli
.slave_adr
, I2C_MCR_A7
, 1);
302 /* start byte procedure not applied */
303 mcr
|= GEN_MASK(0, I2C_MCR_SB
, 11);
305 /* check the operation, master read/write? */
306 if (dev
->cli
.operation
== I2C_WRITE
)
307 mcr
|= GEN_MASK(I2C_WRITE
, I2C_MCR_OP
, 0);
309 mcr
|= GEN_MASK(I2C_READ
, I2C_MCR_OP
, 0);
311 /* stop or repeated start? */
313 mcr
|= GEN_MASK(1, I2C_MCR_STOP
, 14);
315 mcr
&= ~(GEN_MASK(1, I2C_MCR_STOP
, 14));
317 mcr
|= GEN_MASK(dev
->cli
.count
, I2C_MCR_LENGTH
, 15);
323 * setup_i2c_controller() - setup the controller
324 * @dev: private data of controller
326 static void setup_i2c_controller(struct nmk_i2c_dev
*dev
)
331 writel(0x0, dev
->virtbase
+ I2C_CR
);
332 writel(0x0, dev
->virtbase
+ I2C_HSMCR
);
333 writel(0x0, dev
->virtbase
+ I2C_TFTR
);
334 writel(0x0, dev
->virtbase
+ I2C_RFTR
);
335 writel(0x0, dev
->virtbase
+ I2C_DMAR
);
340 * slsu defines the data setup time after SCL clock
341 * stretching in terms of i2c clk cycles. The
342 * needed setup time for the three modes are 250ns,
343 * 100ns, 10ns respectively thus leading to the values
344 * of 14, 6, 2 for a 48 MHz i2c clk.
346 writel(dev
->cfg
.slsu
<< 16, dev
->virtbase
+ I2C_SCR
);
348 i2c_clk
= clk_get_rate(dev
->clk
);
350 /* fallback to std. mode if machine has not provided it */
351 if (dev
->cfg
.clk_freq
== 0)
352 dev
->cfg
.clk_freq
= 100000;
355 * The spec says, in case of std. mode the divider is
356 * 2 whereas it is 3 for fast and fastplus mode of
357 * operation. TODO - high speed support.
359 div
= (dev
->cfg
.clk_freq
> 100000) ? 3 : 2;
362 * generate the mask for baud rate counters. The controller
363 * has two baud rate counters. One is used for High speed
364 * operation, and the other is for std, fast mode, fast mode
365 * plus operation. Currently we do not supprt high speed mode
369 brcr2
= (i2c_clk
/(dev
->cfg
.clk_freq
* div
)) & 0xffff;
371 /* set the baud rate counter register */
372 writel((brcr1
| brcr2
), dev
->virtbase
+ I2C_BRCR
);
375 * set the speed mode. Currently we support
376 * only standard and fast mode of operation
377 * TODO - support for fast mode plus (up to 1Mb/s)
378 * and high speed (up to 3.4 Mb/s)
380 if (dev
->cfg
.sm
> I2C_FREQ_MODE_FAST
) {
381 dev_err(&dev
->pdev
->dev
, "do not support this mode "
382 "defaulting to std. mode\n");
383 brcr2
= i2c_clk
/(100000 * 2) & 0xffff;
384 writel((brcr1
| brcr2
), dev
->virtbase
+ I2C_BRCR
);
385 writel(I2C_FREQ_MODE_STANDARD
<< 4,
386 dev
->virtbase
+ I2C_CR
);
388 writel(dev
->cfg
.sm
<< 4, dev
->virtbase
+ I2C_CR
);
390 /* set the Tx and Rx FIFO threshold */
391 writel(dev
->cfg
.tft
, dev
->virtbase
+ I2C_TFTR
);
392 writel(dev
->cfg
.rft
, dev
->virtbase
+ I2C_RFTR
);
396 * read_i2c() - Read from I2C client device
397 * @dev: private data of I2C Driver
399 * This function reads from i2c client device when controller is in
400 * master mode. There is a completion timeout. If there is no transfer
401 * before timeout error is returned.
403 static int read_i2c(struct nmk_i2c_dev
*dev
)
410 mcr
= load_i2c_mcr_reg(dev
);
411 writel(mcr
, dev
->virtbase
+ I2C_MCR
);
413 /* load the current CR value */
414 writel(readl(dev
->virtbase
+ I2C_CR
) | DEFAULT_I2C_REG_CR
,
415 dev
->virtbase
+ I2C_CR
);
417 /* enable the controller */
418 i2c_set_bit(dev
->virtbase
+ I2C_CR
, I2C_CR_PE
);
420 init_completion(&dev
->xfer_complete
);
422 /* enable interrupts by setting the mask */
423 irq_mask
= (I2C_IT_RXFNF
| I2C_IT_RXFF
|
424 I2C_IT_MAL
| I2C_IT_BERR
);
427 irq_mask
|= I2C_IT_MTD
;
429 irq_mask
|= I2C_IT_MTDWS
;
431 irq_mask
= I2C_CLEAR_ALL_INTS
& IRQ_MASK(irq_mask
);
433 writel(readl(dev
->virtbase
+ I2C_IMSCR
) | irq_mask
,
434 dev
->virtbase
+ I2C_IMSCR
);
436 timeout
= wait_for_completion_interruptible_timeout(
437 &dev
->xfer_complete
, msecs_to_jiffies(I2C_TIMEOUT_MS
));
440 dev_err(&dev
->pdev
->dev
,
441 "wait_for_completion_interruptible_timeout"
442 "returned %d waiting for event\n", timeout
);
447 /* controller has timedout, re-init the h/w */
448 dev_err(&dev
->pdev
->dev
, "controller timed out, re-init h/w\n");
456 * write_i2c() - Write data to I2C client.
457 * @dev: private data of I2C Driver
459 * This function writes data to I2C client
461 static int write_i2c(struct nmk_i2c_dev
*dev
)
468 mcr
= load_i2c_mcr_reg(dev
);
470 writel(mcr
, dev
->virtbase
+ I2C_MCR
);
472 /* load the current CR value */
473 writel(readl(dev
->virtbase
+ I2C_CR
) | DEFAULT_I2C_REG_CR
,
474 dev
->virtbase
+ I2C_CR
);
476 /* enable the controller */
477 i2c_set_bit(dev
->virtbase
+ I2C_CR
, I2C_CR_PE
);
479 init_completion(&dev
->xfer_complete
);
481 /* enable interrupts by settings the masks */
482 irq_mask
= (I2C_IT_TXFNE
| I2C_IT_TXFOVR
|
483 I2C_IT_MAL
| I2C_IT_BERR
);
486 * check if we want to transfer a single or multiple bytes, if so
487 * set the MTDWS bit (Master Transaction Done Without Stop)
488 * to start repeated start operation
491 irq_mask
|= I2C_IT_MTD
;
493 irq_mask
|= I2C_IT_MTDWS
;
495 irq_mask
= I2C_CLEAR_ALL_INTS
& IRQ_MASK(irq_mask
);
497 writel(readl(dev
->virtbase
+ I2C_IMSCR
) | irq_mask
,
498 dev
->virtbase
+ I2C_IMSCR
);
500 timeout
= wait_for_completion_interruptible_timeout(
501 &dev
->xfer_complete
, msecs_to_jiffies(I2C_TIMEOUT_MS
));
504 dev_err(&dev
->pdev
->dev
,
505 "wait_for_completion_interruptible_timeout"
506 "returned %d waiting for event\n", timeout
);
511 /* controller has timedout, re-init the h/w */
512 dev_err(&dev
->pdev
->dev
, "controller timed out, re-init h/w\n");
521 * nmk_i2c_xfer() - I2C transfer function used by kernel framework
522 * @i2c_adap: Adapter pointer to the controller
523 * @msgs: Pointer to data to be written.
524 * @num_msgs: Number of messages to be executed
526 * This is the function called by the generic kernel i2c_transfer()
527 * or i2c_smbus...() API calls. Note that this code is protected by the
528 * semaphore set in the kernel i2c_transfer() function.
531 * READ TRANSFER : We impose a restriction of the first message to be the
532 * index message for any read transaction.
533 * - a no index is coded as '0',
534 * - 2byte big endian index is coded as '3'
535 * !!! msg[0].buf holds the actual index.
536 * This is compatible with generic messages of smbus emulator
537 * that send a one byte index.
538 * eg. a I2C transation to read 2 bytes from index 0
540 * msg[0].addr = client->addr;
541 * msg[0].flags = 0x0;
545 * msg[1].addr = client->addr;
546 * msg[1].flags = I2C_M_RD;
548 * msg[1].buf = rd_buff
549 * i2c_transfer(adap, msg, 2);
551 * WRITE TRANSFER : The I2C standard interface interprets all data as payload.
552 * If you want to emulate an SMBUS write transaction put the
553 * index as first byte(or first and second) in the payload.
554 * eg. a I2C transation to write 2 bytes from index 1
558 * msg[0].flags = 0x0;
560 * msg[0].buf = wr_buff;
561 * i2c_transfer(adap, msg, 1);
563 * To read or write a block of data (multiple bytes) using SMBUS emulation
564 * please use the i2c_smbus_read_i2c_block_data()
565 * or i2c_smbus_write_i2c_block_data() API
567 static int nmk_i2c_xfer(struct i2c_adapter
*i2c_adap
,
568 struct i2c_msg msgs
[], int num_msgs
)
573 struct nmk_i2c_dev
*dev
= i2c_get_adapdata(i2c_adap
);
578 regulator_enable(dev
->regulator
);
580 status
= init_hw(dev
);
584 clk_enable(dev
->clk
);
586 /* setup the i2c controller */
587 setup_i2c_controller(dev
);
589 for (i
= 0; i
< num_msgs
; i
++) {
590 if (unlikely(msgs
[i
].flags
& I2C_M_TEN
)) {
591 dev_err(&dev
->pdev
->dev
, "10 bit addressing"
597 dev
->cli
.slave_adr
= msgs
[i
].addr
;
598 dev
->cli
.buffer
= msgs
[i
].buf
;
599 dev
->cli
.count
= msgs
[i
].len
;
600 dev
->stop
= (i
< (num_msgs
- 1)) ? 0 : 1;
603 if (msgs
[i
].flags
& I2C_M_RD
) {
604 /* it is a read operation */
605 dev
->cli
.operation
= I2C_READ
;
606 status
= read_i2c(dev
);
608 /* write operation */
609 dev
->cli
.operation
= I2C_WRITE
;
610 status
= write_i2c(dev
);
612 if (status
|| (dev
->result
)) {
613 /* get the abort cause */
614 cause
= (readl(dev
->virtbase
+ I2C_SR
) >> 4) & 0x7;
615 dev_err(&dev
->pdev
->dev
, "error during I2C"
616 "message xfer: %d\n", cause
);
617 dev_err(&dev
->pdev
->dev
, "%s\n",
618 cause
>= ARRAY_SIZE(abort_causes
)
619 ? "unknown reason" : abort_causes
[cause
]);
627 clk_disable(dev
->clk
);
630 regulator_disable(dev
->regulator
);
634 /* return the no. messages processed */
642 * disable_interrupts() - disable the interrupts
643 * @dev: private data of controller
644 * @irq: interrupt number
646 static int disable_interrupts(struct nmk_i2c_dev
*dev
, u32 irq
)
649 writel(readl(dev
->virtbase
+ I2C_IMSCR
) & ~(I2C_CLEAR_ALL_INTS
& irq
),
650 dev
->virtbase
+ I2C_IMSCR
);
655 * i2c_irq_handler() - interrupt routine
656 * @irq: interrupt number
657 * @arg: data passed to the handler
659 * This is the interrupt handler for the i2c driver. Currently
660 * it handles the major interrupts like Rx & Tx FIFO management
661 * interrupts, master transaction interrupts, arbitration and
662 * bus error interrupts. The rest of the interrupts are treated as
665 static irqreturn_t
i2c_irq_handler(int irq
, void *arg
)
667 struct nmk_i2c_dev
*dev
= arg
;
673 /* load Tx FIFO and Rx FIFO threshold values */
674 tft
= readl(dev
->virtbase
+ I2C_TFTR
);
675 rft
= readl(dev
->virtbase
+ I2C_RFTR
);
677 /* read interrupt status register */
678 misr
= readl(dev
->virtbase
+ I2C_MISR
);
681 switch ((1 << src
)) {
683 /* Transmit FIFO nearly empty interrupt */
686 if (dev
->cli
.operation
== I2C_READ
) {
688 * in read operation why do we care for writing?
689 * so disable the Transmit FIFO interrupt
691 disable_interrupts(dev
, I2C_IT_TXFNE
);
693 for (count
= (MAX_I2C_FIFO_THRESHOLD
- tft
- 2);
695 (dev
->cli
.count
!= 0);
697 /* write to the Tx FIFO */
698 writeb(*dev
->cli
.buffer
,
699 dev
->virtbase
+ I2C_TFR
);
702 dev
->cli
.xfer_bytes
++;
705 * if done, close the transfer by disabling the
706 * corresponding TXFNE interrupt
708 if (dev
->cli
.count
== 0)
709 disable_interrupts(dev
, I2C_IT_TXFNE
);
715 * Rx FIFO nearly full interrupt.
716 * This is set when the numer of entries in Rx FIFO is
717 * greater or equal than the threshold value programmed
721 for (count
= rft
; count
> 0; count
--) {
722 /* Read the Rx FIFO */
723 *dev
->cli
.buffer
= readb(dev
->virtbase
+ I2C_RFR
);
726 dev
->cli
.count
-= rft
;
727 dev
->cli
.xfer_bytes
+= rft
;
732 for (count
= MAX_I2C_FIFO_THRESHOLD
; count
> 0; count
--) {
733 *dev
->cli
.buffer
= readb(dev
->virtbase
+ I2C_RFR
);
736 dev
->cli
.count
-= MAX_I2C_FIFO_THRESHOLD
;
737 dev
->cli
.xfer_bytes
+= MAX_I2C_FIFO_THRESHOLD
;
740 /* Master Transaction Done with/without stop */
743 if (dev
->cli
.operation
== I2C_READ
) {
744 while (!(readl(dev
->virtbase
+ I2C_RISR
)
746 if (dev
->cli
.count
== 0)
749 readb(dev
->virtbase
+ I2C_RFR
);
752 dev
->cli
.xfer_bytes
++;
756 i2c_set_bit(dev
->virtbase
+ I2C_ICR
, I2C_IT_MTD
);
757 i2c_set_bit(dev
->virtbase
+ I2C_ICR
, I2C_IT_MTDWS
);
759 disable_interrupts(dev
,
760 (I2C_IT_TXFNE
| I2C_IT_TXFE
| I2C_IT_TXFF
761 | I2C_IT_TXFOVR
| I2C_IT_RXFNF
762 | I2C_IT_RXFF
| I2C_IT_RXFE
));
764 if (dev
->cli
.count
) {
766 dev_err(&dev
->pdev
->dev
, "%lu bytes still remain to be"
767 "xfered\n", dev
->cli
.count
);
770 complete(&dev
->xfer_complete
);
774 /* Master Arbitration lost interrupt */
779 i2c_set_bit(dev
->virtbase
+ I2C_ICR
, I2C_IT_MAL
);
780 complete(&dev
->xfer_complete
);
785 * Bus Error interrupt.
786 * This happens when an unexpected start/stop condition occurs
787 * during the transaction.
792 if (((readl(dev
->virtbase
+ I2C_SR
) >> 2) & 0x3) == I2C_ABORT
)
795 i2c_set_bit(dev
->virtbase
+ I2C_ICR
, I2C_IT_BERR
);
796 complete(&dev
->xfer_complete
);
801 * Tx FIFO overrun interrupt.
802 * This is set when a write operation in Tx FIFO is performed and
803 * the Tx FIFO is full.
809 dev_err(&dev
->pdev
->dev
, "Tx Fifo Over run\n");
810 complete(&dev
->xfer_complete
);
814 /* unhandled interrupts by this driver - TODO*/
822 dev_err(&dev
->pdev
->dev
, "unhandled Interrupt\n");
825 dev_err(&dev
->pdev
->dev
, "spurious Interrupt..\n");
834 static int nmk_i2c_suspend(struct platform_device
*pdev
, pm_message_t mesg
)
836 struct nmk_i2c_dev
*dev
= platform_get_drvdata(pdev
);
844 #define nmk_i2c_suspend NULL
847 static unsigned int nmk_i2c_functionality(struct i2c_adapter
*adap
)
849 return I2C_FUNC_I2C
| I2C_FUNC_SMBUS_EMUL
;
852 static const struct i2c_algorithm nmk_i2c_algo
= {
853 .master_xfer
= nmk_i2c_xfer
,
854 .functionality
= nmk_i2c_functionality
857 static int __devinit
nmk_i2c_probe(struct platform_device
*pdev
)
860 struct resource
*res
;
861 struct nmk_i2c_controller
*pdata
=
862 pdev
->dev
.platform_data
;
863 struct nmk_i2c_dev
*dev
;
864 struct i2c_adapter
*adap
;
866 dev
= kzalloc(sizeof(struct nmk_i2c_dev
), GFP_KERNEL
);
868 dev_err(&pdev
->dev
, "cannot allocate memory\n");
874 platform_set_drvdata(pdev
, dev
);
876 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
879 goto err_no_resource
;
882 if (request_mem_region(res
->start
, resource_size(res
),
883 DRIVER_NAME
"I/O region") == NULL
) {
888 dev
->virtbase
= ioremap(res
->start
, resource_size(res
));
889 if (!dev
->virtbase
) {
894 dev
->irq
= platform_get_irq(pdev
, 0);
895 ret
= request_irq(dev
->irq
, i2c_irq_handler
, IRQF_DISABLED
,
898 dev_err(&pdev
->dev
, "cannot claim the irq %d\n", dev
->irq
);
902 dev
->regulator
= regulator_get(&pdev
->dev
, "v-i2c");
903 if (IS_ERR(dev
->regulator
)) {
904 dev_warn(&pdev
->dev
, "could not get i2c regulator\n");
905 dev
->regulator
= NULL
;
908 dev
->clk
= clk_get(&pdev
->dev
, NULL
);
909 if (IS_ERR(dev
->clk
)) {
910 dev_err(&pdev
->dev
, "could not get i2c clock\n");
911 ret
= PTR_ERR(dev
->clk
);
916 adap
->dev
.parent
= &pdev
->dev
;
917 adap
->owner
= THIS_MODULE
;
918 adap
->class = I2C_CLASS_HWMON
| I2C_CLASS_SPD
;
919 adap
->algo
= &nmk_i2c_algo
;
920 snprintf(adap
->name
, sizeof(adap
->name
),
921 "Nomadik I2C%d at %lx", pdev
->id
, (unsigned long)res
->start
);
923 /* fetch the controller id */
926 /* fetch the controller configuration from machine */
927 dev
->cfg
.clk_freq
= pdata
->clk_freq
;
928 dev
->cfg
.slsu
= pdata
->slsu
;
929 dev
->cfg
.tft
= pdata
->tft
;
930 dev
->cfg
.rft
= pdata
->rft
;
931 dev
->cfg
.sm
= pdata
->sm
;
933 i2c_set_adapdata(adap
, dev
);
935 dev_info(&pdev
->dev
, "initialize %s on virtual "
936 "base %p\n", adap
->name
, dev
->virtbase
);
938 ret
= i2c_add_numbered_adapter(adap
);
940 dev_err(&pdev
->dev
, "failed to add adapter\n");
950 regulator_put(dev
->regulator
);
951 free_irq(dev
->irq
, dev
);
953 iounmap(dev
->virtbase
);
955 release_mem_region(res
->start
, resource_size(res
));
957 platform_set_drvdata(pdev
, NULL
);
965 static int __devexit
nmk_i2c_remove(struct platform_device
*pdev
)
967 struct resource
*res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
968 struct nmk_i2c_dev
*dev
= platform_get_drvdata(pdev
);
970 i2c_del_adapter(&dev
->adap
);
972 disable_all_interrupts(dev
);
973 clear_all_interrupts(dev
);
974 /* disable the controller */
975 i2c_clr_bit(dev
->virtbase
+ I2C_CR
, I2C_CR_PE
);
976 free_irq(dev
->irq
, dev
);
977 iounmap(dev
->virtbase
);
979 release_mem_region(res
->start
, resource_size(res
));
982 regulator_put(dev
->regulator
);
983 platform_set_drvdata(pdev
, NULL
);
989 static struct platform_driver nmk_i2c_driver
= {
991 .owner
= THIS_MODULE
,
994 .probe
= nmk_i2c_probe
,
995 .remove
= __devexit_p(nmk_i2c_remove
),
996 .suspend
= nmk_i2c_suspend
,
999 static int __init
nmk_i2c_init(void)
1001 return platform_driver_register(&nmk_i2c_driver
);
1004 static void __exit
nmk_i2c_exit(void)
1006 platform_driver_unregister(&nmk_i2c_driver
);
1009 subsys_initcall(nmk_i2c_init
);
1010 module_exit(nmk_i2c_exit
);
1012 MODULE_AUTHOR("Sachin Verma, Srinidhi KASAGAR");
1013 MODULE_DESCRIPTION("Nomadik/Ux500 I2C driver");
1014 MODULE_LICENSE("GPL");
1015 MODULE_ALIAS("platform:" DRIVER_NAME
);