2 * (C) Copyright 2009-2010
3 * Nokia Siemens Networks, michael.lawnick.ext@nsn.com
5 * Portions Copyright (C) 2010 - 2016 Cavium, Inc.
7 * This is a driver for the i2c adapter in Cavium Networks' OCTEON processors.
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
14 #include <linux/platform_device.h>
15 #include <linux/interrupt.h>
16 #include <linux/kernel.h>
17 #include <linux/module.h>
18 #include <linux/delay.h>
19 #include <linux/sched.h>
20 #include <linux/slab.h>
21 #include <linux/i2c.h>
25 #include <asm/octeon/octeon.h>
27 #define DRV_NAME "i2c-octeon"
29 /* Register offsets */
33 /* Controller command patterns */
34 #define SW_TWSI_V BIT_ULL(63) /* Valid bit */
35 #define SW_TWSI_R BIT_ULL(56) /* Result or read bit */
37 /* Controller opcode word (bits 60:57) */
38 #define SW_TWSI_OP_SHIFT 57
39 #define SW_TWSI_OP_TWSI_CLK (4ULL << SW_TWSI_OP_SHIFT)
40 #define SW_TWSI_OP_EOP (6ULL << SW_TWSI_OP_SHIFT) /* Extended opcode */
42 /* Controller extended opcode word (bits 34:32) */
43 #define SW_TWSI_EOP_SHIFT 32
44 #define SW_TWSI_EOP_TWSI_DATA (SW_TWSI_OP_EOP | 1ULL << SW_TWSI_EOP_SHIFT)
45 #define SW_TWSI_EOP_TWSI_CTL (SW_TWSI_OP_EOP | 2ULL << SW_TWSI_EOP_SHIFT)
46 #define SW_TWSI_EOP_TWSI_CLKCTL (SW_TWSI_OP_EOP | 3ULL << SW_TWSI_EOP_SHIFT)
47 #define SW_TWSI_EOP_TWSI_STAT (SW_TWSI_OP_EOP | 3ULL << SW_TWSI_EOP_SHIFT)
48 #define SW_TWSI_EOP_TWSI_RST (SW_TWSI_OP_EOP | 7ULL << SW_TWSI_EOP_SHIFT)
50 /* Controller command and status bits */
51 #define TWSI_CTL_CE 0x80
52 #define TWSI_CTL_ENAB 0x40 /* Bus enable */
53 #define TWSI_CTL_STA 0x20 /* Master-mode start, HW clears when done */
54 #define TWSI_CTL_STP 0x10 /* Master-mode stop, HW clears when done */
55 #define TWSI_CTL_IFLG 0x08 /* HW event, SW writes 0 to ACK */
56 #define TWSI_CTL_AAK 0x04 /* Assert ACK */
58 /* Some status values */
59 #define STAT_START 0x08
60 #define STAT_RSTART 0x10
61 #define STAT_TXADDR_ACK 0x18
62 #define STAT_TXDATA_ACK 0x28
63 #define STAT_RXADDR_ACK 0x40
64 #define STAT_RXDATA_ACK 0x50
65 #define STAT_IDLE 0xF8
68 #define TWSI_INT_CORE_EN BIT_ULL(6)
69 #define TWSI_INT_SDA_OVR BIT_ULL(8)
70 #define TWSI_INT_SCL_OVR BIT_ULL(9)
73 wait_queue_head_t queue
;
74 struct i2c_adapter adap
;
78 void __iomem
*twsi_base
;
83 * octeon_i2c_write_sw - write an I2C core register
84 * @i2c: The struct octeon_i2c
85 * @eop_reg: Register selector
86 * @data: Value to be written
88 * The I2C core registers are accessed indirectly via the SW_TWSI CSR.
90 static void octeon_i2c_write_sw(struct octeon_i2c
*i2c
, u64 eop_reg
, u8 data
)
94 __raw_writeq(SW_TWSI_V
| eop_reg
| data
, i2c
->twsi_base
+ SW_TWSI
);
96 tmp
= __raw_readq(i2c
->twsi_base
+ SW_TWSI
);
97 } while ((tmp
& SW_TWSI_V
) != 0);
101 * octeon_i2c_read_sw - read lower bits of an I2C core register
102 * @i2c: The struct octeon_i2c
103 * @eop_reg: Register selector
107 * The I2C core registers are accessed indirectly via the SW_TWSI CSR.
109 static u8
octeon_i2c_read_sw(struct octeon_i2c
*i2c
, u64 eop_reg
)
113 __raw_writeq(SW_TWSI_V
| eop_reg
| SW_TWSI_R
, i2c
->twsi_base
+ SW_TWSI
);
115 tmp
= __raw_readq(i2c
->twsi_base
+ SW_TWSI
);
116 } while ((tmp
& SW_TWSI_V
) != 0);
122 * octeon_i2c_write_int - write the TWSI_INT register
123 * @i2c: The struct octeon_i2c
124 * @data: Value to be written
126 static void octeon_i2c_write_int(struct octeon_i2c
*i2c
, u64 data
)
128 __raw_writeq(data
, i2c
->twsi_base
+ TWSI_INT
);
129 __raw_readq(i2c
->twsi_base
+ TWSI_INT
);
133 * octeon_i2c_int_enable - enable the CORE interrupt
134 * @i2c: The struct octeon_i2c
136 * The interrupt will be asserted when there is non-STAT_IDLE state in
137 * the SW_TWSI_EOP_TWSI_STAT register.
139 static void octeon_i2c_int_enable(struct octeon_i2c
*i2c
)
141 octeon_i2c_write_int(i2c
, TWSI_INT_CORE_EN
);
144 /* disable the CORE interrupt */
145 static void octeon_i2c_int_disable(struct octeon_i2c
*i2c
)
147 /* clear TS/ST/IFLG events */
148 octeon_i2c_write_int(i2c
, 0);
152 * octeon_i2c_unblock - unblock the bus
153 * @i2c: The struct octeon_i2c
155 * If there was a reset while a device was driving 0 to bus, bus is blocked.
156 * We toggle it free manually by some clock cycles and send a stop.
158 static void octeon_i2c_unblock(struct octeon_i2c
*i2c
)
162 dev_dbg(i2c
->dev
, "%s\n", __func__
);
164 for (i
= 0; i
< 9; i
++) {
165 octeon_i2c_write_int(i2c
, 0);
167 octeon_i2c_write_int(i2c
, TWSI_INT_SCL_OVR
);
170 /* hand-crank a STOP */
171 octeon_i2c_write_int(i2c
, TWSI_INT_SDA_OVR
| TWSI_INT_SCL_OVR
);
173 octeon_i2c_write_int(i2c
, TWSI_INT_SDA_OVR
);
175 octeon_i2c_write_int(i2c
, 0);
178 /* interrupt service routine */
179 static irqreturn_t
octeon_i2c_isr(int irq
, void *dev_id
)
181 struct octeon_i2c
*i2c
= dev_id
;
183 octeon_i2c_int_disable(i2c
);
184 wake_up(&i2c
->queue
);
190 static int octeon_i2c_test_iflg(struct octeon_i2c
*i2c
)
192 return (octeon_i2c_read_sw(i2c
, SW_TWSI_EOP_TWSI_CTL
) & TWSI_CTL_IFLG
) != 0;
196 * octeon_i2c_wait - wait for the IFLG to be set
197 * @i2c: The struct octeon_i2c
199 * Returns 0 on success, otherwise a negative errno.
201 static int octeon_i2c_wait(struct octeon_i2c
*i2c
)
205 octeon_i2c_int_enable(i2c
);
206 time_left
= wait_event_timeout(i2c
->queue
, octeon_i2c_test_iflg(i2c
),
208 octeon_i2c_int_disable(i2c
);
210 dev_dbg(i2c
->dev
, "%s: timeout\n", __func__
);
218 * octeon_i2c_start - send START to the bus
219 * @i2c: The struct octeon_i2c
221 * Returns 0 on success, otherwise a negative errno.
223 static int octeon_i2c_start(struct octeon_i2c
*i2c
)
228 octeon_i2c_write_sw(i2c
, SW_TWSI_EOP_TWSI_CTL
,
229 TWSI_CTL_ENAB
| TWSI_CTL_STA
);
231 result
= octeon_i2c_wait(i2c
);
233 if (octeon_i2c_read_sw(i2c
, SW_TWSI_EOP_TWSI_STAT
) == STAT_IDLE
) {
235 * Controller refused to send start flag May
236 * be a client is holding SDA low - let's try
239 octeon_i2c_unblock(i2c
);
240 octeon_i2c_write_sw(i2c
, SW_TWSI_EOP_TWSI_CTL
,
241 TWSI_CTL_ENAB
| TWSI_CTL_STA
);
242 result
= octeon_i2c_wait(i2c
);
248 data
= octeon_i2c_read_sw(i2c
, SW_TWSI_EOP_TWSI_STAT
);
249 if ((data
!= STAT_START
) && (data
!= STAT_RSTART
)) {
250 dev_err(i2c
->dev
, "%s: bad status (0x%x)\n", __func__
, data
);
257 /* send STOP to the bus */
258 static void octeon_i2c_stop(struct octeon_i2c
*i2c
)
260 octeon_i2c_write_sw(i2c
, SW_TWSI_EOP_TWSI_CTL
,
261 TWSI_CTL_ENAB
| TWSI_CTL_STP
);
265 * octeon_i2c_write - send data to the bus via low-level controller
266 * @i2c: The struct octeon_i2c
267 * @target: Target address
268 * @data: Pointer to the data to be sent
269 * @length: Length of the data
271 * The address is sent over the bus, then the data.
273 * Returns 0 on success, otherwise a negative errno.
275 static int octeon_i2c_write(struct octeon_i2c
*i2c
, int target
,
276 const u8
*data
, int length
)
281 result
= octeon_i2c_start(i2c
);
285 octeon_i2c_write_sw(i2c
, SW_TWSI_EOP_TWSI_DATA
, target
<< 1);
286 octeon_i2c_write_sw(i2c
, SW_TWSI_EOP_TWSI_CTL
, TWSI_CTL_ENAB
);
288 result
= octeon_i2c_wait(i2c
);
292 for (i
= 0; i
< length
; i
++) {
293 tmp
= octeon_i2c_read_sw(i2c
, SW_TWSI_EOP_TWSI_STAT
);
295 if ((tmp
!= STAT_TXADDR_ACK
) && (tmp
!= STAT_TXDATA_ACK
)) {
297 "%s: bad status before write (0x%x)\n",
302 octeon_i2c_write_sw(i2c
, SW_TWSI_EOP_TWSI_DATA
, data
[i
]);
303 octeon_i2c_write_sw(i2c
, SW_TWSI_EOP_TWSI_CTL
, TWSI_CTL_ENAB
);
305 result
= octeon_i2c_wait(i2c
);
314 * octeon_i2c_read - receive data from the bus via low-level controller
315 * @i2c: The struct octeon_i2c
316 * @target: Target address
317 * @data: Pointer to the location to store the data
318 * @length: Length of the data
320 * The address is sent over the bus, then the data is read.
322 * Returns 0 on success, otherwise a negative errno.
324 static int octeon_i2c_read(struct octeon_i2c
*i2c
, int target
,
325 u8
*data
, int length
)
333 result
= octeon_i2c_start(i2c
);
337 octeon_i2c_write_sw(i2c
, SW_TWSI_EOP_TWSI_DATA
, (target
<< 1) | 1);
338 octeon_i2c_write_sw(i2c
, SW_TWSI_EOP_TWSI_CTL
, TWSI_CTL_ENAB
);
340 result
= octeon_i2c_wait(i2c
);
344 for (i
= 0; i
< length
; i
++) {
345 tmp
= octeon_i2c_read_sw(i2c
, SW_TWSI_EOP_TWSI_STAT
);
347 if ((tmp
!= STAT_RXDATA_ACK
) && (tmp
!= STAT_RXADDR_ACK
)) {
349 "%s: bad status before read (0x%x)\n",
355 octeon_i2c_write_sw(i2c
, SW_TWSI_EOP_TWSI_CTL
,
356 TWSI_CTL_ENAB
| TWSI_CTL_AAK
);
358 octeon_i2c_write_sw(i2c
, SW_TWSI_EOP_TWSI_CTL
,
361 result
= octeon_i2c_wait(i2c
);
365 data
[i
] = octeon_i2c_read_sw(i2c
, SW_TWSI_EOP_TWSI_DATA
);
371 * octeon_i2c_xfer - The driver's master_xfer function
372 * @adap: Pointer to the i2c_adapter structure
373 * @msgs: Pointer to the messages to be processed
374 * @num: Length of the MSGS array
376 * Returns the number of messages processed, or a negative errno on failure.
378 static int octeon_i2c_xfer(struct i2c_adapter
*adap
, struct i2c_msg
*msgs
,
381 struct octeon_i2c
*i2c
= i2c_get_adapdata(adap
);
384 for (i
= 0; ret
== 0 && i
< num
; i
++) {
385 struct i2c_msg
*pmsg
= &msgs
[i
];
388 "Doing %s %d byte(s) to/from 0x%02x - %d of %d messages\n",
389 pmsg
->flags
& I2C_M_RD
? "read" : "write",
390 pmsg
->len
, pmsg
->addr
, i
+ 1, num
);
391 if (pmsg
->flags
& I2C_M_RD
)
392 ret
= octeon_i2c_read(i2c
, pmsg
->addr
, pmsg
->buf
,
395 ret
= octeon_i2c_write(i2c
, pmsg
->addr
, pmsg
->buf
,
398 octeon_i2c_stop(i2c
);
400 return (ret
!= 0) ? ret
: num
;
403 static u32
octeon_i2c_functionality(struct i2c_adapter
*adap
)
405 return I2C_FUNC_I2C
| I2C_FUNC_SMBUS_EMUL
;
408 static const struct i2c_algorithm octeon_i2c_algo
= {
409 .master_xfer
= octeon_i2c_xfer
,
410 .functionality
= octeon_i2c_functionality
,
413 static struct i2c_adapter octeon_i2c_ops
= {
414 .owner
= THIS_MODULE
,
415 .name
= "OCTEON adapter",
416 .algo
= &octeon_i2c_algo
,
420 /* calculate and set clock divisors */
421 static void octeon_i2c_set_clock(struct octeon_i2c
*i2c
)
423 int tclk
, thp_base
, inc
, thp_idx
, mdiv_idx
, ndiv_idx
, foscl
, diff
;
424 int thp
= 0x18, mdiv
= 2, ndiv
= 0, delta_hz
= 1000000;
426 for (ndiv_idx
= 0; ndiv_idx
< 8 && delta_hz
!= 0; ndiv_idx
++) {
428 * An mdiv value of less than 2 seems to not work well
429 * with ds1337 RTCs, so we constrain it to larger values.
431 for (mdiv_idx
= 15; mdiv_idx
>= 2 && delta_hz
!= 0; mdiv_idx
--) {
433 * For given ndiv and mdiv values check the
434 * two closest thp values.
436 tclk
= i2c
->twsi_freq
* (mdiv_idx
+ 1) * 10;
437 tclk
*= (1 << ndiv_idx
);
438 thp_base
= (i2c
->sys_freq
/ (tclk
* 2)) - 1;
440 for (inc
= 0; inc
<= 1; inc
++) {
441 thp_idx
= thp_base
+ inc
;
442 if (thp_idx
< 5 || thp_idx
> 0xff)
445 foscl
= i2c
->sys_freq
/ (2 * (thp_idx
+ 1));
446 foscl
= foscl
/ (1 << ndiv_idx
);
447 foscl
= foscl
/ (mdiv_idx
+ 1) / 10;
448 diff
= abs(foscl
- i2c
->twsi_freq
);
449 if (diff
< delta_hz
) {
458 octeon_i2c_write_sw(i2c
, SW_TWSI_OP_TWSI_CLK
, thp
);
459 octeon_i2c_write_sw(i2c
, SW_TWSI_EOP_TWSI_CLKCTL
, (mdiv
<< 3) | ndiv
);
462 static int octeon_i2c_init_lowlevel(struct octeon_i2c
*i2c
)
467 /* disable high level controller, enable bus access */
468 octeon_i2c_write_sw(i2c
, SW_TWSI_EOP_TWSI_CTL
, TWSI_CTL_ENAB
);
470 /* reset controller */
471 octeon_i2c_write_sw(i2c
, SW_TWSI_EOP_TWSI_RST
, 0);
473 for (tries
= 10; tries
; tries
--) {
475 status
= octeon_i2c_read_sw(i2c
, SW_TWSI_EOP_TWSI_STAT
);
476 if (status
== STAT_IDLE
)
479 dev_err(i2c
->dev
, "%s: TWSI_RST failed! (0x%x)\n", __func__
, status
);
483 static int octeon_i2c_probe(struct platform_device
*pdev
)
485 struct device_node
*node
= pdev
->dev
.of_node
;
486 struct resource
*res_mem
;
487 struct octeon_i2c
*i2c
;
490 /* All adaptors have an irq. */
491 irq
= platform_get_irq(pdev
, 0);
495 i2c
= devm_kzalloc(&pdev
->dev
, sizeof(*i2c
), GFP_KERNEL
);
500 i2c
->dev
= &pdev
->dev
;
502 res_mem
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
503 i2c
->twsi_base
= devm_ioremap_resource(&pdev
->dev
, res_mem
);
504 if (IS_ERR(i2c
->twsi_base
)) {
505 result
= PTR_ERR(i2c
->twsi_base
);
510 * "clock-rate" is a legacy binding, the official binding is
511 * "clock-frequency". Try the official one first and then
512 * fall back if it doesn't exist.
514 if (of_property_read_u32(node
, "clock-frequency", &i2c
->twsi_freq
) &&
515 of_property_read_u32(node
, "clock-rate", &i2c
->twsi_freq
)) {
517 "no I2C 'clock-rate' or 'clock-frequency' property\n");
522 i2c
->sys_freq
= octeon_get_io_clock_rate();
524 init_waitqueue_head(&i2c
->queue
);
528 result
= devm_request_irq(&pdev
->dev
, i2c
->irq
,
529 octeon_i2c_isr
, 0, DRV_NAME
, i2c
);
531 dev_err(i2c
->dev
, "failed to attach interrupt\n");
535 result
= octeon_i2c_init_lowlevel(i2c
);
537 dev_err(i2c
->dev
, "init low level failed\n");
541 octeon_i2c_set_clock(i2c
);
543 i2c
->adap
= octeon_i2c_ops
;
544 i2c
->adap
.dev
.parent
= &pdev
->dev
;
545 i2c
->adap
.dev
.of_node
= node
;
546 i2c_set_adapdata(&i2c
->adap
, i2c
);
547 platform_set_drvdata(pdev
, i2c
);
549 result
= i2c_add_adapter(&i2c
->adap
);
551 dev_err(i2c
->dev
, "failed to add adapter\n");
554 dev_info(i2c
->dev
, "probed\n");
561 static int octeon_i2c_remove(struct platform_device
*pdev
)
563 struct octeon_i2c
*i2c
= platform_get_drvdata(pdev
);
565 i2c_del_adapter(&i2c
->adap
);
569 static const struct of_device_id octeon_i2c_match
[] = {
570 { .compatible
= "cavium,octeon-3860-twsi", },
573 MODULE_DEVICE_TABLE(of
, octeon_i2c_match
);
575 static struct platform_driver octeon_i2c_driver
= {
576 .probe
= octeon_i2c_probe
,
577 .remove
= octeon_i2c_remove
,
580 .of_match_table
= octeon_i2c_match
,
584 module_platform_driver(octeon_i2c_driver
);
586 MODULE_AUTHOR("Michael Lawnick <michael.lawnick.ext@nsn.com>");
587 MODULE_DESCRIPTION("I2C-Bus adapter for Cavium OCTEON processors");
588 MODULE_LICENSE("GPL");