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[mirror_ubuntu-focal-kernel.git] / drivers / i2c / busses / i2c-omap.c
1 /*
2 * TI OMAP I2C master mode driver
3 *
4 * Copyright (C) 2003 MontaVista Software, Inc.
5 * Copyright (C) 2005 Nokia Corporation
6 * Copyright (C) 2004 - 2007 Texas Instruments.
7 *
8 * Originally written by MontaVista Software, Inc.
9 * Additional contributions by:
10 * Tony Lindgren <tony@atomide.com>
11 * Imre Deak <imre.deak@nokia.com>
12 * Juha Yrjölä <juha.yrjola@solidboot.com>
13 * Syed Khasim <x0khasim@ti.com>
14 * Nishant Menon <nm@ti.com>
15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License as published by
18 * the Free Software Foundation; either version 2 of the License, or
19 * (at your option) any later version.
20 *
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
25 */
26
27 #include <linux/module.h>
28 #include <linux/delay.h>
29 #include <linux/i2c.h>
30 #include <linux/err.h>
31 #include <linux/interrupt.h>
32 #include <linux/completion.h>
33 #include <linux/platform_device.h>
34 #include <linux/clk.h>
35 #include <linux/io.h>
36 #include <linux/of.h>
37 #include <linux/of_device.h>
38 #include <linux/slab.h>
39 #include <linux/i2c-omap.h>
40 #include <linux/pm_runtime.h>
41 #include <linux/pinctrl/consumer.h>
42
43 /* I2C controller revisions */
44 #define OMAP_I2C_OMAP1_REV_2 0x20
45
46 /* I2C controller revisions present on specific hardware */
47 #define OMAP_I2C_REV_ON_2430 0x00000036
48 #define OMAP_I2C_REV_ON_3430_3530 0x0000003C
49 #define OMAP_I2C_REV_ON_3630 0x00000040
50 #define OMAP_I2C_REV_ON_4430_PLUS 0x50400002
51
52 /* timeout waiting for the controller to respond */
53 #define OMAP_I2C_TIMEOUT (msecs_to_jiffies(1000))
54
55 /* timeout for pm runtime autosuspend */
56 #define OMAP_I2C_PM_TIMEOUT 1000 /* ms */
57
58 /* timeout for making decision on bus free status */
59 #define OMAP_I2C_BUS_FREE_TIMEOUT (msecs_to_jiffies(10))
60
61 /* For OMAP3 I2C_IV has changed to I2C_WE (wakeup enable) */
62 enum {
63 OMAP_I2C_REV_REG = 0,
64 OMAP_I2C_IE_REG,
65 OMAP_I2C_STAT_REG,
66 OMAP_I2C_IV_REG,
67 OMAP_I2C_WE_REG,
68 OMAP_I2C_SYSS_REG,
69 OMAP_I2C_BUF_REG,
70 OMAP_I2C_CNT_REG,
71 OMAP_I2C_DATA_REG,
72 OMAP_I2C_SYSC_REG,
73 OMAP_I2C_CON_REG,
74 OMAP_I2C_OA_REG,
75 OMAP_I2C_SA_REG,
76 OMAP_I2C_PSC_REG,
77 OMAP_I2C_SCLL_REG,
78 OMAP_I2C_SCLH_REG,
79 OMAP_I2C_SYSTEST_REG,
80 OMAP_I2C_BUFSTAT_REG,
81 /* only on OMAP4430 */
82 OMAP_I2C_IP_V2_REVNB_LO,
83 OMAP_I2C_IP_V2_REVNB_HI,
84 OMAP_I2C_IP_V2_IRQSTATUS_RAW,
85 OMAP_I2C_IP_V2_IRQENABLE_SET,
86 OMAP_I2C_IP_V2_IRQENABLE_CLR,
87 };
88
89 /* I2C Interrupt Enable Register (OMAP_I2C_IE): */
90 #define OMAP_I2C_IE_XDR (1 << 14) /* TX Buffer drain int enable */
91 #define OMAP_I2C_IE_RDR (1 << 13) /* RX Buffer drain int enable */
92 #define OMAP_I2C_IE_XRDY (1 << 4) /* TX data ready int enable */
93 #define OMAP_I2C_IE_RRDY (1 << 3) /* RX data ready int enable */
94 #define OMAP_I2C_IE_ARDY (1 << 2) /* Access ready int enable */
95 #define OMAP_I2C_IE_NACK (1 << 1) /* No ack interrupt enable */
96 #define OMAP_I2C_IE_AL (1 << 0) /* Arbitration lost int ena */
97
98 /* I2C Status Register (OMAP_I2C_STAT): */
99 #define OMAP_I2C_STAT_XDR (1 << 14) /* TX Buffer draining */
100 #define OMAP_I2C_STAT_RDR (1 << 13) /* RX Buffer draining */
101 #define OMAP_I2C_STAT_BB (1 << 12) /* Bus busy */
102 #define OMAP_I2C_STAT_ROVR (1 << 11) /* Receive overrun */
103 #define OMAP_I2C_STAT_XUDF (1 << 10) /* Transmit underflow */
104 #define OMAP_I2C_STAT_AAS (1 << 9) /* Address as slave */
105 #define OMAP_I2C_STAT_BF (1 << 8) /* Bus Free */
106 #define OMAP_I2C_STAT_XRDY (1 << 4) /* Transmit data ready */
107 #define OMAP_I2C_STAT_RRDY (1 << 3) /* Receive data ready */
108 #define OMAP_I2C_STAT_ARDY (1 << 2) /* Register access ready */
109 #define OMAP_I2C_STAT_NACK (1 << 1) /* No ack interrupt enable */
110 #define OMAP_I2C_STAT_AL (1 << 0) /* Arbitration lost int ena */
111
112 /* I2C WE wakeup enable register */
113 #define OMAP_I2C_WE_XDR_WE (1 << 14) /* TX drain wakup */
114 #define OMAP_I2C_WE_RDR_WE (1 << 13) /* RX drain wakeup */
115 #define OMAP_I2C_WE_AAS_WE (1 << 9) /* Address as slave wakeup*/
116 #define OMAP_I2C_WE_BF_WE (1 << 8) /* Bus free wakeup */
117 #define OMAP_I2C_WE_STC_WE (1 << 6) /* Start condition wakeup */
118 #define OMAP_I2C_WE_GC_WE (1 << 5) /* General call wakeup */
119 #define OMAP_I2C_WE_DRDY_WE (1 << 3) /* TX/RX data ready wakeup */
120 #define OMAP_I2C_WE_ARDY_WE (1 << 2) /* Reg access ready wakeup */
121 #define OMAP_I2C_WE_NACK_WE (1 << 1) /* No acknowledgment wakeup */
122 #define OMAP_I2C_WE_AL_WE (1 << 0) /* Arbitration lost wakeup */
123
124 #define OMAP_I2C_WE_ALL (OMAP_I2C_WE_XDR_WE | OMAP_I2C_WE_RDR_WE | \
125 OMAP_I2C_WE_AAS_WE | OMAP_I2C_WE_BF_WE | \
126 OMAP_I2C_WE_STC_WE | OMAP_I2C_WE_GC_WE | \
127 OMAP_I2C_WE_DRDY_WE | OMAP_I2C_WE_ARDY_WE | \
128 OMAP_I2C_WE_NACK_WE | OMAP_I2C_WE_AL_WE)
129
130 /* I2C Buffer Configuration Register (OMAP_I2C_BUF): */
131 #define OMAP_I2C_BUF_RDMA_EN (1 << 15) /* RX DMA channel enable */
132 #define OMAP_I2C_BUF_RXFIF_CLR (1 << 14) /* RX FIFO Clear */
133 #define OMAP_I2C_BUF_XDMA_EN (1 << 7) /* TX DMA channel enable */
134 #define OMAP_I2C_BUF_TXFIF_CLR (1 << 6) /* TX FIFO Clear */
135
136 /* I2C Configuration Register (OMAP_I2C_CON): */
137 #define OMAP_I2C_CON_EN (1 << 15) /* I2C module enable */
138 #define OMAP_I2C_CON_BE (1 << 14) /* Big endian mode */
139 #define OMAP_I2C_CON_OPMODE_HS (1 << 12) /* High Speed support */
140 #define OMAP_I2C_CON_STB (1 << 11) /* Start byte mode (master) */
141 #define OMAP_I2C_CON_MST (1 << 10) /* Master/slave mode */
142 #define OMAP_I2C_CON_TRX (1 << 9) /* TX/RX mode (master only) */
143 #define OMAP_I2C_CON_XA (1 << 8) /* Expand address */
144 #define OMAP_I2C_CON_RM (1 << 2) /* Repeat mode (master only) */
145 #define OMAP_I2C_CON_STP (1 << 1) /* Stop cond (master only) */
146 #define OMAP_I2C_CON_STT (1 << 0) /* Start condition (master) */
147
148 /* I2C SCL time value when Master */
149 #define OMAP_I2C_SCLL_HSSCLL 8
150 #define OMAP_I2C_SCLH_HSSCLH 8
151
152 /* I2C System Test Register (OMAP_I2C_SYSTEST): */
153 #define OMAP_I2C_SYSTEST_ST_EN (1 << 15) /* System test enable */
154 #define OMAP_I2C_SYSTEST_FREE (1 << 14) /* Free running mode */
155 #define OMAP_I2C_SYSTEST_TMODE_MASK (3 << 12) /* Test mode select */
156 #define OMAP_I2C_SYSTEST_TMODE_SHIFT (12) /* Test mode select */
157 /* Functional mode */
158 #define OMAP_I2C_SYSTEST_SCL_I_FUNC (1 << 8) /* SCL line input value */
159 #define OMAP_I2C_SYSTEST_SCL_O_FUNC (1 << 7) /* SCL line output value */
160 #define OMAP_I2C_SYSTEST_SDA_I_FUNC (1 << 6) /* SDA line input value */
161 #define OMAP_I2C_SYSTEST_SDA_O_FUNC (1 << 5) /* SDA line output value */
162 /* SDA/SCL IO mode */
163 #define OMAP_I2C_SYSTEST_SCL_I (1 << 3) /* SCL line sense in */
164 #define OMAP_I2C_SYSTEST_SCL_O (1 << 2) /* SCL line drive out */
165 #define OMAP_I2C_SYSTEST_SDA_I (1 << 1) /* SDA line sense in */
166 #define OMAP_I2C_SYSTEST_SDA_O (1 << 0) /* SDA line drive out */
167
168 /* OCP_SYSSTATUS bit definitions */
169 #define SYSS_RESETDONE_MASK (1 << 0)
170
171 /* OCP_SYSCONFIG bit definitions */
172 #define SYSC_CLOCKACTIVITY_MASK (0x3 << 8)
173 #define SYSC_SIDLEMODE_MASK (0x3 << 3)
174 #define SYSC_ENAWAKEUP_MASK (1 << 2)
175 #define SYSC_SOFTRESET_MASK (1 << 1)
176 #define SYSC_AUTOIDLE_MASK (1 << 0)
177
178 #define SYSC_IDLEMODE_SMART 0x2
179 #define SYSC_CLOCKACTIVITY_FCLK 0x2
180
181 /* Errata definitions */
182 #define I2C_OMAP_ERRATA_I207 (1 << 0)
183 #define I2C_OMAP_ERRATA_I462 (1 << 1)
184
185 #define OMAP_I2C_IP_V2_INTERRUPTS_MASK 0x6FFF
186
187 struct omap_i2c_dev {
188 struct device *dev;
189 void __iomem *base; /* virtual */
190 int irq;
191 int reg_shift; /* bit shift for I2C register addresses */
192 struct completion cmd_complete;
193 struct resource *ioarea;
194 u32 latency; /* maximum mpu wkup latency */
195 void (*set_mpu_wkup_lat)(struct device *dev,
196 long latency);
197 u32 speed; /* Speed of bus in kHz */
198 u32 flags;
199 u16 scheme;
200 u16 cmd_err;
201 u8 *buf;
202 u8 *regs;
203 size_t buf_len;
204 struct i2c_adapter adapter;
205 u8 threshold;
206 u8 fifo_size; /* use as flag and value
207 * fifo_size==0 implies no fifo
208 * if set, should be trsh+1
209 */
210 u32 rev;
211 unsigned b_hw:1; /* bad h/w fixes */
212 unsigned bb_valid:1; /* true when BB-bit reflects
213 * the I2C bus state
214 */
215 unsigned receiver:1; /* true when we're in receiver mode */
216 u16 iestate; /* Saved interrupt register */
217 u16 pscstate;
218 u16 scllstate;
219 u16 sclhstate;
220 u16 syscstate;
221 u16 westate;
222 u16 errata;
223 };
224
225 static const u8 reg_map_ip_v1[] = {
226 [OMAP_I2C_REV_REG] = 0x00,
227 [OMAP_I2C_IE_REG] = 0x01,
228 [OMAP_I2C_STAT_REG] = 0x02,
229 [OMAP_I2C_IV_REG] = 0x03,
230 [OMAP_I2C_WE_REG] = 0x03,
231 [OMAP_I2C_SYSS_REG] = 0x04,
232 [OMAP_I2C_BUF_REG] = 0x05,
233 [OMAP_I2C_CNT_REG] = 0x06,
234 [OMAP_I2C_DATA_REG] = 0x07,
235 [OMAP_I2C_SYSC_REG] = 0x08,
236 [OMAP_I2C_CON_REG] = 0x09,
237 [OMAP_I2C_OA_REG] = 0x0a,
238 [OMAP_I2C_SA_REG] = 0x0b,
239 [OMAP_I2C_PSC_REG] = 0x0c,
240 [OMAP_I2C_SCLL_REG] = 0x0d,
241 [OMAP_I2C_SCLH_REG] = 0x0e,
242 [OMAP_I2C_SYSTEST_REG] = 0x0f,
243 [OMAP_I2C_BUFSTAT_REG] = 0x10,
244 };
245
246 static const u8 reg_map_ip_v2[] = {
247 [OMAP_I2C_REV_REG] = 0x04,
248 [OMAP_I2C_IE_REG] = 0x2c,
249 [OMAP_I2C_STAT_REG] = 0x28,
250 [OMAP_I2C_IV_REG] = 0x34,
251 [OMAP_I2C_WE_REG] = 0x34,
252 [OMAP_I2C_SYSS_REG] = 0x90,
253 [OMAP_I2C_BUF_REG] = 0x94,
254 [OMAP_I2C_CNT_REG] = 0x98,
255 [OMAP_I2C_DATA_REG] = 0x9c,
256 [OMAP_I2C_SYSC_REG] = 0x10,
257 [OMAP_I2C_CON_REG] = 0xa4,
258 [OMAP_I2C_OA_REG] = 0xa8,
259 [OMAP_I2C_SA_REG] = 0xac,
260 [OMAP_I2C_PSC_REG] = 0xb0,
261 [OMAP_I2C_SCLL_REG] = 0xb4,
262 [OMAP_I2C_SCLH_REG] = 0xb8,
263 [OMAP_I2C_SYSTEST_REG] = 0xbC,
264 [OMAP_I2C_BUFSTAT_REG] = 0xc0,
265 [OMAP_I2C_IP_V2_REVNB_LO] = 0x00,
266 [OMAP_I2C_IP_V2_REVNB_HI] = 0x04,
267 [OMAP_I2C_IP_V2_IRQSTATUS_RAW] = 0x24,
268 [OMAP_I2C_IP_V2_IRQENABLE_SET] = 0x2c,
269 [OMAP_I2C_IP_V2_IRQENABLE_CLR] = 0x30,
270 };
271
272 static inline void omap_i2c_write_reg(struct omap_i2c_dev *omap,
273 int reg, u16 val)
274 {
275 writew_relaxed(val, omap->base +
276 (omap->regs[reg] << omap->reg_shift));
277 }
278
279 static inline u16 omap_i2c_read_reg(struct omap_i2c_dev *omap, int reg)
280 {
281 return readw_relaxed(omap->base +
282 (omap->regs[reg] << omap->reg_shift));
283 }
284
285 static void __omap_i2c_init(struct omap_i2c_dev *omap)
286 {
287
288 omap_i2c_write_reg(omap, OMAP_I2C_CON_REG, 0);
289
290 /* Setup clock prescaler to obtain approx 12MHz I2C module clock: */
291 omap_i2c_write_reg(omap, OMAP_I2C_PSC_REG, omap->pscstate);
292
293 /* SCL low and high time values */
294 omap_i2c_write_reg(omap, OMAP_I2C_SCLL_REG, omap->scllstate);
295 omap_i2c_write_reg(omap, OMAP_I2C_SCLH_REG, omap->sclhstate);
296 if (omap->rev >= OMAP_I2C_REV_ON_3430_3530)
297 omap_i2c_write_reg(omap, OMAP_I2C_WE_REG, omap->westate);
298
299 /* Take the I2C module out of reset: */
300 omap_i2c_write_reg(omap, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
301
302 /*
303 * NOTE: right after setting CON_EN, STAT_BB could be 0 while the
304 * bus is busy. It will be changed to 1 on the next IP FCLK clock.
305 * udelay(1) will be enough to fix that.
306 */
307
308 /*
309 * Don't write to this register if the IE state is 0 as it can
310 * cause deadlock.
311 */
312 if (omap->iestate)
313 omap_i2c_write_reg(omap, OMAP_I2C_IE_REG, omap->iestate);
314 }
315
316 static int omap_i2c_reset(struct omap_i2c_dev *omap)
317 {
318 unsigned long timeout;
319 u16 sysc;
320
321 if (omap->rev >= OMAP_I2C_OMAP1_REV_2) {
322 sysc = omap_i2c_read_reg(omap, OMAP_I2C_SYSC_REG);
323
324 /* Disable I2C controller before soft reset */
325 omap_i2c_write_reg(omap, OMAP_I2C_CON_REG,
326 omap_i2c_read_reg(omap, OMAP_I2C_CON_REG) &
327 ~(OMAP_I2C_CON_EN));
328
329 omap_i2c_write_reg(omap, OMAP_I2C_SYSC_REG, SYSC_SOFTRESET_MASK);
330 /* For some reason we need to set the EN bit before the
331 * reset done bit gets set. */
332 timeout = jiffies + OMAP_I2C_TIMEOUT;
333 omap_i2c_write_reg(omap, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
334 while (!(omap_i2c_read_reg(omap, OMAP_I2C_SYSS_REG) &
335 SYSS_RESETDONE_MASK)) {
336 if (time_after(jiffies, timeout)) {
337 dev_warn(omap->dev, "timeout waiting "
338 "for controller reset\n");
339 return -ETIMEDOUT;
340 }
341 msleep(1);
342 }
343
344 /* SYSC register is cleared by the reset; rewrite it */
345 omap_i2c_write_reg(omap, OMAP_I2C_SYSC_REG, sysc);
346
347 if (omap->rev > OMAP_I2C_REV_ON_3430_3530) {
348 /* Schedule I2C-bus monitoring on the next transfer */
349 omap->bb_valid = 0;
350 }
351 }
352
353 return 0;
354 }
355
356 static int omap_i2c_init(struct omap_i2c_dev *omap)
357 {
358 u16 psc = 0, scll = 0, sclh = 0;
359 u16 fsscll = 0, fssclh = 0, hsscll = 0, hssclh = 0;
360 unsigned long fclk_rate = 12000000;
361 unsigned long internal_clk = 0;
362 struct clk *fclk;
363 int error;
364
365 if (omap->rev >= OMAP_I2C_REV_ON_3430_3530) {
366 /*
367 * Enabling all wakup sources to stop I2C freezing on
368 * WFI instruction.
369 * REVISIT: Some wkup sources might not be needed.
370 */
371 omap->westate = OMAP_I2C_WE_ALL;
372 }
373
374 if (omap->flags & OMAP_I2C_FLAG_ALWAYS_ARMXOR_CLK) {
375 /*
376 * The I2C functional clock is the armxor_ck, so there's
377 * no need to get "armxor_ck" separately. Now, if OMAP2420
378 * always returns 12MHz for the functional clock, we can
379 * do this bit unconditionally.
380 */
381 fclk = clk_get(omap->dev, "fck");
382 if (IS_ERR(fclk)) {
383 error = PTR_ERR(fclk);
384 dev_err(omap->dev, "could not get fck: %i\n", error);
385
386 return error;
387 }
388
389 fclk_rate = clk_get_rate(fclk);
390 clk_put(fclk);
391
392 /* TRM for 5912 says the I2C clock must be prescaled to be
393 * between 7 - 12 MHz. The XOR input clock is typically
394 * 12, 13 or 19.2 MHz. So we should have code that produces:
395 *
396 * XOR MHz Divider Prescaler
397 * 12 1 0
398 * 13 2 1
399 * 19.2 2 1
400 */
401 if (fclk_rate > 12000000)
402 psc = fclk_rate / 12000000;
403 }
404
405 if (!(omap->flags & OMAP_I2C_FLAG_SIMPLE_CLOCK)) {
406
407 /*
408 * HSI2C controller internal clk rate should be 19.2 Mhz for
409 * HS and for all modes on 2430. On 34xx we can use lower rate
410 * to get longer filter period for better noise suppression.
411 * The filter is iclk (fclk for HS) period.
412 */
413 if (omap->speed > 400 ||
414 omap->flags & OMAP_I2C_FLAG_FORCE_19200_INT_CLK)
415 internal_clk = 19200;
416 else if (omap->speed > 100)
417 internal_clk = 9600;
418 else
419 internal_clk = 4000;
420 fclk = clk_get(omap->dev, "fck");
421 if (IS_ERR(fclk)) {
422 error = PTR_ERR(fclk);
423 dev_err(omap->dev, "could not get fck: %i\n", error);
424
425 return error;
426 }
427 fclk_rate = clk_get_rate(fclk) / 1000;
428 clk_put(fclk);
429
430 /* Compute prescaler divisor */
431 psc = fclk_rate / internal_clk;
432 psc = psc - 1;
433
434 /* If configured for High Speed */
435 if (omap->speed > 400) {
436 unsigned long scl;
437
438 /* For first phase of HS mode */
439 scl = internal_clk / 400;
440 fsscll = scl - (scl / 3) - 7;
441 fssclh = (scl / 3) - 5;
442
443 /* For second phase of HS mode */
444 scl = fclk_rate / omap->speed;
445 hsscll = scl - (scl / 3) - 7;
446 hssclh = (scl / 3) - 5;
447 } else if (omap->speed > 100) {
448 unsigned long scl;
449
450 /* Fast mode */
451 scl = internal_clk / omap->speed;
452 fsscll = scl - (scl / 3) - 7;
453 fssclh = (scl / 3) - 5;
454 } else {
455 /* Standard mode */
456 fsscll = internal_clk / (omap->speed * 2) - 7;
457 fssclh = internal_clk / (omap->speed * 2) - 5;
458 }
459 scll = (hsscll << OMAP_I2C_SCLL_HSSCLL) | fsscll;
460 sclh = (hssclh << OMAP_I2C_SCLH_HSSCLH) | fssclh;
461 } else {
462 /* Program desired operating rate */
463 fclk_rate /= (psc + 1) * 1000;
464 if (psc > 2)
465 psc = 2;
466 scll = fclk_rate / (omap->speed * 2) - 7 + psc;
467 sclh = fclk_rate / (omap->speed * 2) - 7 + psc;
468 }
469
470 omap->iestate = (OMAP_I2C_IE_XRDY | OMAP_I2C_IE_RRDY |
471 OMAP_I2C_IE_ARDY | OMAP_I2C_IE_NACK |
472 OMAP_I2C_IE_AL) | ((omap->fifo_size) ?
473 (OMAP_I2C_IE_RDR | OMAP_I2C_IE_XDR) : 0);
474
475 omap->pscstate = psc;
476 omap->scllstate = scll;
477 omap->sclhstate = sclh;
478
479 if (omap->rev <= OMAP_I2C_REV_ON_3430_3530) {
480 /* Not implemented */
481 omap->bb_valid = 1;
482 }
483
484 __omap_i2c_init(omap);
485
486 return 0;
487 }
488
489 /*
490 * Waiting on Bus Busy
491 */
492 static int omap_i2c_wait_for_bb(struct omap_i2c_dev *omap)
493 {
494 unsigned long timeout;
495
496 timeout = jiffies + OMAP_I2C_TIMEOUT;
497 while (omap_i2c_read_reg(omap, OMAP_I2C_STAT_REG) & OMAP_I2C_STAT_BB) {
498 if (time_after(jiffies, timeout))
499 return i2c_recover_bus(&omap->adapter);
500 msleep(1);
501 }
502
503 return 0;
504 }
505
506 /*
507 * Wait while BB-bit doesn't reflect the I2C bus state
508 *
509 * In a multimaster environment, after IP software reset, BB-bit value doesn't
510 * correspond to the current bus state. It may happen what BB-bit will be 0,
511 * while the bus is busy due to another I2C master activity.
512 * Here are BB-bit values after reset:
513 * SDA SCL BB NOTES
514 * 0 0 0 1, 2
515 * 1 0 0 1, 2
516 * 0 1 1
517 * 1 1 0 3
518 * Later, if IP detect SDA=0 and SCL=1 (ACK) or SDA 1->0 while SCL=1 (START)
519 * combinations on the bus, it set BB-bit to 1.
520 * If IP detect SDA 0->1 while SCL=1 (STOP) combination on the bus,
521 * it set BB-bit to 0 and BF to 1.
522 * BB and BF bits correctly tracks the bus state while IP is suspended
523 * BB bit became valid on the next FCLK clock after CON_EN bit set
524 *
525 * NOTES:
526 * 1. Any transfer started when BB=0 and bus is busy wouldn't be
527 * completed by IP and results in controller timeout.
528 * 2. Any transfer started when BB=0 and SCL=0 results in IP
529 * starting to drive SDA low. In that case IP corrupt data
530 * on the bus.
531 * 3. Any transfer started in the middle of another master's transfer
532 * results in unpredictable results and data corruption
533 */
534 static int omap_i2c_wait_for_bb_valid(struct omap_i2c_dev *omap)
535 {
536 unsigned long bus_free_timeout = 0;
537 unsigned long timeout;
538 int bus_free = 0;
539 u16 stat, systest;
540
541 if (omap->bb_valid)
542 return 0;
543
544 timeout = jiffies + OMAP_I2C_TIMEOUT;
545 while (1) {
546 stat = omap_i2c_read_reg(omap, OMAP_I2C_STAT_REG);
547 /*
548 * We will see BB or BF event in a case IP had detected any
549 * activity on the I2C bus. Now IP correctly tracks the bus
550 * state. BB-bit value is valid.
551 */
552 if (stat & (OMAP_I2C_STAT_BB | OMAP_I2C_STAT_BF))
553 break;
554
555 /*
556 * Otherwise, we must look signals on the bus to make
557 * the right decision.
558 */
559 systest = omap_i2c_read_reg(omap, OMAP_I2C_SYSTEST_REG);
560 if ((systest & OMAP_I2C_SYSTEST_SCL_I_FUNC) &&
561 (systest & OMAP_I2C_SYSTEST_SDA_I_FUNC)) {
562 if (!bus_free) {
563 bus_free_timeout = jiffies +
564 OMAP_I2C_BUS_FREE_TIMEOUT;
565 bus_free = 1;
566 }
567
568 /*
569 * SDA and SCL lines was high for 10 ms without bus
570 * activity detected. The bus is free. Consider
571 * BB-bit value is valid.
572 */
573 if (time_after(jiffies, bus_free_timeout))
574 break;
575 } else {
576 bus_free = 0;
577 }
578
579 if (time_after(jiffies, timeout)) {
580 dev_warn(omap->dev, "timeout waiting for bus ready\n");
581 return -ETIMEDOUT;
582 }
583
584 msleep(1);
585 }
586
587 omap->bb_valid = 1;
588 return 0;
589 }
590
591 static void omap_i2c_resize_fifo(struct omap_i2c_dev *omap, u8 size, bool is_rx)
592 {
593 u16 buf;
594
595 if (omap->flags & OMAP_I2C_FLAG_NO_FIFO)
596 return;
597
598 /*
599 * Set up notification threshold based on message size. We're doing
600 * this to try and avoid draining feature as much as possible. Whenever
601 * we have big messages to transfer (bigger than our total fifo size)
602 * then we might use draining feature to transfer the remaining bytes.
603 */
604
605 omap->threshold = clamp(size, (u8) 1, omap->fifo_size);
606
607 buf = omap_i2c_read_reg(omap, OMAP_I2C_BUF_REG);
608
609 if (is_rx) {
610 /* Clear RX Threshold */
611 buf &= ~(0x3f << 8);
612 buf |= ((omap->threshold - 1) << 8) | OMAP_I2C_BUF_RXFIF_CLR;
613 } else {
614 /* Clear TX Threshold */
615 buf &= ~0x3f;
616 buf |= (omap->threshold - 1) | OMAP_I2C_BUF_TXFIF_CLR;
617 }
618
619 omap_i2c_write_reg(omap, OMAP_I2C_BUF_REG, buf);
620
621 if (omap->rev < OMAP_I2C_REV_ON_3630)
622 omap->b_hw = 1; /* Enable hardware fixes */
623
624 /* calculate wakeup latency constraint for MPU */
625 if (omap->set_mpu_wkup_lat != NULL)
626 omap->latency = (1000000 * omap->threshold) /
627 (1000 * omap->speed / 8);
628 }
629
630 /*
631 * Low level master read/write transaction.
632 */
633 static int omap_i2c_xfer_msg(struct i2c_adapter *adap,
634 struct i2c_msg *msg, int stop)
635 {
636 struct omap_i2c_dev *omap = i2c_get_adapdata(adap);
637 unsigned long timeout;
638 u16 w;
639
640 dev_dbg(omap->dev, "addr: 0x%04x, len: %d, flags: 0x%x, stop: %d\n",
641 msg->addr, msg->len, msg->flags, stop);
642
643 if (msg->len == 0)
644 return -EINVAL;
645
646 omap->receiver = !!(msg->flags & I2C_M_RD);
647 omap_i2c_resize_fifo(omap, msg->len, omap->receiver);
648
649 omap_i2c_write_reg(omap, OMAP_I2C_SA_REG, msg->addr);
650
651 /* REVISIT: Could the STB bit of I2C_CON be used with probing? */
652 omap->buf = msg->buf;
653 omap->buf_len = msg->len;
654
655 /* make sure writes to omap->buf_len are ordered */
656 barrier();
657
658 omap_i2c_write_reg(omap, OMAP_I2C_CNT_REG, omap->buf_len);
659
660 /* Clear the FIFO Buffers */
661 w = omap_i2c_read_reg(omap, OMAP_I2C_BUF_REG);
662 w |= OMAP_I2C_BUF_RXFIF_CLR | OMAP_I2C_BUF_TXFIF_CLR;
663 omap_i2c_write_reg(omap, OMAP_I2C_BUF_REG, w);
664
665 reinit_completion(&omap->cmd_complete);
666 omap->cmd_err = 0;
667
668 w = OMAP_I2C_CON_EN | OMAP_I2C_CON_MST | OMAP_I2C_CON_STT;
669
670 /* High speed configuration */
671 if (omap->speed > 400)
672 w |= OMAP_I2C_CON_OPMODE_HS;
673
674 if (msg->flags & I2C_M_STOP)
675 stop = 1;
676 if (msg->flags & I2C_M_TEN)
677 w |= OMAP_I2C_CON_XA;
678 if (!(msg->flags & I2C_M_RD))
679 w |= OMAP_I2C_CON_TRX;
680
681 if (!omap->b_hw && stop)
682 w |= OMAP_I2C_CON_STP;
683 /*
684 * NOTE: STAT_BB bit could became 1 here if another master occupy
685 * the bus. IP successfully complete transfer when the bus will be
686 * free again (BB reset to 0).
687 */
688 omap_i2c_write_reg(omap, OMAP_I2C_CON_REG, w);
689
690 /*
691 * Don't write stt and stp together on some hardware.
692 */
693 if (omap->b_hw && stop) {
694 unsigned long delay = jiffies + OMAP_I2C_TIMEOUT;
695 u16 con = omap_i2c_read_reg(omap, OMAP_I2C_CON_REG);
696 while (con & OMAP_I2C_CON_STT) {
697 con = omap_i2c_read_reg(omap, OMAP_I2C_CON_REG);
698
699 /* Let the user know if i2c is in a bad state */
700 if (time_after(jiffies, delay)) {
701 dev_err(omap->dev, "controller timed out "
702 "waiting for start condition to finish\n");
703 return -ETIMEDOUT;
704 }
705 cpu_relax();
706 }
707
708 w |= OMAP_I2C_CON_STP;
709 w &= ~OMAP_I2C_CON_STT;
710 omap_i2c_write_reg(omap, OMAP_I2C_CON_REG, w);
711 }
712
713 /*
714 * REVISIT: We should abort the transfer on signals, but the bus goes
715 * into arbitration and we're currently unable to recover from it.
716 */
717 timeout = wait_for_completion_timeout(&omap->cmd_complete,
718 OMAP_I2C_TIMEOUT);
719 if (timeout == 0) {
720 dev_err(omap->dev, "controller timed out\n");
721 omap_i2c_reset(omap);
722 __omap_i2c_init(omap);
723 return -ETIMEDOUT;
724 }
725
726 if (likely(!omap->cmd_err))
727 return 0;
728
729 /* We have an error */
730 if (omap->cmd_err & (OMAP_I2C_STAT_ROVR | OMAP_I2C_STAT_XUDF)) {
731 omap_i2c_reset(omap);
732 __omap_i2c_init(omap);
733 return -EIO;
734 }
735
736 if (omap->cmd_err & OMAP_I2C_STAT_AL)
737 return -EAGAIN;
738
739 if (omap->cmd_err & OMAP_I2C_STAT_NACK) {
740 if (msg->flags & I2C_M_IGNORE_NAK)
741 return 0;
742
743 w = omap_i2c_read_reg(omap, OMAP_I2C_CON_REG);
744 w |= OMAP_I2C_CON_STP;
745 omap_i2c_write_reg(omap, OMAP_I2C_CON_REG, w);
746 return -EREMOTEIO;
747 }
748 return -EIO;
749 }
750
751
752 /*
753 * Prepare controller for a transaction and call omap_i2c_xfer_msg
754 * to do the work during IRQ processing.
755 */
756 static int
757 omap_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
758 {
759 struct omap_i2c_dev *omap = i2c_get_adapdata(adap);
760 int i;
761 int r;
762
763 r = pm_runtime_get_sync(omap->dev);
764 if (r < 0)
765 goto out;
766
767 r = omap_i2c_wait_for_bb_valid(omap);
768 if (r < 0)
769 goto out;
770
771 r = omap_i2c_wait_for_bb(omap);
772 if (r < 0)
773 goto out;
774
775 if (omap->set_mpu_wkup_lat != NULL)
776 omap->set_mpu_wkup_lat(omap->dev, omap->latency);
777
778 for (i = 0; i < num; i++) {
779 r = omap_i2c_xfer_msg(adap, &msgs[i], (i == (num - 1)));
780 if (r != 0)
781 break;
782 }
783
784 if (r == 0)
785 r = num;
786
787 omap_i2c_wait_for_bb(omap);
788
789 if (omap->set_mpu_wkup_lat != NULL)
790 omap->set_mpu_wkup_lat(omap->dev, -1);
791
792 out:
793 pm_runtime_mark_last_busy(omap->dev);
794 pm_runtime_put_autosuspend(omap->dev);
795 return r;
796 }
797
798 static u32
799 omap_i2c_func(struct i2c_adapter *adap)
800 {
801 return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK) |
802 I2C_FUNC_PROTOCOL_MANGLING;
803 }
804
805 static inline void
806 omap_i2c_complete_cmd(struct omap_i2c_dev *omap, u16 err)
807 {
808 omap->cmd_err |= err;
809 complete(&omap->cmd_complete);
810 }
811
812 static inline void
813 omap_i2c_ack_stat(struct omap_i2c_dev *omap, u16 stat)
814 {
815 omap_i2c_write_reg(omap, OMAP_I2C_STAT_REG, stat);
816 }
817
818 static inline void i2c_omap_errata_i207(struct omap_i2c_dev *omap, u16 stat)
819 {
820 /*
821 * I2C Errata(Errata Nos. OMAP2: 1.67, OMAP3: 1.8)
822 * Not applicable for OMAP4.
823 * Under certain rare conditions, RDR could be set again
824 * when the bus is busy, then ignore the interrupt and
825 * clear the interrupt.
826 */
827 if (stat & OMAP_I2C_STAT_RDR) {
828 /* Step 1: If RDR is set, clear it */
829 omap_i2c_ack_stat(omap, OMAP_I2C_STAT_RDR);
830
831 /* Step 2: */
832 if (!(omap_i2c_read_reg(omap, OMAP_I2C_STAT_REG)
833 & OMAP_I2C_STAT_BB)) {
834
835 /* Step 3: */
836 if (omap_i2c_read_reg(omap, OMAP_I2C_STAT_REG)
837 & OMAP_I2C_STAT_RDR) {
838 omap_i2c_ack_stat(omap, OMAP_I2C_STAT_RDR);
839 dev_dbg(omap->dev, "RDR when bus is busy.\n");
840 }
841
842 }
843 }
844 }
845
846 /* rev1 devices are apparently only on some 15xx */
847 #ifdef CONFIG_ARCH_OMAP15XX
848
849 static irqreturn_t
850 omap_i2c_omap1_isr(int this_irq, void *dev_id)
851 {
852 struct omap_i2c_dev *omap = dev_id;
853 u16 iv, w;
854
855 if (pm_runtime_suspended(omap->dev))
856 return IRQ_NONE;
857
858 iv = omap_i2c_read_reg(omap, OMAP_I2C_IV_REG);
859 switch (iv) {
860 case 0x00: /* None */
861 break;
862 case 0x01: /* Arbitration lost */
863 dev_err(omap->dev, "Arbitration lost\n");
864 omap_i2c_complete_cmd(omap, OMAP_I2C_STAT_AL);
865 break;
866 case 0x02: /* No acknowledgement */
867 omap_i2c_complete_cmd(omap, OMAP_I2C_STAT_NACK);
868 omap_i2c_write_reg(omap, OMAP_I2C_CON_REG, OMAP_I2C_CON_STP);
869 break;
870 case 0x03: /* Register access ready */
871 omap_i2c_complete_cmd(omap, 0);
872 break;
873 case 0x04: /* Receive data ready */
874 if (omap->buf_len) {
875 w = omap_i2c_read_reg(omap, OMAP_I2C_DATA_REG);
876 *omap->buf++ = w;
877 omap->buf_len--;
878 if (omap->buf_len) {
879 *omap->buf++ = w >> 8;
880 omap->buf_len--;
881 }
882 } else
883 dev_err(omap->dev, "RRDY IRQ while no data requested\n");
884 break;
885 case 0x05: /* Transmit data ready */
886 if (omap->buf_len) {
887 w = *omap->buf++;
888 omap->buf_len--;
889 if (omap->buf_len) {
890 w |= *omap->buf++ << 8;
891 omap->buf_len--;
892 }
893 omap_i2c_write_reg(omap, OMAP_I2C_DATA_REG, w);
894 } else
895 dev_err(omap->dev, "XRDY IRQ while no data to send\n");
896 break;
897 default:
898 return IRQ_NONE;
899 }
900
901 return IRQ_HANDLED;
902 }
903 #else
904 #define omap_i2c_omap1_isr NULL
905 #endif
906
907 /*
908 * OMAP3430 Errata i462: When an XRDY/XDR is hit, wait for XUDF before writing
909 * data to DATA_REG. Otherwise some data bytes can be lost while transferring
910 * them from the memory to the I2C interface.
911 */
912 static int errata_omap3_i462(struct omap_i2c_dev *omap)
913 {
914 unsigned long timeout = 10000;
915 u16 stat;
916
917 do {
918 stat = omap_i2c_read_reg(omap, OMAP_I2C_STAT_REG);
919 if (stat & OMAP_I2C_STAT_XUDF)
920 break;
921
922 if (stat & (OMAP_I2C_STAT_NACK | OMAP_I2C_STAT_AL)) {
923 omap_i2c_ack_stat(omap, (OMAP_I2C_STAT_XRDY |
924 OMAP_I2C_STAT_XDR));
925 if (stat & OMAP_I2C_STAT_NACK) {
926 omap->cmd_err |= OMAP_I2C_STAT_NACK;
927 omap_i2c_ack_stat(omap, OMAP_I2C_STAT_NACK);
928 }
929
930 if (stat & OMAP_I2C_STAT_AL) {
931 dev_err(omap->dev, "Arbitration lost\n");
932 omap->cmd_err |= OMAP_I2C_STAT_AL;
933 omap_i2c_ack_stat(omap, OMAP_I2C_STAT_AL);
934 }
935
936 return -EIO;
937 }
938
939 cpu_relax();
940 } while (--timeout);
941
942 if (!timeout) {
943 dev_err(omap->dev, "timeout waiting on XUDF bit\n");
944 return 0;
945 }
946
947 return 0;
948 }
949
950 static void omap_i2c_receive_data(struct omap_i2c_dev *omap, u8 num_bytes,
951 bool is_rdr)
952 {
953 u16 w;
954
955 while (num_bytes--) {
956 w = omap_i2c_read_reg(omap, OMAP_I2C_DATA_REG);
957 *omap->buf++ = w;
958 omap->buf_len--;
959
960 /*
961 * Data reg in 2430, omap3 and
962 * omap4 is 8 bit wide
963 */
964 if (omap->flags & OMAP_I2C_FLAG_16BIT_DATA_REG) {
965 *omap->buf++ = w >> 8;
966 omap->buf_len--;
967 }
968 }
969 }
970
971 static int omap_i2c_transmit_data(struct omap_i2c_dev *omap, u8 num_bytes,
972 bool is_xdr)
973 {
974 u16 w;
975
976 while (num_bytes--) {
977 w = *omap->buf++;
978 omap->buf_len--;
979
980 /*
981 * Data reg in 2430, omap3 and
982 * omap4 is 8 bit wide
983 */
984 if (omap->flags & OMAP_I2C_FLAG_16BIT_DATA_REG) {
985 w |= *omap->buf++ << 8;
986 omap->buf_len--;
987 }
988
989 if (omap->errata & I2C_OMAP_ERRATA_I462) {
990 int ret;
991
992 ret = errata_omap3_i462(omap);
993 if (ret < 0)
994 return ret;
995 }
996
997 omap_i2c_write_reg(omap, OMAP_I2C_DATA_REG, w);
998 }
999
1000 return 0;
1001 }
1002
1003 static irqreturn_t
1004 omap_i2c_isr(int irq, void *dev_id)
1005 {
1006 struct omap_i2c_dev *omap = dev_id;
1007 irqreturn_t ret = IRQ_HANDLED;
1008 u16 mask;
1009 u16 stat;
1010
1011 stat = omap_i2c_read_reg(omap, OMAP_I2C_STAT_REG);
1012 mask = omap_i2c_read_reg(omap, OMAP_I2C_IE_REG);
1013
1014 if (stat & mask)
1015 ret = IRQ_WAKE_THREAD;
1016
1017 return ret;
1018 }
1019
1020 static irqreturn_t
1021 omap_i2c_isr_thread(int this_irq, void *dev_id)
1022 {
1023 struct omap_i2c_dev *omap = dev_id;
1024 u16 bits;
1025 u16 stat;
1026 int err = 0, count = 0;
1027
1028 do {
1029 bits = omap_i2c_read_reg(omap, OMAP_I2C_IE_REG);
1030 stat = omap_i2c_read_reg(omap, OMAP_I2C_STAT_REG);
1031 stat &= bits;
1032
1033 /* If we're in receiver mode, ignore XDR/XRDY */
1034 if (omap->receiver)
1035 stat &= ~(OMAP_I2C_STAT_XDR | OMAP_I2C_STAT_XRDY);
1036 else
1037 stat &= ~(OMAP_I2C_STAT_RDR | OMAP_I2C_STAT_RRDY);
1038
1039 if (!stat) {
1040 /* my work here is done */
1041 goto out;
1042 }
1043
1044 dev_dbg(omap->dev, "IRQ (ISR = 0x%04x)\n", stat);
1045 if (count++ == 100) {
1046 dev_warn(omap->dev, "Too much work in one IRQ\n");
1047 break;
1048 }
1049
1050 if (stat & OMAP_I2C_STAT_NACK) {
1051 err |= OMAP_I2C_STAT_NACK;
1052 omap_i2c_ack_stat(omap, OMAP_I2C_STAT_NACK);
1053 }
1054
1055 if (stat & OMAP_I2C_STAT_AL) {
1056 dev_err(omap->dev, "Arbitration lost\n");
1057 err |= OMAP_I2C_STAT_AL;
1058 omap_i2c_ack_stat(omap, OMAP_I2C_STAT_AL);
1059 }
1060
1061 /*
1062 * ProDB0017052: Clear ARDY bit twice
1063 */
1064 if (stat & OMAP_I2C_STAT_ARDY)
1065 omap_i2c_ack_stat(omap, OMAP_I2C_STAT_ARDY);
1066
1067 if (stat & (OMAP_I2C_STAT_ARDY | OMAP_I2C_STAT_NACK |
1068 OMAP_I2C_STAT_AL)) {
1069 omap_i2c_ack_stat(omap, (OMAP_I2C_STAT_RRDY |
1070 OMAP_I2C_STAT_RDR |
1071 OMAP_I2C_STAT_XRDY |
1072 OMAP_I2C_STAT_XDR |
1073 OMAP_I2C_STAT_ARDY));
1074 break;
1075 }
1076
1077 if (stat & OMAP_I2C_STAT_RDR) {
1078 u8 num_bytes = 1;
1079
1080 if (omap->fifo_size)
1081 num_bytes = omap->buf_len;
1082
1083 if (omap->errata & I2C_OMAP_ERRATA_I207) {
1084 i2c_omap_errata_i207(omap, stat);
1085 num_bytes = (omap_i2c_read_reg(omap,
1086 OMAP_I2C_BUFSTAT_REG) >> 8) & 0x3F;
1087 }
1088
1089 omap_i2c_receive_data(omap, num_bytes, true);
1090 omap_i2c_ack_stat(omap, OMAP_I2C_STAT_RDR);
1091 continue;
1092 }
1093
1094 if (stat & OMAP_I2C_STAT_RRDY) {
1095 u8 num_bytes = 1;
1096
1097 if (omap->threshold)
1098 num_bytes = omap->threshold;
1099
1100 omap_i2c_receive_data(omap, num_bytes, false);
1101 omap_i2c_ack_stat(omap, OMAP_I2C_STAT_RRDY);
1102 continue;
1103 }
1104
1105 if (stat & OMAP_I2C_STAT_XDR) {
1106 u8 num_bytes = 1;
1107 int ret;
1108
1109 if (omap->fifo_size)
1110 num_bytes = omap->buf_len;
1111
1112 ret = omap_i2c_transmit_data(omap, num_bytes, true);
1113 if (ret < 0)
1114 break;
1115
1116 omap_i2c_ack_stat(omap, OMAP_I2C_STAT_XDR);
1117 continue;
1118 }
1119
1120 if (stat & OMAP_I2C_STAT_XRDY) {
1121 u8 num_bytes = 1;
1122 int ret;
1123
1124 if (omap->threshold)
1125 num_bytes = omap->threshold;
1126
1127 ret = omap_i2c_transmit_data(omap, num_bytes, false);
1128 if (ret < 0)
1129 break;
1130
1131 omap_i2c_ack_stat(omap, OMAP_I2C_STAT_XRDY);
1132 continue;
1133 }
1134
1135 if (stat & OMAP_I2C_STAT_ROVR) {
1136 dev_err(omap->dev, "Receive overrun\n");
1137 err |= OMAP_I2C_STAT_ROVR;
1138 omap_i2c_ack_stat(omap, OMAP_I2C_STAT_ROVR);
1139 break;
1140 }
1141
1142 if (stat & OMAP_I2C_STAT_XUDF) {
1143 dev_err(omap->dev, "Transmit underflow\n");
1144 err |= OMAP_I2C_STAT_XUDF;
1145 omap_i2c_ack_stat(omap, OMAP_I2C_STAT_XUDF);
1146 break;
1147 }
1148 } while (stat);
1149
1150 omap_i2c_complete_cmd(omap, err);
1151
1152 out:
1153 return IRQ_HANDLED;
1154 }
1155
1156 static const struct i2c_algorithm omap_i2c_algo = {
1157 .master_xfer = omap_i2c_xfer,
1158 .functionality = omap_i2c_func,
1159 };
1160
1161 #ifdef CONFIG_OF
1162 static struct omap_i2c_bus_platform_data omap2420_pdata = {
1163 .rev = OMAP_I2C_IP_VERSION_1,
1164 .flags = OMAP_I2C_FLAG_NO_FIFO |
1165 OMAP_I2C_FLAG_SIMPLE_CLOCK |
1166 OMAP_I2C_FLAG_16BIT_DATA_REG |
1167 OMAP_I2C_FLAG_BUS_SHIFT_2,
1168 };
1169
1170 static struct omap_i2c_bus_platform_data omap2430_pdata = {
1171 .rev = OMAP_I2C_IP_VERSION_1,
1172 .flags = OMAP_I2C_FLAG_BUS_SHIFT_2 |
1173 OMAP_I2C_FLAG_FORCE_19200_INT_CLK,
1174 };
1175
1176 static struct omap_i2c_bus_platform_data omap3_pdata = {
1177 .rev = OMAP_I2C_IP_VERSION_1,
1178 .flags = OMAP_I2C_FLAG_BUS_SHIFT_2,
1179 };
1180
1181 static struct omap_i2c_bus_platform_data omap4_pdata = {
1182 .rev = OMAP_I2C_IP_VERSION_2,
1183 };
1184
1185 static const struct of_device_id omap_i2c_of_match[] = {
1186 {
1187 .compatible = "ti,omap4-i2c",
1188 .data = &omap4_pdata,
1189 },
1190 {
1191 .compatible = "ti,omap3-i2c",
1192 .data = &omap3_pdata,
1193 },
1194 {
1195 .compatible = "ti,omap2430-i2c",
1196 .data = &omap2430_pdata,
1197 },
1198 {
1199 .compatible = "ti,omap2420-i2c",
1200 .data = &omap2420_pdata,
1201 },
1202 { },
1203 };
1204 MODULE_DEVICE_TABLE(of, omap_i2c_of_match);
1205 #endif
1206
1207 #define OMAP_I2C_SCHEME(rev) ((rev & 0xc000) >> 14)
1208
1209 #define OMAP_I2C_REV_SCHEME_0_MAJOR(rev) (rev >> 4)
1210 #define OMAP_I2C_REV_SCHEME_0_MINOR(rev) (rev & 0xf)
1211
1212 #define OMAP_I2C_REV_SCHEME_1_MAJOR(rev) ((rev & 0x0700) >> 7)
1213 #define OMAP_I2C_REV_SCHEME_1_MINOR(rev) (rev & 0x1f)
1214 #define OMAP_I2C_SCHEME_0 0
1215 #define OMAP_I2C_SCHEME_1 1
1216
1217 static int omap_i2c_get_scl(struct i2c_adapter *adap)
1218 {
1219 struct omap_i2c_dev *dev = i2c_get_adapdata(adap);
1220 u32 reg;
1221
1222 reg = omap_i2c_read_reg(dev, OMAP_I2C_SYSTEST_REG);
1223
1224 return reg & OMAP_I2C_SYSTEST_SCL_I_FUNC;
1225 }
1226
1227 static int omap_i2c_get_sda(struct i2c_adapter *adap)
1228 {
1229 struct omap_i2c_dev *dev = i2c_get_adapdata(adap);
1230 u32 reg;
1231
1232 reg = omap_i2c_read_reg(dev, OMAP_I2C_SYSTEST_REG);
1233
1234 return reg & OMAP_I2C_SYSTEST_SDA_I_FUNC;
1235 }
1236
1237 static void omap_i2c_set_scl(struct i2c_adapter *adap, int val)
1238 {
1239 struct omap_i2c_dev *dev = i2c_get_adapdata(adap);
1240 u32 reg;
1241
1242 reg = omap_i2c_read_reg(dev, OMAP_I2C_SYSTEST_REG);
1243 if (val)
1244 reg |= OMAP_I2C_SYSTEST_SCL_O;
1245 else
1246 reg &= ~OMAP_I2C_SYSTEST_SCL_O;
1247 omap_i2c_write_reg(dev, OMAP_I2C_SYSTEST_REG, reg);
1248 }
1249
1250 static void omap_i2c_prepare_recovery(struct i2c_adapter *adap)
1251 {
1252 struct omap_i2c_dev *dev = i2c_get_adapdata(adap);
1253 u32 reg;
1254
1255 reg = omap_i2c_read_reg(dev, OMAP_I2C_SYSTEST_REG);
1256 /* enable test mode */
1257 reg |= OMAP_I2C_SYSTEST_ST_EN;
1258 /* select SDA/SCL IO mode */
1259 reg |= 3 << OMAP_I2C_SYSTEST_TMODE_SHIFT;
1260 /* set SCL to high-impedance state (reset value is 0) */
1261 reg |= OMAP_I2C_SYSTEST_SCL_O;
1262 /* set SDA to high-impedance state (reset value is 0) */
1263 reg |= OMAP_I2C_SYSTEST_SDA_O;
1264 omap_i2c_write_reg(dev, OMAP_I2C_SYSTEST_REG, reg);
1265 }
1266
1267 static void omap_i2c_unprepare_recovery(struct i2c_adapter *adap)
1268 {
1269 struct omap_i2c_dev *dev = i2c_get_adapdata(adap);
1270 u32 reg;
1271
1272 reg = omap_i2c_read_reg(dev, OMAP_I2C_SYSTEST_REG);
1273 /* restore reset values */
1274 reg &= ~OMAP_I2C_SYSTEST_ST_EN;
1275 reg &= ~OMAP_I2C_SYSTEST_TMODE_MASK;
1276 reg &= ~OMAP_I2C_SYSTEST_SCL_O;
1277 reg &= ~OMAP_I2C_SYSTEST_SDA_O;
1278 omap_i2c_write_reg(dev, OMAP_I2C_SYSTEST_REG, reg);
1279 }
1280
1281 static struct i2c_bus_recovery_info omap_i2c_bus_recovery_info = {
1282 .get_scl = omap_i2c_get_scl,
1283 .get_sda = omap_i2c_get_sda,
1284 .set_scl = omap_i2c_set_scl,
1285 .prepare_recovery = omap_i2c_prepare_recovery,
1286 .unprepare_recovery = omap_i2c_unprepare_recovery,
1287 .recover_bus = i2c_generic_scl_recovery,
1288 };
1289
1290 static int
1291 omap_i2c_probe(struct platform_device *pdev)
1292 {
1293 struct omap_i2c_dev *omap;
1294 struct i2c_adapter *adap;
1295 struct resource *mem;
1296 const struct omap_i2c_bus_platform_data *pdata =
1297 dev_get_platdata(&pdev->dev);
1298 struct device_node *node = pdev->dev.of_node;
1299 const struct of_device_id *match;
1300 int irq;
1301 int r;
1302 u32 rev;
1303 u16 minor, major;
1304
1305 irq = platform_get_irq(pdev, 0);
1306 if (irq < 0) {
1307 dev_err(&pdev->dev, "no irq resource?\n");
1308 return irq;
1309 }
1310
1311 omap = devm_kzalloc(&pdev->dev, sizeof(struct omap_i2c_dev), GFP_KERNEL);
1312 if (!omap)
1313 return -ENOMEM;
1314
1315 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1316 omap->base = devm_ioremap_resource(&pdev->dev, mem);
1317 if (IS_ERR(omap->base))
1318 return PTR_ERR(omap->base);
1319
1320 match = of_match_device(of_match_ptr(omap_i2c_of_match), &pdev->dev);
1321 if (match) {
1322 u32 freq = 100000; /* default to 100000 Hz */
1323
1324 pdata = match->data;
1325 omap->flags = pdata->flags;
1326
1327 of_property_read_u32(node, "clock-frequency", &freq);
1328 /* convert DT freq value in Hz into kHz for speed */
1329 omap->speed = freq / 1000;
1330 } else if (pdata != NULL) {
1331 omap->speed = pdata->clkrate;
1332 omap->flags = pdata->flags;
1333 omap->set_mpu_wkup_lat = pdata->set_mpu_wkup_lat;
1334 }
1335
1336 omap->dev = &pdev->dev;
1337 omap->irq = irq;
1338
1339 platform_set_drvdata(pdev, omap);
1340 init_completion(&omap->cmd_complete);
1341
1342 omap->reg_shift = (omap->flags >> OMAP_I2C_FLAG_BUS_SHIFT__SHIFT) & 3;
1343
1344 pm_runtime_enable(omap->dev);
1345 pm_runtime_set_autosuspend_delay(omap->dev, OMAP_I2C_PM_TIMEOUT);
1346 pm_runtime_use_autosuspend(omap->dev);
1347
1348 r = pm_runtime_get_sync(omap->dev);
1349 if (r < 0)
1350 goto err_free_mem;
1351
1352 /*
1353 * Read the Rev hi bit-[15:14] ie scheme this is 1 indicates ver2.
1354 * On omap1/3/2 Offset 4 is IE Reg the bit [15:14] is 0 at reset.
1355 * Also since the omap_i2c_read_reg uses reg_map_ip_* a
1356 * readw_relaxed is done.
1357 */
1358 rev = readw_relaxed(omap->base + 0x04);
1359
1360 omap->scheme = OMAP_I2C_SCHEME(rev);
1361 switch (omap->scheme) {
1362 case OMAP_I2C_SCHEME_0:
1363 omap->regs = (u8 *)reg_map_ip_v1;
1364 omap->rev = omap_i2c_read_reg(omap, OMAP_I2C_REV_REG);
1365 minor = OMAP_I2C_REV_SCHEME_0_MAJOR(omap->rev);
1366 major = OMAP_I2C_REV_SCHEME_0_MAJOR(omap->rev);
1367 break;
1368 case OMAP_I2C_SCHEME_1:
1369 /* FALLTHROUGH */
1370 default:
1371 omap->regs = (u8 *)reg_map_ip_v2;
1372 rev = (rev << 16) |
1373 omap_i2c_read_reg(omap, OMAP_I2C_IP_V2_REVNB_LO);
1374 minor = OMAP_I2C_REV_SCHEME_1_MINOR(rev);
1375 major = OMAP_I2C_REV_SCHEME_1_MAJOR(rev);
1376 omap->rev = rev;
1377 }
1378
1379 omap->errata = 0;
1380
1381 if (omap->rev >= OMAP_I2C_REV_ON_2430 &&
1382 omap->rev < OMAP_I2C_REV_ON_4430_PLUS)
1383 omap->errata |= I2C_OMAP_ERRATA_I207;
1384
1385 if (omap->rev <= OMAP_I2C_REV_ON_3430_3530)
1386 omap->errata |= I2C_OMAP_ERRATA_I462;
1387
1388 if (!(omap->flags & OMAP_I2C_FLAG_NO_FIFO)) {
1389 u16 s;
1390
1391 /* Set up the fifo size - Get total size */
1392 s = (omap_i2c_read_reg(omap, OMAP_I2C_BUFSTAT_REG) >> 14) & 0x3;
1393 omap->fifo_size = 0x8 << s;
1394
1395 /*
1396 * Set up notification threshold as half the total available
1397 * size. This is to ensure that we can handle the status on int
1398 * call back latencies.
1399 */
1400
1401 omap->fifo_size = (omap->fifo_size / 2);
1402
1403 if (omap->rev < OMAP_I2C_REV_ON_3630)
1404 omap->b_hw = 1; /* Enable hardware fixes */
1405
1406 /* calculate wakeup latency constraint for MPU */
1407 if (omap->set_mpu_wkup_lat != NULL)
1408 omap->latency = (1000000 * omap->fifo_size) /
1409 (1000 * omap->speed / 8);
1410 }
1411
1412 /* reset ASAP, clearing any IRQs */
1413 omap_i2c_init(omap);
1414
1415 if (omap->rev < OMAP_I2C_OMAP1_REV_2)
1416 r = devm_request_irq(&pdev->dev, omap->irq, omap_i2c_omap1_isr,
1417 IRQF_NO_SUSPEND, pdev->name, omap);
1418 else
1419 r = devm_request_threaded_irq(&pdev->dev, omap->irq,
1420 omap_i2c_isr, omap_i2c_isr_thread,
1421 IRQF_NO_SUSPEND | IRQF_ONESHOT,
1422 pdev->name, omap);
1423
1424 if (r) {
1425 dev_err(omap->dev, "failure requesting irq %i\n", omap->irq);
1426 goto err_unuse_clocks;
1427 }
1428
1429 adap = &omap->adapter;
1430 i2c_set_adapdata(adap, omap);
1431 adap->owner = THIS_MODULE;
1432 adap->class = I2C_CLASS_DEPRECATED;
1433 strlcpy(adap->name, "OMAP I2C adapter", sizeof(adap->name));
1434 adap->algo = &omap_i2c_algo;
1435 adap->dev.parent = &pdev->dev;
1436 adap->dev.of_node = pdev->dev.of_node;
1437 adap->bus_recovery_info = &omap_i2c_bus_recovery_info;
1438
1439 /* i2c device drivers may be active on return from add_adapter() */
1440 adap->nr = pdev->id;
1441 r = i2c_add_numbered_adapter(adap);
1442 if (r)
1443 goto err_unuse_clocks;
1444
1445 dev_info(omap->dev, "bus %d rev%d.%d at %d kHz\n", adap->nr,
1446 major, minor, omap->speed);
1447
1448 pm_runtime_mark_last_busy(omap->dev);
1449 pm_runtime_put_autosuspend(omap->dev);
1450
1451 return 0;
1452
1453 err_unuse_clocks:
1454 omap_i2c_write_reg(omap, OMAP_I2C_CON_REG, 0);
1455 pm_runtime_dont_use_autosuspend(omap->dev);
1456 pm_runtime_put_sync(omap->dev);
1457 pm_runtime_disable(&pdev->dev);
1458 err_free_mem:
1459
1460 return r;
1461 }
1462
1463 static int omap_i2c_remove(struct platform_device *pdev)
1464 {
1465 struct omap_i2c_dev *omap = platform_get_drvdata(pdev);
1466 int ret;
1467
1468 i2c_del_adapter(&omap->adapter);
1469 ret = pm_runtime_get_sync(&pdev->dev);
1470 if (ret < 0)
1471 return ret;
1472
1473 omap_i2c_write_reg(omap, OMAP_I2C_CON_REG, 0);
1474 pm_runtime_dont_use_autosuspend(&pdev->dev);
1475 pm_runtime_put_sync(&pdev->dev);
1476 pm_runtime_disable(&pdev->dev);
1477 return 0;
1478 }
1479
1480 #ifdef CONFIG_PM
1481 static int omap_i2c_runtime_suspend(struct device *dev)
1482 {
1483 struct omap_i2c_dev *omap = dev_get_drvdata(dev);
1484
1485 omap->iestate = omap_i2c_read_reg(omap, OMAP_I2C_IE_REG);
1486
1487 if (omap->scheme == OMAP_I2C_SCHEME_0)
1488 omap_i2c_write_reg(omap, OMAP_I2C_IE_REG, 0);
1489 else
1490 omap_i2c_write_reg(omap, OMAP_I2C_IP_V2_IRQENABLE_CLR,
1491 OMAP_I2C_IP_V2_INTERRUPTS_MASK);
1492
1493 if (omap->rev < OMAP_I2C_OMAP1_REV_2) {
1494 omap_i2c_read_reg(omap, OMAP_I2C_IV_REG); /* Read clears */
1495 } else {
1496 omap_i2c_write_reg(omap, OMAP_I2C_STAT_REG, omap->iestate);
1497
1498 /* Flush posted write */
1499 omap_i2c_read_reg(omap, OMAP_I2C_STAT_REG);
1500 }
1501
1502 pinctrl_pm_select_sleep_state(dev);
1503
1504 return 0;
1505 }
1506
1507 static int omap_i2c_runtime_resume(struct device *dev)
1508 {
1509 struct omap_i2c_dev *omap = dev_get_drvdata(dev);
1510
1511 pinctrl_pm_select_default_state(dev);
1512
1513 if (!omap->regs)
1514 return 0;
1515
1516 __omap_i2c_init(omap);
1517
1518 return 0;
1519 }
1520
1521 static const struct dev_pm_ops omap_i2c_pm_ops = {
1522 SET_RUNTIME_PM_OPS(omap_i2c_runtime_suspend,
1523 omap_i2c_runtime_resume, NULL)
1524 };
1525 #define OMAP_I2C_PM_OPS (&omap_i2c_pm_ops)
1526 #else
1527 #define OMAP_I2C_PM_OPS NULL
1528 #endif /* CONFIG_PM */
1529
1530 static struct platform_driver omap_i2c_driver = {
1531 .probe = omap_i2c_probe,
1532 .remove = omap_i2c_remove,
1533 .driver = {
1534 .name = "omap_i2c",
1535 .pm = OMAP_I2C_PM_OPS,
1536 .of_match_table = of_match_ptr(omap_i2c_of_match),
1537 },
1538 };
1539
1540 /* I2C may be needed to bring up other drivers */
1541 static int __init
1542 omap_i2c_init_driver(void)
1543 {
1544 return platform_driver_register(&omap_i2c_driver);
1545 }
1546 subsys_initcall(omap_i2c_init_driver);
1547
1548 static void __exit omap_i2c_exit_driver(void)
1549 {
1550 platform_driver_unregister(&omap_i2c_driver);
1551 }
1552 module_exit(omap_i2c_exit_driver);
1553
1554 MODULE_AUTHOR("MontaVista Software, Inc. (and others)");
1555 MODULE_DESCRIPTION("TI OMAP I2C bus adapter");
1556 MODULE_LICENSE("GPL");
1557 MODULE_ALIAS("platform:omap_i2c");
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