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[mirror_ubuntu-artful-kernel.git] / drivers / i2c / busses / i2c-omap.c
1 /*
2 * TI OMAP I2C master mode driver
3 *
4 * Copyright (C) 2003 MontaVista Software, Inc.
5 * Copyright (C) 2005 Nokia Corporation
6 * Copyright (C) 2004 - 2007 Texas Instruments.
7 *
8 * Originally written by MontaVista Software, Inc.
9 * Additional contributions by:
10 * Tony Lindgren <tony@atomide.com>
11 * Imre Deak <imre.deak@nokia.com>
12 * Juha Yrjölä <juha.yrjola@solidboot.com>
13 * Syed Khasim <x0khasim@ti.com>
14 * Nishant Menon <nm@ti.com>
15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License as published by
18 * the Free Software Foundation; either version 2 of the License, or
19 * (at your option) any later version.
20 *
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
25 *
26 * You should have received a copy of the GNU General Public License
27 * along with this program; if not, write to the Free Software
28 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
29 */
30
31 #include <linux/module.h>
32 #include <linux/delay.h>
33 #include <linux/i2c.h>
34 #include <linux/err.h>
35 #include <linux/interrupt.h>
36 #include <linux/completion.h>
37 #include <linux/platform_device.h>
38 #include <linux/clk.h>
39 #include <linux/io.h>
40 #include <linux/slab.h>
41 #include <linux/i2c-omap.h>
42 #include <linux/pm_runtime.h>
43
44 /* I2C controller revisions */
45 #define OMAP_I2C_OMAP1_REV_2 0x20
46
47 /* I2C controller revisions present on specific hardware */
48 #define OMAP_I2C_REV_ON_2430 0x36
49 #define OMAP_I2C_REV_ON_3430 0x3C
50 #define OMAP_I2C_REV_ON_3530_4430 0x40
51
52 /* timeout waiting for the controller to respond */
53 #define OMAP_I2C_TIMEOUT (msecs_to_jiffies(1000))
54
55 /* For OMAP3 I2C_IV has changed to I2C_WE (wakeup enable) */
56 enum {
57 OMAP_I2C_REV_REG = 0,
58 OMAP_I2C_IE_REG,
59 OMAP_I2C_STAT_REG,
60 OMAP_I2C_IV_REG,
61 OMAP_I2C_WE_REG,
62 OMAP_I2C_SYSS_REG,
63 OMAP_I2C_BUF_REG,
64 OMAP_I2C_CNT_REG,
65 OMAP_I2C_DATA_REG,
66 OMAP_I2C_SYSC_REG,
67 OMAP_I2C_CON_REG,
68 OMAP_I2C_OA_REG,
69 OMAP_I2C_SA_REG,
70 OMAP_I2C_PSC_REG,
71 OMAP_I2C_SCLL_REG,
72 OMAP_I2C_SCLH_REG,
73 OMAP_I2C_SYSTEST_REG,
74 OMAP_I2C_BUFSTAT_REG,
75 /* only on OMAP4430 */
76 OMAP_I2C_IP_V2_REVNB_LO,
77 OMAP_I2C_IP_V2_REVNB_HI,
78 OMAP_I2C_IP_V2_IRQSTATUS_RAW,
79 OMAP_I2C_IP_V2_IRQENABLE_SET,
80 OMAP_I2C_IP_V2_IRQENABLE_CLR,
81 };
82
83 /* I2C Interrupt Enable Register (OMAP_I2C_IE): */
84 #define OMAP_I2C_IE_XDR (1 << 14) /* TX Buffer drain int enable */
85 #define OMAP_I2C_IE_RDR (1 << 13) /* RX Buffer drain int enable */
86 #define OMAP_I2C_IE_XRDY (1 << 4) /* TX data ready int enable */
87 #define OMAP_I2C_IE_RRDY (1 << 3) /* RX data ready int enable */
88 #define OMAP_I2C_IE_ARDY (1 << 2) /* Access ready int enable */
89 #define OMAP_I2C_IE_NACK (1 << 1) /* No ack interrupt enable */
90 #define OMAP_I2C_IE_AL (1 << 0) /* Arbitration lost int ena */
91
92 /* I2C Status Register (OMAP_I2C_STAT): */
93 #define OMAP_I2C_STAT_XDR (1 << 14) /* TX Buffer draining */
94 #define OMAP_I2C_STAT_RDR (1 << 13) /* RX Buffer draining */
95 #define OMAP_I2C_STAT_BB (1 << 12) /* Bus busy */
96 #define OMAP_I2C_STAT_ROVR (1 << 11) /* Receive overrun */
97 #define OMAP_I2C_STAT_XUDF (1 << 10) /* Transmit underflow */
98 #define OMAP_I2C_STAT_AAS (1 << 9) /* Address as slave */
99 #define OMAP_I2C_STAT_AD0 (1 << 8) /* Address zero */
100 #define OMAP_I2C_STAT_XRDY (1 << 4) /* Transmit data ready */
101 #define OMAP_I2C_STAT_RRDY (1 << 3) /* Receive data ready */
102 #define OMAP_I2C_STAT_ARDY (1 << 2) /* Register access ready */
103 #define OMAP_I2C_STAT_NACK (1 << 1) /* No ack interrupt enable */
104 #define OMAP_I2C_STAT_AL (1 << 0) /* Arbitration lost int ena */
105
106 /* I2C WE wakeup enable register */
107 #define OMAP_I2C_WE_XDR_WE (1 << 14) /* TX drain wakup */
108 #define OMAP_I2C_WE_RDR_WE (1 << 13) /* RX drain wakeup */
109 #define OMAP_I2C_WE_AAS_WE (1 << 9) /* Address as slave wakeup*/
110 #define OMAP_I2C_WE_BF_WE (1 << 8) /* Bus free wakeup */
111 #define OMAP_I2C_WE_STC_WE (1 << 6) /* Start condition wakeup */
112 #define OMAP_I2C_WE_GC_WE (1 << 5) /* General call wakeup */
113 #define OMAP_I2C_WE_DRDY_WE (1 << 3) /* TX/RX data ready wakeup */
114 #define OMAP_I2C_WE_ARDY_WE (1 << 2) /* Reg access ready wakeup */
115 #define OMAP_I2C_WE_NACK_WE (1 << 1) /* No acknowledgment wakeup */
116 #define OMAP_I2C_WE_AL_WE (1 << 0) /* Arbitration lost wakeup */
117
118 #define OMAP_I2C_WE_ALL (OMAP_I2C_WE_XDR_WE | OMAP_I2C_WE_RDR_WE | \
119 OMAP_I2C_WE_AAS_WE | OMAP_I2C_WE_BF_WE | \
120 OMAP_I2C_WE_STC_WE | OMAP_I2C_WE_GC_WE | \
121 OMAP_I2C_WE_DRDY_WE | OMAP_I2C_WE_ARDY_WE | \
122 OMAP_I2C_WE_NACK_WE | OMAP_I2C_WE_AL_WE)
123
124 /* I2C Buffer Configuration Register (OMAP_I2C_BUF): */
125 #define OMAP_I2C_BUF_RDMA_EN (1 << 15) /* RX DMA channel enable */
126 #define OMAP_I2C_BUF_RXFIF_CLR (1 << 14) /* RX FIFO Clear */
127 #define OMAP_I2C_BUF_XDMA_EN (1 << 7) /* TX DMA channel enable */
128 #define OMAP_I2C_BUF_TXFIF_CLR (1 << 6) /* TX FIFO Clear */
129
130 /* I2C Configuration Register (OMAP_I2C_CON): */
131 #define OMAP_I2C_CON_EN (1 << 15) /* I2C module enable */
132 #define OMAP_I2C_CON_BE (1 << 14) /* Big endian mode */
133 #define OMAP_I2C_CON_OPMODE_HS (1 << 12) /* High Speed support */
134 #define OMAP_I2C_CON_STB (1 << 11) /* Start byte mode (master) */
135 #define OMAP_I2C_CON_MST (1 << 10) /* Master/slave mode */
136 #define OMAP_I2C_CON_TRX (1 << 9) /* TX/RX mode (master only) */
137 #define OMAP_I2C_CON_XA (1 << 8) /* Expand address */
138 #define OMAP_I2C_CON_RM (1 << 2) /* Repeat mode (master only) */
139 #define OMAP_I2C_CON_STP (1 << 1) /* Stop cond (master only) */
140 #define OMAP_I2C_CON_STT (1 << 0) /* Start condition (master) */
141
142 /* I2C SCL time value when Master */
143 #define OMAP_I2C_SCLL_HSSCLL 8
144 #define OMAP_I2C_SCLH_HSSCLH 8
145
146 /* I2C System Test Register (OMAP_I2C_SYSTEST): */
147 #ifdef DEBUG
148 #define OMAP_I2C_SYSTEST_ST_EN (1 << 15) /* System test enable */
149 #define OMAP_I2C_SYSTEST_FREE (1 << 14) /* Free running mode */
150 #define OMAP_I2C_SYSTEST_TMODE_MASK (3 << 12) /* Test mode select */
151 #define OMAP_I2C_SYSTEST_TMODE_SHIFT (12) /* Test mode select */
152 #define OMAP_I2C_SYSTEST_SCL_I (1 << 3) /* SCL line sense in */
153 #define OMAP_I2C_SYSTEST_SCL_O (1 << 2) /* SCL line drive out */
154 #define OMAP_I2C_SYSTEST_SDA_I (1 << 1) /* SDA line sense in */
155 #define OMAP_I2C_SYSTEST_SDA_O (1 << 0) /* SDA line drive out */
156 #endif
157
158 /* OCP_SYSSTATUS bit definitions */
159 #define SYSS_RESETDONE_MASK (1 << 0)
160
161 /* OCP_SYSCONFIG bit definitions */
162 #define SYSC_CLOCKACTIVITY_MASK (0x3 << 8)
163 #define SYSC_SIDLEMODE_MASK (0x3 << 3)
164 #define SYSC_ENAWAKEUP_MASK (1 << 2)
165 #define SYSC_SOFTRESET_MASK (1 << 1)
166 #define SYSC_AUTOIDLE_MASK (1 << 0)
167
168 #define SYSC_IDLEMODE_SMART 0x2
169 #define SYSC_CLOCKACTIVITY_FCLK 0x2
170
171 /* Errata definitions */
172 #define I2C_OMAP_ERRATA_I207 (1 << 0)
173 #define I2C_OMAP3_1P153 (1 << 1)
174
175 struct omap_i2c_dev {
176 struct device *dev;
177 void __iomem *base; /* virtual */
178 int irq;
179 int reg_shift; /* bit shift for I2C register addresses */
180 struct completion cmd_complete;
181 struct resource *ioarea;
182 u32 latency; /* maximum mpu wkup latency */
183 void (*set_mpu_wkup_lat)(struct device *dev,
184 long latency);
185 u32 speed; /* Speed of bus in Khz */
186 u16 cmd_err;
187 u8 *buf;
188 u8 *regs;
189 size_t buf_len;
190 struct i2c_adapter adapter;
191 u8 fifo_size; /* use as flag and value
192 * fifo_size==0 implies no fifo
193 * if set, should be trsh+1
194 */
195 u8 rev;
196 unsigned b_hw:1; /* bad h/w fixes */
197 unsigned idle:1;
198 u16 iestate; /* Saved interrupt register */
199 u16 pscstate;
200 u16 scllstate;
201 u16 sclhstate;
202 u16 bufstate;
203 u16 syscstate;
204 u16 westate;
205 u16 errata;
206 };
207
208 static const u8 reg_map_ip_v1[] = {
209 [OMAP_I2C_REV_REG] = 0x00,
210 [OMAP_I2C_IE_REG] = 0x01,
211 [OMAP_I2C_STAT_REG] = 0x02,
212 [OMAP_I2C_IV_REG] = 0x03,
213 [OMAP_I2C_WE_REG] = 0x03,
214 [OMAP_I2C_SYSS_REG] = 0x04,
215 [OMAP_I2C_BUF_REG] = 0x05,
216 [OMAP_I2C_CNT_REG] = 0x06,
217 [OMAP_I2C_DATA_REG] = 0x07,
218 [OMAP_I2C_SYSC_REG] = 0x08,
219 [OMAP_I2C_CON_REG] = 0x09,
220 [OMAP_I2C_OA_REG] = 0x0a,
221 [OMAP_I2C_SA_REG] = 0x0b,
222 [OMAP_I2C_PSC_REG] = 0x0c,
223 [OMAP_I2C_SCLL_REG] = 0x0d,
224 [OMAP_I2C_SCLH_REG] = 0x0e,
225 [OMAP_I2C_SYSTEST_REG] = 0x0f,
226 [OMAP_I2C_BUFSTAT_REG] = 0x10,
227 };
228
229 static const u8 reg_map_ip_v2[] = {
230 [OMAP_I2C_REV_REG] = 0x04,
231 [OMAP_I2C_IE_REG] = 0x2c,
232 [OMAP_I2C_STAT_REG] = 0x28,
233 [OMAP_I2C_IV_REG] = 0x34,
234 [OMAP_I2C_WE_REG] = 0x34,
235 [OMAP_I2C_SYSS_REG] = 0x90,
236 [OMAP_I2C_BUF_REG] = 0x94,
237 [OMAP_I2C_CNT_REG] = 0x98,
238 [OMAP_I2C_DATA_REG] = 0x9c,
239 [OMAP_I2C_SYSC_REG] = 0x20,
240 [OMAP_I2C_CON_REG] = 0xa4,
241 [OMAP_I2C_OA_REG] = 0xa8,
242 [OMAP_I2C_SA_REG] = 0xac,
243 [OMAP_I2C_PSC_REG] = 0xb0,
244 [OMAP_I2C_SCLL_REG] = 0xb4,
245 [OMAP_I2C_SCLH_REG] = 0xb8,
246 [OMAP_I2C_SYSTEST_REG] = 0xbC,
247 [OMAP_I2C_BUFSTAT_REG] = 0xc0,
248 [OMAP_I2C_IP_V2_REVNB_LO] = 0x00,
249 [OMAP_I2C_IP_V2_REVNB_HI] = 0x04,
250 [OMAP_I2C_IP_V2_IRQSTATUS_RAW] = 0x24,
251 [OMAP_I2C_IP_V2_IRQENABLE_SET] = 0x2c,
252 [OMAP_I2C_IP_V2_IRQENABLE_CLR] = 0x30,
253 };
254
255 static inline void omap_i2c_write_reg(struct omap_i2c_dev *i2c_dev,
256 int reg, u16 val)
257 {
258 __raw_writew(val, i2c_dev->base +
259 (i2c_dev->regs[reg] << i2c_dev->reg_shift));
260 }
261
262 static inline u16 omap_i2c_read_reg(struct omap_i2c_dev *i2c_dev, int reg)
263 {
264 return __raw_readw(i2c_dev->base +
265 (i2c_dev->regs[reg] << i2c_dev->reg_shift));
266 }
267
268 static void omap_i2c_unidle(struct omap_i2c_dev *dev)
269 {
270 struct platform_device *pdev;
271 struct omap_i2c_bus_platform_data *pdata;
272
273 WARN_ON(!dev->idle);
274
275 pdev = to_platform_device(dev->dev);
276 pdata = pdev->dev.platform_data;
277
278 pm_runtime_get_sync(&pdev->dev);
279
280 if (pdata->flags & OMAP_I2C_FLAG_RESET_REGS_POSTIDLE) {
281 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
282 omap_i2c_write_reg(dev, OMAP_I2C_PSC_REG, dev->pscstate);
283 omap_i2c_write_reg(dev, OMAP_I2C_SCLL_REG, dev->scllstate);
284 omap_i2c_write_reg(dev, OMAP_I2C_SCLH_REG, dev->sclhstate);
285 omap_i2c_write_reg(dev, OMAP_I2C_BUF_REG, dev->bufstate);
286 omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG, dev->syscstate);
287 omap_i2c_write_reg(dev, OMAP_I2C_WE_REG, dev->westate);
288 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
289 }
290 dev->idle = 0;
291
292 /*
293 * Don't write to this register if the IE state is 0 as it can
294 * cause deadlock.
295 */
296 if (dev->iestate)
297 omap_i2c_write_reg(dev, OMAP_I2C_IE_REG, dev->iestate);
298 }
299
300 static void omap_i2c_idle(struct omap_i2c_dev *dev)
301 {
302 struct platform_device *pdev;
303 struct omap_i2c_bus_platform_data *pdata;
304 u16 iv;
305
306 WARN_ON(dev->idle);
307
308 pdev = to_platform_device(dev->dev);
309 pdata = pdev->dev.platform_data;
310
311 dev->iestate = omap_i2c_read_reg(dev, OMAP_I2C_IE_REG);
312 if (pdata->rev == OMAP_I2C_IP_VERSION_2)
313 omap_i2c_write_reg(dev, OMAP_I2C_IP_V2_IRQENABLE_CLR, 1);
314 else
315 omap_i2c_write_reg(dev, OMAP_I2C_IE_REG, 0);
316
317 if (dev->rev < OMAP_I2C_OMAP1_REV_2) {
318 iv = omap_i2c_read_reg(dev, OMAP_I2C_IV_REG); /* Read clears */
319 } else {
320 omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, dev->iestate);
321
322 /* Flush posted write before the dev->idle store occurs */
323 omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG);
324 }
325 dev->idle = 1;
326
327 pm_runtime_put_sync(&pdev->dev);
328 }
329
330 static int omap_i2c_init(struct omap_i2c_dev *dev)
331 {
332 u16 psc = 0, scll = 0, sclh = 0, buf = 0;
333 u16 fsscll = 0, fssclh = 0, hsscll = 0, hssclh = 0;
334 unsigned long fclk_rate = 12000000;
335 unsigned long timeout;
336 unsigned long internal_clk = 0;
337 struct clk *fclk;
338 struct platform_device *pdev;
339 struct omap_i2c_bus_platform_data *pdata;
340
341 pdev = to_platform_device(dev->dev);
342 pdata = pdev->dev.platform_data;
343
344 if (dev->rev >= OMAP_I2C_OMAP1_REV_2) {
345 /* Disable I2C controller before soft reset */
346 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG,
347 omap_i2c_read_reg(dev, OMAP_I2C_CON_REG) &
348 ~(OMAP_I2C_CON_EN));
349
350 omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG, SYSC_SOFTRESET_MASK);
351 /* For some reason we need to set the EN bit before the
352 * reset done bit gets set. */
353 timeout = jiffies + OMAP_I2C_TIMEOUT;
354 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
355 while (!(omap_i2c_read_reg(dev, OMAP_I2C_SYSS_REG) &
356 SYSS_RESETDONE_MASK)) {
357 if (time_after(jiffies, timeout)) {
358 dev_warn(dev->dev, "timeout waiting "
359 "for controller reset\n");
360 return -ETIMEDOUT;
361 }
362 msleep(1);
363 }
364
365 /* SYSC register is cleared by the reset; rewrite it */
366 if (dev->rev == OMAP_I2C_REV_ON_2430) {
367
368 omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG,
369 SYSC_AUTOIDLE_MASK);
370
371 } else if (dev->rev >= OMAP_I2C_REV_ON_3430) {
372 dev->syscstate = SYSC_AUTOIDLE_MASK;
373 dev->syscstate |= SYSC_ENAWAKEUP_MASK;
374 dev->syscstate |= (SYSC_IDLEMODE_SMART <<
375 __ffs(SYSC_SIDLEMODE_MASK));
376 dev->syscstate |= (SYSC_CLOCKACTIVITY_FCLK <<
377 __ffs(SYSC_CLOCKACTIVITY_MASK));
378
379 omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG,
380 dev->syscstate);
381 /*
382 * Enabling all wakup sources to stop I2C freezing on
383 * WFI instruction.
384 * REVISIT: Some wkup sources might not be needed.
385 */
386 dev->westate = OMAP_I2C_WE_ALL;
387 if (dev->rev < OMAP_I2C_REV_ON_3530_4430)
388 omap_i2c_write_reg(dev, OMAP_I2C_WE_REG,
389 dev->westate);
390 }
391 }
392 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
393
394 if (pdata->flags & OMAP_I2C_FLAG_ALWAYS_ARMXOR_CLK) {
395 /*
396 * The I2C functional clock is the armxor_ck, so there's
397 * no need to get "armxor_ck" separately. Now, if OMAP2420
398 * always returns 12MHz for the functional clock, we can
399 * do this bit unconditionally.
400 */
401 fclk = clk_get(dev->dev, "fck");
402 fclk_rate = clk_get_rate(fclk);
403 clk_put(fclk);
404
405 /* TRM for 5912 says the I2C clock must be prescaled to be
406 * between 7 - 12 MHz. The XOR input clock is typically
407 * 12, 13 or 19.2 MHz. So we should have code that produces:
408 *
409 * XOR MHz Divider Prescaler
410 * 12 1 0
411 * 13 2 1
412 * 19.2 2 1
413 */
414 if (fclk_rate > 12000000)
415 psc = fclk_rate / 12000000;
416 }
417
418 if (!(pdata->flags & OMAP_I2C_FLAG_SIMPLE_CLOCK)) {
419
420 /*
421 * HSI2C controller internal clk rate should be 19.2 Mhz for
422 * HS and for all modes on 2430. On 34xx we can use lower rate
423 * to get longer filter period for better noise suppression.
424 * The filter is iclk (fclk for HS) period.
425 */
426 if (dev->speed > 400 ||
427 pdata->flags & OMAP_I2C_FLAG_FORCE_19200_INT_CLK)
428 internal_clk = 19200;
429 else if (dev->speed > 100)
430 internal_clk = 9600;
431 else
432 internal_clk = 4000;
433 fclk = clk_get(dev->dev, "fck");
434 fclk_rate = clk_get_rate(fclk) / 1000;
435 clk_put(fclk);
436
437 /* Compute prescaler divisor */
438 psc = fclk_rate / internal_clk;
439 psc = psc - 1;
440
441 /* If configured for High Speed */
442 if (dev->speed > 400) {
443 unsigned long scl;
444
445 /* For first phase of HS mode */
446 scl = internal_clk / 400;
447 fsscll = scl - (scl / 3) - 7;
448 fssclh = (scl / 3) - 5;
449
450 /* For second phase of HS mode */
451 scl = fclk_rate / dev->speed;
452 hsscll = scl - (scl / 3) - 7;
453 hssclh = (scl / 3) - 5;
454 } else if (dev->speed > 100) {
455 unsigned long scl;
456
457 /* Fast mode */
458 scl = internal_clk / dev->speed;
459 fsscll = scl - (scl / 3) - 7;
460 fssclh = (scl / 3) - 5;
461 } else {
462 /* Standard mode */
463 fsscll = internal_clk / (dev->speed * 2) - 7;
464 fssclh = internal_clk / (dev->speed * 2) - 5;
465 }
466 scll = (hsscll << OMAP_I2C_SCLL_HSSCLL) | fsscll;
467 sclh = (hssclh << OMAP_I2C_SCLH_HSSCLH) | fssclh;
468 } else {
469 /* Program desired operating rate */
470 fclk_rate /= (psc + 1) * 1000;
471 if (psc > 2)
472 psc = 2;
473 scll = fclk_rate / (dev->speed * 2) - 7 + psc;
474 sclh = fclk_rate / (dev->speed * 2) - 7 + psc;
475 }
476
477 /* Setup clock prescaler to obtain approx 12MHz I2C module clock: */
478 omap_i2c_write_reg(dev, OMAP_I2C_PSC_REG, psc);
479
480 /* SCL low and high time values */
481 omap_i2c_write_reg(dev, OMAP_I2C_SCLL_REG, scll);
482 omap_i2c_write_reg(dev, OMAP_I2C_SCLH_REG, sclh);
483
484 if (dev->fifo_size) {
485 /* Note: setup required fifo size - 1. RTRSH and XTRSH */
486 buf = (dev->fifo_size - 1) << 8 | OMAP_I2C_BUF_RXFIF_CLR |
487 (dev->fifo_size - 1) | OMAP_I2C_BUF_TXFIF_CLR;
488 omap_i2c_write_reg(dev, OMAP_I2C_BUF_REG, buf);
489 }
490
491 /* Take the I2C module out of reset: */
492 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
493
494 dev->errata = 0;
495
496 if (pdata->flags & OMAP_I2C_FLAG_APPLY_ERRATA_I207)
497 dev->errata |= I2C_OMAP_ERRATA_I207;
498
499 /* Enable interrupts */
500 dev->iestate = (OMAP_I2C_IE_XRDY | OMAP_I2C_IE_RRDY |
501 OMAP_I2C_IE_ARDY | OMAP_I2C_IE_NACK |
502 OMAP_I2C_IE_AL) | ((dev->fifo_size) ?
503 (OMAP_I2C_IE_RDR | OMAP_I2C_IE_XDR) : 0);
504 omap_i2c_write_reg(dev, OMAP_I2C_IE_REG, dev->iestate);
505 if (pdata->flags & OMAP_I2C_FLAG_RESET_REGS_POSTIDLE) {
506 dev->pscstate = psc;
507 dev->scllstate = scll;
508 dev->sclhstate = sclh;
509 dev->bufstate = buf;
510 }
511 return 0;
512 }
513
514 /*
515 * Waiting on Bus Busy
516 */
517 static int omap_i2c_wait_for_bb(struct omap_i2c_dev *dev)
518 {
519 unsigned long timeout;
520
521 timeout = jiffies + OMAP_I2C_TIMEOUT;
522 while (omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG) & OMAP_I2C_STAT_BB) {
523 if (time_after(jiffies, timeout)) {
524 dev_warn(dev->dev, "timeout waiting for bus ready\n");
525 return -ETIMEDOUT;
526 }
527 msleep(1);
528 }
529
530 return 0;
531 }
532
533 /*
534 * Low level master read/write transaction.
535 */
536 static int omap_i2c_xfer_msg(struct i2c_adapter *adap,
537 struct i2c_msg *msg, int stop)
538 {
539 struct omap_i2c_dev *dev = i2c_get_adapdata(adap);
540 int r;
541 u16 w;
542
543 dev_dbg(dev->dev, "addr: 0x%04x, len: %d, flags: 0x%x, stop: %d\n",
544 msg->addr, msg->len, msg->flags, stop);
545
546 if (msg->len == 0)
547 return -EINVAL;
548
549 omap_i2c_write_reg(dev, OMAP_I2C_SA_REG, msg->addr);
550
551 /* REVISIT: Could the STB bit of I2C_CON be used with probing? */
552 dev->buf = msg->buf;
553 dev->buf_len = msg->len;
554
555 omap_i2c_write_reg(dev, OMAP_I2C_CNT_REG, dev->buf_len);
556
557 /* Clear the FIFO Buffers */
558 w = omap_i2c_read_reg(dev, OMAP_I2C_BUF_REG);
559 w |= OMAP_I2C_BUF_RXFIF_CLR | OMAP_I2C_BUF_TXFIF_CLR;
560 omap_i2c_write_reg(dev, OMAP_I2C_BUF_REG, w);
561
562 init_completion(&dev->cmd_complete);
563 dev->cmd_err = 0;
564
565 w = OMAP_I2C_CON_EN | OMAP_I2C_CON_MST | OMAP_I2C_CON_STT;
566
567 /* High speed configuration */
568 if (dev->speed > 400)
569 w |= OMAP_I2C_CON_OPMODE_HS;
570
571 if (msg->flags & I2C_M_TEN)
572 w |= OMAP_I2C_CON_XA;
573 if (!(msg->flags & I2C_M_RD))
574 w |= OMAP_I2C_CON_TRX;
575
576 if (!dev->b_hw && stop)
577 w |= OMAP_I2C_CON_STP;
578
579 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w);
580
581 /*
582 * Don't write stt and stp together on some hardware.
583 */
584 if (dev->b_hw && stop) {
585 unsigned long delay = jiffies + OMAP_I2C_TIMEOUT;
586 u16 con = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG);
587 while (con & OMAP_I2C_CON_STT) {
588 con = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG);
589
590 /* Let the user know if i2c is in a bad state */
591 if (time_after(jiffies, delay)) {
592 dev_err(dev->dev, "controller timed out "
593 "waiting for start condition to finish\n");
594 return -ETIMEDOUT;
595 }
596 cpu_relax();
597 }
598
599 w |= OMAP_I2C_CON_STP;
600 w &= ~OMAP_I2C_CON_STT;
601 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w);
602 }
603
604 /*
605 * REVISIT: We should abort the transfer on signals, but the bus goes
606 * into arbitration and we're currently unable to recover from it.
607 */
608 r = wait_for_completion_timeout(&dev->cmd_complete,
609 OMAP_I2C_TIMEOUT);
610 dev->buf_len = 0;
611 if (r < 0)
612 return r;
613 if (r == 0) {
614 dev_err(dev->dev, "controller timed out\n");
615 omap_i2c_init(dev);
616 return -ETIMEDOUT;
617 }
618
619 if (likely(!dev->cmd_err))
620 return 0;
621
622 /* We have an error */
623 if (dev->cmd_err & (OMAP_I2C_STAT_AL | OMAP_I2C_STAT_ROVR |
624 OMAP_I2C_STAT_XUDF)) {
625 omap_i2c_init(dev);
626 return -EIO;
627 }
628
629 if (dev->cmd_err & OMAP_I2C_STAT_NACK) {
630 if (msg->flags & I2C_M_IGNORE_NAK)
631 return 0;
632 if (stop) {
633 w = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG);
634 w |= OMAP_I2C_CON_STP;
635 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w);
636 }
637 return -EREMOTEIO;
638 }
639 return -EIO;
640 }
641
642
643 /*
644 * Prepare controller for a transaction and call omap_i2c_xfer_msg
645 * to do the work during IRQ processing.
646 */
647 static int
648 omap_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
649 {
650 struct omap_i2c_dev *dev = i2c_get_adapdata(adap);
651 int i;
652 int r;
653
654 omap_i2c_unidle(dev);
655
656 r = omap_i2c_wait_for_bb(dev);
657 if (r < 0)
658 goto out;
659
660 if (dev->set_mpu_wkup_lat != NULL)
661 dev->set_mpu_wkup_lat(dev->dev, dev->latency);
662
663 for (i = 0; i < num; i++) {
664 r = omap_i2c_xfer_msg(adap, &msgs[i], (i == (num - 1)));
665 if (r != 0)
666 break;
667 }
668
669 if (dev->set_mpu_wkup_lat != NULL)
670 dev->set_mpu_wkup_lat(dev->dev, -1);
671
672 if (r == 0)
673 r = num;
674
675 omap_i2c_wait_for_bb(dev);
676 out:
677 omap_i2c_idle(dev);
678 return r;
679 }
680
681 static u32
682 omap_i2c_func(struct i2c_adapter *adap)
683 {
684 return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK);
685 }
686
687 static inline void
688 omap_i2c_complete_cmd(struct omap_i2c_dev *dev, u16 err)
689 {
690 dev->cmd_err |= err;
691 complete(&dev->cmd_complete);
692 }
693
694 static inline void
695 omap_i2c_ack_stat(struct omap_i2c_dev *dev, u16 stat)
696 {
697 omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, stat);
698 }
699
700 static inline void i2c_omap_errata_i207(struct omap_i2c_dev *dev, u16 stat)
701 {
702 /*
703 * I2C Errata(Errata Nos. OMAP2: 1.67, OMAP3: 1.8)
704 * Not applicable for OMAP4.
705 * Under certain rare conditions, RDR could be set again
706 * when the bus is busy, then ignore the interrupt and
707 * clear the interrupt.
708 */
709 if (stat & OMAP_I2C_STAT_RDR) {
710 /* Step 1: If RDR is set, clear it */
711 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_RDR);
712
713 /* Step 2: */
714 if (!(omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG)
715 & OMAP_I2C_STAT_BB)) {
716
717 /* Step 3: */
718 if (omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG)
719 & OMAP_I2C_STAT_RDR) {
720 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_RDR);
721 dev_dbg(dev->dev, "RDR when bus is busy.\n");
722 }
723
724 }
725 }
726 }
727
728 /* rev1 devices are apparently only on some 15xx */
729 #ifdef CONFIG_ARCH_OMAP15XX
730
731 static irqreturn_t
732 omap_i2c_omap1_isr(int this_irq, void *dev_id)
733 {
734 struct omap_i2c_dev *dev = dev_id;
735 u16 iv, w;
736
737 if (dev->idle)
738 return IRQ_NONE;
739
740 iv = omap_i2c_read_reg(dev, OMAP_I2C_IV_REG);
741 switch (iv) {
742 case 0x00: /* None */
743 break;
744 case 0x01: /* Arbitration lost */
745 dev_err(dev->dev, "Arbitration lost\n");
746 omap_i2c_complete_cmd(dev, OMAP_I2C_STAT_AL);
747 break;
748 case 0x02: /* No acknowledgement */
749 omap_i2c_complete_cmd(dev, OMAP_I2C_STAT_NACK);
750 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_STP);
751 break;
752 case 0x03: /* Register access ready */
753 omap_i2c_complete_cmd(dev, 0);
754 break;
755 case 0x04: /* Receive data ready */
756 if (dev->buf_len) {
757 w = omap_i2c_read_reg(dev, OMAP_I2C_DATA_REG);
758 *dev->buf++ = w;
759 dev->buf_len--;
760 if (dev->buf_len) {
761 *dev->buf++ = w >> 8;
762 dev->buf_len--;
763 }
764 } else
765 dev_err(dev->dev, "RRDY IRQ while no data requested\n");
766 break;
767 case 0x05: /* Transmit data ready */
768 if (dev->buf_len) {
769 w = *dev->buf++;
770 dev->buf_len--;
771 if (dev->buf_len) {
772 w |= *dev->buf++ << 8;
773 dev->buf_len--;
774 }
775 omap_i2c_write_reg(dev, OMAP_I2C_DATA_REG, w);
776 } else
777 dev_err(dev->dev, "XRDY IRQ while no data to send\n");
778 break;
779 default:
780 return IRQ_NONE;
781 }
782
783 return IRQ_HANDLED;
784 }
785 #else
786 #define omap_i2c_omap1_isr NULL
787 #endif
788
789 /*
790 * OMAP3430 Errata 1.153: When an XRDY/XDR is hit, wait for XUDF before writing
791 * data to DATA_REG. Otherwise some data bytes can be lost while transferring
792 * them from the memory to the I2C interface.
793 */
794 static int errata_omap3_1p153(struct omap_i2c_dev *dev, u16 *stat, int *err)
795 {
796 unsigned long timeout = 10000;
797
798 while (--timeout && !(*stat & OMAP_I2C_STAT_XUDF)) {
799 if (*stat & (OMAP_I2C_STAT_NACK | OMAP_I2C_STAT_AL)) {
800 omap_i2c_ack_stat(dev, *stat & (OMAP_I2C_STAT_XRDY |
801 OMAP_I2C_STAT_XDR));
802 *err |= OMAP_I2C_STAT_XUDF;
803 return -ETIMEDOUT;
804 }
805
806 cpu_relax();
807 *stat = omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG);
808 }
809
810 if (!timeout) {
811 dev_err(dev->dev, "timeout waiting on XUDF bit\n");
812 return 0;
813 }
814
815 return 0;
816 }
817
818 static irqreturn_t
819 omap_i2c_isr(int this_irq, void *dev_id)
820 {
821 struct omap_i2c_dev *dev = dev_id;
822 u16 bits;
823 u16 stat, w;
824 int err, count = 0;
825 struct platform_device *pdev;
826 struct omap_i2c_bus_platform_data *pdata;
827
828 pdev = to_platform_device(dev->dev);
829 pdata = pdev->dev.platform_data;
830
831 if (dev->idle)
832 return IRQ_NONE;
833
834 bits = omap_i2c_read_reg(dev, OMAP_I2C_IE_REG);
835 while ((stat = (omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG))) & bits) {
836 dev_dbg(dev->dev, "IRQ (ISR = 0x%04x)\n", stat);
837 if (count++ == 100) {
838 dev_warn(dev->dev, "Too much work in one IRQ\n");
839 break;
840 }
841
842 err = 0;
843 complete:
844 /*
845 * Ack the stat in one go, but [R/X]DR and [R/X]RDY should be
846 * acked after the data operation is complete.
847 * Ref: TRM SWPU114Q Figure 18-31
848 */
849 omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, stat &
850 ~(OMAP_I2C_STAT_RRDY | OMAP_I2C_STAT_RDR |
851 OMAP_I2C_STAT_XRDY | OMAP_I2C_STAT_XDR));
852
853 if (stat & OMAP_I2C_STAT_NACK) {
854 err |= OMAP_I2C_STAT_NACK;
855 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG,
856 OMAP_I2C_CON_STP);
857 }
858 if (stat & OMAP_I2C_STAT_AL) {
859 dev_err(dev->dev, "Arbitration lost\n");
860 err |= OMAP_I2C_STAT_AL;
861 }
862 /*
863 * ProDB0017052: Clear ARDY bit twice
864 */
865 if (stat & (OMAP_I2C_STAT_ARDY | OMAP_I2C_STAT_NACK |
866 OMAP_I2C_STAT_AL)) {
867 omap_i2c_ack_stat(dev, stat &
868 (OMAP_I2C_STAT_RRDY | OMAP_I2C_STAT_RDR |
869 OMAP_I2C_STAT_XRDY | OMAP_I2C_STAT_XDR |
870 OMAP_I2C_STAT_ARDY));
871 omap_i2c_complete_cmd(dev, err);
872 return IRQ_HANDLED;
873 }
874 if (stat & (OMAP_I2C_STAT_RRDY | OMAP_I2C_STAT_RDR)) {
875 u8 num_bytes = 1;
876
877 if (dev->errata & I2C_OMAP_ERRATA_I207)
878 i2c_omap_errata_i207(dev, stat);
879
880 if (dev->fifo_size) {
881 if (stat & OMAP_I2C_STAT_RRDY)
882 num_bytes = dev->fifo_size;
883 else /* read RXSTAT on RDR interrupt */
884 num_bytes = (omap_i2c_read_reg(dev,
885 OMAP_I2C_BUFSTAT_REG)
886 >> 8) & 0x3F;
887 }
888 while (num_bytes) {
889 num_bytes--;
890 w = omap_i2c_read_reg(dev, OMAP_I2C_DATA_REG);
891 if (dev->buf_len) {
892 *dev->buf++ = w;
893 dev->buf_len--;
894 /*
895 * Data reg in 2430, omap3 and
896 * omap4 is 8 bit wide
897 */
898 if (pdata->flags &
899 OMAP_I2C_FLAG_16BIT_DATA_REG) {
900 if (dev->buf_len) {
901 *dev->buf++ = w >> 8;
902 dev->buf_len--;
903 }
904 }
905 } else {
906 if (stat & OMAP_I2C_STAT_RRDY)
907 dev_err(dev->dev,
908 "RRDY IRQ while no data"
909 " requested\n");
910 if (stat & OMAP_I2C_STAT_RDR)
911 dev_err(dev->dev,
912 "RDR IRQ while no data"
913 " requested\n");
914 break;
915 }
916 }
917 omap_i2c_ack_stat(dev,
918 stat & (OMAP_I2C_STAT_RRDY | OMAP_I2C_STAT_RDR));
919 continue;
920 }
921 if (stat & (OMAP_I2C_STAT_XRDY | OMAP_I2C_STAT_XDR)) {
922 u8 num_bytes = 1;
923 if (dev->fifo_size) {
924 if (stat & OMAP_I2C_STAT_XRDY)
925 num_bytes = dev->fifo_size;
926 else /* read TXSTAT on XDR interrupt */
927 num_bytes = omap_i2c_read_reg(dev,
928 OMAP_I2C_BUFSTAT_REG)
929 & 0x3F;
930 }
931 while (num_bytes) {
932 num_bytes--;
933 w = 0;
934 if (dev->buf_len) {
935 w = *dev->buf++;
936 dev->buf_len--;
937 /*
938 * Data reg in 2430, omap3 and
939 * omap4 is 8 bit wide
940 */
941 if (pdata->flags &
942 OMAP_I2C_FLAG_16BIT_DATA_REG) {
943 if (dev->buf_len) {
944 w |= *dev->buf++ << 8;
945 dev->buf_len--;
946 }
947 }
948 } else {
949 if (stat & OMAP_I2C_STAT_XRDY)
950 dev_err(dev->dev,
951 "XRDY IRQ while no "
952 "data to send\n");
953 if (stat & OMAP_I2C_STAT_XDR)
954 dev_err(dev->dev,
955 "XDR IRQ while no "
956 "data to send\n");
957 break;
958 }
959
960 if ((dev->errata & I2C_OMAP3_1P153) &&
961 errata_omap3_1p153(dev, &stat, &err))
962 goto complete;
963
964 omap_i2c_write_reg(dev, OMAP_I2C_DATA_REG, w);
965 }
966 omap_i2c_ack_stat(dev,
967 stat & (OMAP_I2C_STAT_XRDY | OMAP_I2C_STAT_XDR));
968 continue;
969 }
970 if (stat & OMAP_I2C_STAT_ROVR) {
971 dev_err(dev->dev, "Receive overrun\n");
972 dev->cmd_err |= OMAP_I2C_STAT_ROVR;
973 }
974 if (stat & OMAP_I2C_STAT_XUDF) {
975 dev_err(dev->dev, "Transmit underflow\n");
976 dev->cmd_err |= OMAP_I2C_STAT_XUDF;
977 }
978 }
979
980 return count ? IRQ_HANDLED : IRQ_NONE;
981 }
982
983 static const struct i2c_algorithm omap_i2c_algo = {
984 .master_xfer = omap_i2c_xfer,
985 .functionality = omap_i2c_func,
986 };
987
988 static int __devinit
989 omap_i2c_probe(struct platform_device *pdev)
990 {
991 struct omap_i2c_dev *dev;
992 struct i2c_adapter *adap;
993 struct resource *mem, *irq, *ioarea;
994 struct omap_i2c_bus_platform_data *pdata = pdev->dev.platform_data;
995 irq_handler_t isr;
996 int r;
997 u32 speed = 0;
998
999 /* NOTE: driver uses the static register mapping */
1000 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1001 if (!mem) {
1002 dev_err(&pdev->dev, "no mem resource?\n");
1003 return -ENODEV;
1004 }
1005 irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1006 if (!irq) {
1007 dev_err(&pdev->dev, "no irq resource?\n");
1008 return -ENODEV;
1009 }
1010
1011 ioarea = request_mem_region(mem->start, resource_size(mem),
1012 pdev->name);
1013 if (!ioarea) {
1014 dev_err(&pdev->dev, "I2C region already claimed\n");
1015 return -EBUSY;
1016 }
1017
1018 dev = kzalloc(sizeof(struct omap_i2c_dev), GFP_KERNEL);
1019 if (!dev) {
1020 r = -ENOMEM;
1021 goto err_release_region;
1022 }
1023
1024 if (pdata != NULL) {
1025 speed = pdata->clkrate;
1026 dev->set_mpu_wkup_lat = pdata->set_mpu_wkup_lat;
1027 } else {
1028 speed = 100; /* Default speed */
1029 dev->set_mpu_wkup_lat = NULL;
1030 }
1031
1032 dev->speed = speed;
1033 dev->idle = 1;
1034 dev->dev = &pdev->dev;
1035 dev->irq = irq->start;
1036 dev->base = ioremap(mem->start, resource_size(mem));
1037 if (!dev->base) {
1038 r = -ENOMEM;
1039 goto err_free_mem;
1040 }
1041
1042 platform_set_drvdata(pdev, dev);
1043
1044 dev->reg_shift = (pdata->flags >> OMAP_I2C_FLAG_BUS_SHIFT__SHIFT) & 3;
1045
1046 if (pdata->rev == OMAP_I2C_IP_VERSION_2)
1047 dev->regs = (u8 *)reg_map_ip_v2;
1048 else
1049 dev->regs = (u8 *)reg_map_ip_v1;
1050
1051 pm_runtime_enable(&pdev->dev);
1052 omap_i2c_unidle(dev);
1053
1054 dev->rev = omap_i2c_read_reg(dev, OMAP_I2C_REV_REG) & 0xff;
1055
1056 if (dev->rev <= OMAP_I2C_REV_ON_3430)
1057 dev->errata |= I2C_OMAP3_1P153;
1058
1059 if (!(pdata->flags & OMAP_I2C_FLAG_NO_FIFO)) {
1060 u16 s;
1061
1062 /* Set up the fifo size - Get total size */
1063 s = (omap_i2c_read_reg(dev, OMAP_I2C_BUFSTAT_REG) >> 14) & 0x3;
1064 dev->fifo_size = 0x8 << s;
1065
1066 /*
1067 * Set up notification threshold as half the total available
1068 * size. This is to ensure that we can handle the status on int
1069 * call back latencies.
1070 */
1071 if (dev->rev >= OMAP_I2C_REV_ON_3530_4430) {
1072 dev->fifo_size = 0;
1073 dev->b_hw = 0; /* Disable hardware fixes */
1074 } else {
1075 dev->fifo_size = (dev->fifo_size / 2);
1076 dev->b_hw = 1; /* Enable hardware fixes */
1077 }
1078 /* calculate wakeup latency constraint for MPU */
1079 if (dev->set_mpu_wkup_lat != NULL)
1080 dev->latency = (1000000 * dev->fifo_size) /
1081 (1000 * speed / 8);
1082 }
1083
1084 /* reset ASAP, clearing any IRQs */
1085 omap_i2c_init(dev);
1086
1087 isr = (dev->rev < OMAP_I2C_OMAP1_REV_2) ? omap_i2c_omap1_isr :
1088 omap_i2c_isr;
1089 r = request_irq(dev->irq, isr, 0, pdev->name, dev);
1090
1091 if (r) {
1092 dev_err(dev->dev, "failure requesting irq %i\n", dev->irq);
1093 goto err_unuse_clocks;
1094 }
1095
1096 dev_info(dev->dev, "bus %d rev%d.%d at %d kHz\n",
1097 pdev->id, dev->rev >> 4, dev->rev & 0xf, dev->speed);
1098
1099 omap_i2c_idle(dev);
1100
1101 adap = &dev->adapter;
1102 i2c_set_adapdata(adap, dev);
1103 adap->owner = THIS_MODULE;
1104 adap->class = I2C_CLASS_HWMON;
1105 strlcpy(adap->name, "OMAP I2C adapter", sizeof(adap->name));
1106 adap->algo = &omap_i2c_algo;
1107 adap->dev.parent = &pdev->dev;
1108
1109 /* i2c device drivers may be active on return from add_adapter() */
1110 adap->nr = pdev->id;
1111 r = i2c_add_numbered_adapter(adap);
1112 if (r) {
1113 dev_err(dev->dev, "failure adding adapter\n");
1114 goto err_free_irq;
1115 }
1116
1117 return 0;
1118
1119 err_free_irq:
1120 free_irq(dev->irq, dev);
1121 err_unuse_clocks:
1122 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
1123 omap_i2c_idle(dev);
1124 iounmap(dev->base);
1125 err_free_mem:
1126 platform_set_drvdata(pdev, NULL);
1127 kfree(dev);
1128 err_release_region:
1129 release_mem_region(mem->start, resource_size(mem));
1130
1131 return r;
1132 }
1133
1134 static int
1135 omap_i2c_remove(struct platform_device *pdev)
1136 {
1137 struct omap_i2c_dev *dev = platform_get_drvdata(pdev);
1138 struct resource *mem;
1139
1140 platform_set_drvdata(pdev, NULL);
1141
1142 free_irq(dev->irq, dev);
1143 i2c_del_adapter(&dev->adapter);
1144 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
1145 iounmap(dev->base);
1146 kfree(dev);
1147 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1148 release_mem_region(mem->start, resource_size(mem));
1149 return 0;
1150 }
1151
1152 static struct platform_driver omap_i2c_driver = {
1153 .probe = omap_i2c_probe,
1154 .remove = omap_i2c_remove,
1155 .driver = {
1156 .name = "omap_i2c",
1157 .owner = THIS_MODULE,
1158 },
1159 };
1160
1161 /* I2C may be needed to bring up other drivers */
1162 static int __init
1163 omap_i2c_init_driver(void)
1164 {
1165 return platform_driver_register(&omap_i2c_driver);
1166 }
1167 subsys_initcall(omap_i2c_init_driver);
1168
1169 static void __exit omap_i2c_exit_driver(void)
1170 {
1171 platform_driver_unregister(&omap_i2c_driver);
1172 }
1173 module_exit(omap_i2c_exit_driver);
1174
1175 MODULE_AUTHOR("MontaVista Software, Inc. (and others)");
1176 MODULE_DESCRIPTION("TI OMAP I2C bus adapter");
1177 MODULE_LICENSE("GPL");
1178 MODULE_ALIAS("platform:omap_i2c");
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