2 * TI OMAP I2C master mode driver
4 * Copyright (C) 2003 MontaVista Software, Inc.
5 * Copyright (C) 2005 Nokia Corporation
6 * Copyright (C) 2004 - 2007 Texas Instruments.
8 * Originally written by MontaVista Software, Inc.
9 * Additional contributions by:
10 * Tony Lindgren <tony@atomide.com>
11 * Imre Deak <imre.deak@nokia.com>
12 * Juha Yrjölä <juha.yrjola@solidboot.com>
13 * Syed Khasim <x0khasim@ti.com>
14 * Nishant Menon <nm@ti.com>
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License as published by
18 * the Free Software Foundation; either version 2 of the License, or
19 * (at your option) any later version.
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
26 * You should have received a copy of the GNU General Public License
27 * along with this program; if not, write to the Free Software
28 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
31 #include <linux/module.h>
32 #include <linux/delay.h>
33 #include <linux/i2c.h>
34 #include <linux/err.h>
35 #include <linux/interrupt.h>
36 #include <linux/completion.h>
37 #include <linux/platform_device.h>
38 #include <linux/clk.h>
40 #include <linux/slab.h>
41 #include <linux/i2c-omap.h>
42 #include <linux/pm_runtime.h>
44 /* I2C controller revisions */
45 #define OMAP_I2C_REV_2 0x20
47 /* I2C controller revisions present on specific hardware */
48 #define OMAP_I2C_REV_ON_2430 0x36
49 #define OMAP_I2C_REV_ON_3430 0x3C
50 #define OMAP_I2C_REV_ON_4430 0x40
52 /* timeout waiting for the controller to respond */
53 #define OMAP_I2C_TIMEOUT (msecs_to_jiffies(1000))
55 /* For OMAP3 I2C_IV has changed to I2C_WE (wakeup enable) */
75 /* only on OMAP4430 */
76 OMAP_I2C_IP_V2_REVNB_LO
,
77 OMAP_I2C_IP_V2_REVNB_HI
,
78 OMAP_I2C_IP_V2_IRQSTATUS_RAW
,
79 OMAP_I2C_IP_V2_IRQENABLE_SET
,
80 OMAP_I2C_IP_V2_IRQENABLE_CLR
,
83 /* I2C Interrupt Enable Register (OMAP_I2C_IE): */
84 #define OMAP_I2C_IE_XDR (1 << 14) /* TX Buffer drain int enable */
85 #define OMAP_I2C_IE_RDR (1 << 13) /* RX Buffer drain int enable */
86 #define OMAP_I2C_IE_XRDY (1 << 4) /* TX data ready int enable */
87 #define OMAP_I2C_IE_RRDY (1 << 3) /* RX data ready int enable */
88 #define OMAP_I2C_IE_ARDY (1 << 2) /* Access ready int enable */
89 #define OMAP_I2C_IE_NACK (1 << 1) /* No ack interrupt enable */
90 #define OMAP_I2C_IE_AL (1 << 0) /* Arbitration lost int ena */
92 /* I2C Status Register (OMAP_I2C_STAT): */
93 #define OMAP_I2C_STAT_XDR (1 << 14) /* TX Buffer draining */
94 #define OMAP_I2C_STAT_RDR (1 << 13) /* RX Buffer draining */
95 #define OMAP_I2C_STAT_BB (1 << 12) /* Bus busy */
96 #define OMAP_I2C_STAT_ROVR (1 << 11) /* Receive overrun */
97 #define OMAP_I2C_STAT_XUDF (1 << 10) /* Transmit underflow */
98 #define OMAP_I2C_STAT_AAS (1 << 9) /* Address as slave */
99 #define OMAP_I2C_STAT_AD0 (1 << 8) /* Address zero */
100 #define OMAP_I2C_STAT_XRDY (1 << 4) /* Transmit data ready */
101 #define OMAP_I2C_STAT_RRDY (1 << 3) /* Receive data ready */
102 #define OMAP_I2C_STAT_ARDY (1 << 2) /* Register access ready */
103 #define OMAP_I2C_STAT_NACK (1 << 1) /* No ack interrupt enable */
104 #define OMAP_I2C_STAT_AL (1 << 0) /* Arbitration lost int ena */
106 /* I2C WE wakeup enable register */
107 #define OMAP_I2C_WE_XDR_WE (1 << 14) /* TX drain wakup */
108 #define OMAP_I2C_WE_RDR_WE (1 << 13) /* RX drain wakeup */
109 #define OMAP_I2C_WE_AAS_WE (1 << 9) /* Address as slave wakeup*/
110 #define OMAP_I2C_WE_BF_WE (1 << 8) /* Bus free wakeup */
111 #define OMAP_I2C_WE_STC_WE (1 << 6) /* Start condition wakeup */
112 #define OMAP_I2C_WE_GC_WE (1 << 5) /* General call wakeup */
113 #define OMAP_I2C_WE_DRDY_WE (1 << 3) /* TX/RX data ready wakeup */
114 #define OMAP_I2C_WE_ARDY_WE (1 << 2) /* Reg access ready wakeup */
115 #define OMAP_I2C_WE_NACK_WE (1 << 1) /* No acknowledgment wakeup */
116 #define OMAP_I2C_WE_AL_WE (1 << 0) /* Arbitration lost wakeup */
118 #define OMAP_I2C_WE_ALL (OMAP_I2C_WE_XDR_WE | OMAP_I2C_WE_RDR_WE | \
119 OMAP_I2C_WE_AAS_WE | OMAP_I2C_WE_BF_WE | \
120 OMAP_I2C_WE_STC_WE | OMAP_I2C_WE_GC_WE | \
121 OMAP_I2C_WE_DRDY_WE | OMAP_I2C_WE_ARDY_WE | \
122 OMAP_I2C_WE_NACK_WE | OMAP_I2C_WE_AL_WE)
124 /* I2C Buffer Configuration Register (OMAP_I2C_BUF): */
125 #define OMAP_I2C_BUF_RDMA_EN (1 << 15) /* RX DMA channel enable */
126 #define OMAP_I2C_BUF_RXFIF_CLR (1 << 14) /* RX FIFO Clear */
127 #define OMAP_I2C_BUF_XDMA_EN (1 << 7) /* TX DMA channel enable */
128 #define OMAP_I2C_BUF_TXFIF_CLR (1 << 6) /* TX FIFO Clear */
130 /* I2C Configuration Register (OMAP_I2C_CON): */
131 #define OMAP_I2C_CON_EN (1 << 15) /* I2C module enable */
132 #define OMAP_I2C_CON_BE (1 << 14) /* Big endian mode */
133 #define OMAP_I2C_CON_OPMODE_HS (1 << 12) /* High Speed support */
134 #define OMAP_I2C_CON_STB (1 << 11) /* Start byte mode (master) */
135 #define OMAP_I2C_CON_MST (1 << 10) /* Master/slave mode */
136 #define OMAP_I2C_CON_TRX (1 << 9) /* TX/RX mode (master only) */
137 #define OMAP_I2C_CON_XA (1 << 8) /* Expand address */
138 #define OMAP_I2C_CON_RM (1 << 2) /* Repeat mode (master only) */
139 #define OMAP_I2C_CON_STP (1 << 1) /* Stop cond (master only) */
140 #define OMAP_I2C_CON_STT (1 << 0) /* Start condition (master) */
142 /* I2C SCL time value when Master */
143 #define OMAP_I2C_SCLL_HSSCLL 8
144 #define OMAP_I2C_SCLH_HSSCLH 8
146 /* I2C System Test Register (OMAP_I2C_SYSTEST): */
148 #define OMAP_I2C_SYSTEST_ST_EN (1 << 15) /* System test enable */
149 #define OMAP_I2C_SYSTEST_FREE (1 << 14) /* Free running mode */
150 #define OMAP_I2C_SYSTEST_TMODE_MASK (3 << 12) /* Test mode select */
151 #define OMAP_I2C_SYSTEST_TMODE_SHIFT (12) /* Test mode select */
152 #define OMAP_I2C_SYSTEST_SCL_I (1 << 3) /* SCL line sense in */
153 #define OMAP_I2C_SYSTEST_SCL_O (1 << 2) /* SCL line drive out */
154 #define OMAP_I2C_SYSTEST_SDA_I (1 << 1) /* SDA line sense in */
155 #define OMAP_I2C_SYSTEST_SDA_O (1 << 0) /* SDA line drive out */
158 /* OCP_SYSSTATUS bit definitions */
159 #define SYSS_RESETDONE_MASK (1 << 0)
161 /* OCP_SYSCONFIG bit definitions */
162 #define SYSC_CLOCKACTIVITY_MASK (0x3 << 8)
163 #define SYSC_SIDLEMODE_MASK (0x3 << 3)
164 #define SYSC_ENAWAKEUP_MASK (1 << 2)
165 #define SYSC_SOFTRESET_MASK (1 << 1)
166 #define SYSC_AUTOIDLE_MASK (1 << 0)
168 #define SYSC_IDLEMODE_SMART 0x2
169 #define SYSC_CLOCKACTIVITY_FCLK 0x2
171 /* Errata definitions */
172 #define I2C_OMAP_ERRATA_I207 (1 << 0)
173 #define I2C_OMAP3_1P153 (1 << 1)
175 struct omap_i2c_dev
{
177 void __iomem
*base
; /* virtual */
179 int reg_shift
; /* bit shift for I2C register addresses */
180 struct completion cmd_complete
;
181 struct resource
*ioarea
;
182 u32 latency
; /* maximum mpu wkup latency */
183 void (*set_mpu_wkup_lat
)(struct device
*dev
,
185 u32 speed
; /* Speed of bus in Khz */
190 struct i2c_adapter adapter
;
191 u8 fifo_size
; /* use as flag and value
192 * fifo_size==0 implies no fifo
193 * if set, should be trsh+1
196 unsigned b_hw
:1; /* bad h/w fixes */
198 u16 iestate
; /* Saved interrupt register */
208 static const u8 reg_map_ip_v1
[] = {
209 [OMAP_I2C_REV_REG
] = 0x00,
210 [OMAP_I2C_IE_REG
] = 0x01,
211 [OMAP_I2C_STAT_REG
] = 0x02,
212 [OMAP_I2C_IV_REG
] = 0x03,
213 [OMAP_I2C_WE_REG
] = 0x03,
214 [OMAP_I2C_SYSS_REG
] = 0x04,
215 [OMAP_I2C_BUF_REG
] = 0x05,
216 [OMAP_I2C_CNT_REG
] = 0x06,
217 [OMAP_I2C_DATA_REG
] = 0x07,
218 [OMAP_I2C_SYSC_REG
] = 0x08,
219 [OMAP_I2C_CON_REG
] = 0x09,
220 [OMAP_I2C_OA_REG
] = 0x0a,
221 [OMAP_I2C_SA_REG
] = 0x0b,
222 [OMAP_I2C_PSC_REG
] = 0x0c,
223 [OMAP_I2C_SCLL_REG
] = 0x0d,
224 [OMAP_I2C_SCLH_REG
] = 0x0e,
225 [OMAP_I2C_SYSTEST_REG
] = 0x0f,
226 [OMAP_I2C_BUFSTAT_REG
] = 0x10,
229 static const u8 reg_map_ip_v2
[] = {
230 [OMAP_I2C_REV_REG
] = 0x04,
231 [OMAP_I2C_IE_REG
] = 0x2c,
232 [OMAP_I2C_STAT_REG
] = 0x28,
233 [OMAP_I2C_IV_REG
] = 0x34,
234 [OMAP_I2C_WE_REG
] = 0x34,
235 [OMAP_I2C_SYSS_REG
] = 0x90,
236 [OMAP_I2C_BUF_REG
] = 0x94,
237 [OMAP_I2C_CNT_REG
] = 0x98,
238 [OMAP_I2C_DATA_REG
] = 0x9c,
239 [OMAP_I2C_SYSC_REG
] = 0x20,
240 [OMAP_I2C_CON_REG
] = 0xa4,
241 [OMAP_I2C_OA_REG
] = 0xa8,
242 [OMAP_I2C_SA_REG
] = 0xac,
243 [OMAP_I2C_PSC_REG
] = 0xb0,
244 [OMAP_I2C_SCLL_REG
] = 0xb4,
245 [OMAP_I2C_SCLH_REG
] = 0xb8,
246 [OMAP_I2C_SYSTEST_REG
] = 0xbC,
247 [OMAP_I2C_BUFSTAT_REG
] = 0xc0,
248 [OMAP_I2C_IP_V2_REVNB_LO
] = 0x00,
249 [OMAP_I2C_IP_V2_REVNB_HI
] = 0x04,
250 [OMAP_I2C_IP_V2_IRQSTATUS_RAW
] = 0x24,
251 [OMAP_I2C_IP_V2_IRQENABLE_SET
] = 0x2c,
252 [OMAP_I2C_IP_V2_IRQENABLE_CLR
] = 0x30,
255 static inline void omap_i2c_write_reg(struct omap_i2c_dev
*i2c_dev
,
258 __raw_writew(val
, i2c_dev
->base
+
259 (i2c_dev
->regs
[reg
] << i2c_dev
->reg_shift
));
262 static inline u16
omap_i2c_read_reg(struct omap_i2c_dev
*i2c_dev
, int reg
)
264 return __raw_readw(i2c_dev
->base
+
265 (i2c_dev
->regs
[reg
] << i2c_dev
->reg_shift
));
268 static void omap_i2c_unidle(struct omap_i2c_dev
*dev
)
270 struct platform_device
*pdev
;
271 struct omap_i2c_bus_platform_data
*pdata
;
275 pdev
= to_platform_device(dev
->dev
);
276 pdata
= pdev
->dev
.platform_data
;
278 pm_runtime_get_sync(&pdev
->dev
);
280 if (cpu_is_omap34xx()) {
281 omap_i2c_write_reg(dev
, OMAP_I2C_CON_REG
, 0);
282 omap_i2c_write_reg(dev
, OMAP_I2C_PSC_REG
, dev
->pscstate
);
283 omap_i2c_write_reg(dev
, OMAP_I2C_SCLL_REG
, dev
->scllstate
);
284 omap_i2c_write_reg(dev
, OMAP_I2C_SCLH_REG
, dev
->sclhstate
);
285 omap_i2c_write_reg(dev
, OMAP_I2C_BUF_REG
, dev
->bufstate
);
286 omap_i2c_write_reg(dev
, OMAP_I2C_SYSC_REG
, dev
->syscstate
);
287 omap_i2c_write_reg(dev
, OMAP_I2C_WE_REG
, dev
->westate
);
288 omap_i2c_write_reg(dev
, OMAP_I2C_CON_REG
, OMAP_I2C_CON_EN
);
293 * Don't write to this register if the IE state is 0 as it can
297 omap_i2c_write_reg(dev
, OMAP_I2C_IE_REG
, dev
->iestate
);
300 static void omap_i2c_idle(struct omap_i2c_dev
*dev
)
302 struct platform_device
*pdev
;
303 struct omap_i2c_bus_platform_data
*pdata
;
308 pdev
= to_platform_device(dev
->dev
);
309 pdata
= pdev
->dev
.platform_data
;
311 dev
->iestate
= omap_i2c_read_reg(dev
, OMAP_I2C_IE_REG
);
312 if (dev
->rev
>= OMAP_I2C_REV_ON_4430
)
313 omap_i2c_write_reg(dev
, OMAP_I2C_IP_V2_IRQENABLE_CLR
, 1);
315 omap_i2c_write_reg(dev
, OMAP_I2C_IE_REG
, 0);
317 if (dev
->rev
< OMAP_I2C_REV_2
) {
318 iv
= omap_i2c_read_reg(dev
, OMAP_I2C_IV_REG
); /* Read clears */
320 omap_i2c_write_reg(dev
, OMAP_I2C_STAT_REG
, dev
->iestate
);
322 /* Flush posted write before the dev->idle store occurs */
323 omap_i2c_read_reg(dev
, OMAP_I2C_STAT_REG
);
327 pm_runtime_put_sync(&pdev
->dev
);
330 static int omap_i2c_init(struct omap_i2c_dev
*dev
)
332 u16 psc
= 0, scll
= 0, sclh
= 0, buf
= 0;
333 u16 fsscll
= 0, fssclh
= 0, hsscll
= 0, hssclh
= 0;
334 unsigned long fclk_rate
= 12000000;
335 unsigned long timeout
;
336 unsigned long internal_clk
= 0;
339 if (dev
->rev
>= OMAP_I2C_REV_2
) {
340 /* Disable I2C controller before soft reset */
341 omap_i2c_write_reg(dev
, OMAP_I2C_CON_REG
,
342 omap_i2c_read_reg(dev
, OMAP_I2C_CON_REG
) &
345 omap_i2c_write_reg(dev
, OMAP_I2C_SYSC_REG
, SYSC_SOFTRESET_MASK
);
346 /* For some reason we need to set the EN bit before the
347 * reset done bit gets set. */
348 timeout
= jiffies
+ OMAP_I2C_TIMEOUT
;
349 omap_i2c_write_reg(dev
, OMAP_I2C_CON_REG
, OMAP_I2C_CON_EN
);
350 while (!(omap_i2c_read_reg(dev
, OMAP_I2C_SYSS_REG
) &
351 SYSS_RESETDONE_MASK
)) {
352 if (time_after(jiffies
, timeout
)) {
353 dev_warn(dev
->dev
, "timeout waiting "
354 "for controller reset\n");
360 /* SYSC register is cleared by the reset; rewrite it */
361 if (dev
->rev
== OMAP_I2C_REV_ON_2430
) {
363 omap_i2c_write_reg(dev
, OMAP_I2C_SYSC_REG
,
366 } else if (dev
->rev
>= OMAP_I2C_REV_ON_3430
) {
367 dev
->syscstate
= SYSC_AUTOIDLE_MASK
;
368 dev
->syscstate
|= SYSC_ENAWAKEUP_MASK
;
369 dev
->syscstate
|= (SYSC_IDLEMODE_SMART
<<
370 __ffs(SYSC_SIDLEMODE_MASK
));
371 dev
->syscstate
|= (SYSC_CLOCKACTIVITY_FCLK
<<
372 __ffs(SYSC_CLOCKACTIVITY_MASK
));
374 omap_i2c_write_reg(dev
, OMAP_I2C_SYSC_REG
,
377 * Enabling all wakup sources to stop I2C freezing on
379 * REVISIT: Some wkup sources might not be needed.
381 dev
->westate
= OMAP_I2C_WE_ALL
;
382 omap_i2c_write_reg(dev
, OMAP_I2C_WE_REG
, dev
->westate
);
385 omap_i2c_write_reg(dev
, OMAP_I2C_CON_REG
, 0);
387 if (cpu_class_is_omap1()) {
389 * The I2C functional clock is the armxor_ck, so there's
390 * no need to get "armxor_ck" separately. Now, if OMAP2420
391 * always returns 12MHz for the functional clock, we can
392 * do this bit unconditionally.
394 fclk
= clk_get(dev
->dev
, "fck");
395 fclk_rate
= clk_get_rate(fclk
);
398 /* TRM for 5912 says the I2C clock must be prescaled to be
399 * between 7 - 12 MHz. The XOR input clock is typically
400 * 12, 13 or 19.2 MHz. So we should have code that produces:
402 * XOR MHz Divider Prescaler
407 if (fclk_rate
> 12000000)
408 psc
= fclk_rate
/ 12000000;
411 if (!(cpu_class_is_omap1() || cpu_is_omap2420())) {
414 * HSI2C controller internal clk rate should be 19.2 Mhz for
415 * HS and for all modes on 2430. On 34xx we can use lower rate
416 * to get longer filter period for better noise suppression.
417 * The filter is iclk (fclk for HS) period.
419 if (dev
->speed
> 400 || cpu_is_omap2430())
420 internal_clk
= 19200;
421 else if (dev
->speed
> 100)
425 fclk
= clk_get(dev
->dev
, "fck");
426 fclk_rate
= clk_get_rate(fclk
) / 1000;
429 /* Compute prescaler divisor */
430 psc
= fclk_rate
/ internal_clk
;
433 /* If configured for High Speed */
434 if (dev
->speed
> 400) {
437 /* For first phase of HS mode */
438 scl
= internal_clk
/ 400;
439 fsscll
= scl
- (scl
/ 3) - 7;
440 fssclh
= (scl
/ 3) - 5;
442 /* For second phase of HS mode */
443 scl
= fclk_rate
/ dev
->speed
;
444 hsscll
= scl
- (scl
/ 3) - 7;
445 hssclh
= (scl
/ 3) - 5;
446 } else if (dev
->speed
> 100) {
450 scl
= internal_clk
/ dev
->speed
;
451 fsscll
= scl
- (scl
/ 3) - 7;
452 fssclh
= (scl
/ 3) - 5;
455 fsscll
= internal_clk
/ (dev
->speed
* 2) - 7;
456 fssclh
= internal_clk
/ (dev
->speed
* 2) - 5;
458 scll
= (hsscll
<< OMAP_I2C_SCLL_HSSCLL
) | fsscll
;
459 sclh
= (hssclh
<< OMAP_I2C_SCLH_HSSCLH
) | fssclh
;
461 /* Program desired operating rate */
462 fclk_rate
/= (psc
+ 1) * 1000;
465 scll
= fclk_rate
/ (dev
->speed
* 2) - 7 + psc
;
466 sclh
= fclk_rate
/ (dev
->speed
* 2) - 7 + psc
;
469 /* Setup clock prescaler to obtain approx 12MHz I2C module clock: */
470 omap_i2c_write_reg(dev
, OMAP_I2C_PSC_REG
, psc
);
472 /* SCL low and high time values */
473 omap_i2c_write_reg(dev
, OMAP_I2C_SCLL_REG
, scll
);
474 omap_i2c_write_reg(dev
, OMAP_I2C_SCLH_REG
, sclh
);
476 if (dev
->fifo_size
) {
477 /* Note: setup required fifo size - 1. RTRSH and XTRSH */
478 buf
= (dev
->fifo_size
- 1) << 8 | OMAP_I2C_BUF_RXFIF_CLR
|
479 (dev
->fifo_size
- 1) | OMAP_I2C_BUF_TXFIF_CLR
;
480 omap_i2c_write_reg(dev
, OMAP_I2C_BUF_REG
, buf
);
483 /* Take the I2C module out of reset: */
484 omap_i2c_write_reg(dev
, OMAP_I2C_CON_REG
, OMAP_I2C_CON_EN
);
488 if (cpu_is_omap2430() || cpu_is_omap34xx())
489 dev
->errata
|= I2C_OMAP_ERRATA_I207
;
491 /* Enable interrupts */
492 dev
->iestate
= (OMAP_I2C_IE_XRDY
| OMAP_I2C_IE_RRDY
|
493 OMAP_I2C_IE_ARDY
| OMAP_I2C_IE_NACK
|
494 OMAP_I2C_IE_AL
) | ((dev
->fifo_size
) ?
495 (OMAP_I2C_IE_RDR
| OMAP_I2C_IE_XDR
) : 0);
496 omap_i2c_write_reg(dev
, OMAP_I2C_IE_REG
, dev
->iestate
);
497 if (cpu_is_omap34xx()) {
499 dev
->scllstate
= scll
;
500 dev
->sclhstate
= sclh
;
507 * Waiting on Bus Busy
509 static int omap_i2c_wait_for_bb(struct omap_i2c_dev
*dev
)
511 unsigned long timeout
;
513 timeout
= jiffies
+ OMAP_I2C_TIMEOUT
;
514 while (omap_i2c_read_reg(dev
, OMAP_I2C_STAT_REG
) & OMAP_I2C_STAT_BB
) {
515 if (time_after(jiffies
, timeout
)) {
516 dev_warn(dev
->dev
, "timeout waiting for bus ready\n");
526 * Low level master read/write transaction.
528 static int omap_i2c_xfer_msg(struct i2c_adapter
*adap
,
529 struct i2c_msg
*msg
, int stop
)
531 struct omap_i2c_dev
*dev
= i2c_get_adapdata(adap
);
535 dev_dbg(dev
->dev
, "addr: 0x%04x, len: %d, flags: 0x%x, stop: %d\n",
536 msg
->addr
, msg
->len
, msg
->flags
, stop
);
541 omap_i2c_write_reg(dev
, OMAP_I2C_SA_REG
, msg
->addr
);
543 /* REVISIT: Could the STB bit of I2C_CON be used with probing? */
545 dev
->buf_len
= msg
->len
;
547 omap_i2c_write_reg(dev
, OMAP_I2C_CNT_REG
, dev
->buf_len
);
549 /* Clear the FIFO Buffers */
550 w
= omap_i2c_read_reg(dev
, OMAP_I2C_BUF_REG
);
551 w
|= OMAP_I2C_BUF_RXFIF_CLR
| OMAP_I2C_BUF_TXFIF_CLR
;
552 omap_i2c_write_reg(dev
, OMAP_I2C_BUF_REG
, w
);
554 init_completion(&dev
->cmd_complete
);
557 w
= OMAP_I2C_CON_EN
| OMAP_I2C_CON_MST
| OMAP_I2C_CON_STT
;
559 /* High speed configuration */
560 if (dev
->speed
> 400)
561 w
|= OMAP_I2C_CON_OPMODE_HS
;
563 if (msg
->flags
& I2C_M_TEN
)
564 w
|= OMAP_I2C_CON_XA
;
565 if (!(msg
->flags
& I2C_M_RD
))
566 w
|= OMAP_I2C_CON_TRX
;
568 if (!dev
->b_hw
&& stop
)
569 w
|= OMAP_I2C_CON_STP
;
571 omap_i2c_write_reg(dev
, OMAP_I2C_CON_REG
, w
);
574 * Don't write stt and stp together on some hardware.
576 if (dev
->b_hw
&& stop
) {
577 unsigned long delay
= jiffies
+ OMAP_I2C_TIMEOUT
;
578 u16 con
= omap_i2c_read_reg(dev
, OMAP_I2C_CON_REG
);
579 while (con
& OMAP_I2C_CON_STT
) {
580 con
= omap_i2c_read_reg(dev
, OMAP_I2C_CON_REG
);
582 /* Let the user know if i2c is in a bad state */
583 if (time_after(jiffies
, delay
)) {
584 dev_err(dev
->dev
, "controller timed out "
585 "waiting for start condition to finish\n");
591 w
|= OMAP_I2C_CON_STP
;
592 w
&= ~OMAP_I2C_CON_STT
;
593 omap_i2c_write_reg(dev
, OMAP_I2C_CON_REG
, w
);
597 * REVISIT: We should abort the transfer on signals, but the bus goes
598 * into arbitration and we're currently unable to recover from it.
600 r
= wait_for_completion_timeout(&dev
->cmd_complete
,
606 dev_err(dev
->dev
, "controller timed out\n");
611 if (likely(!dev
->cmd_err
))
614 /* We have an error */
615 if (dev
->cmd_err
& (OMAP_I2C_STAT_AL
| OMAP_I2C_STAT_ROVR
|
616 OMAP_I2C_STAT_XUDF
)) {
621 if (dev
->cmd_err
& OMAP_I2C_STAT_NACK
) {
622 if (msg
->flags
& I2C_M_IGNORE_NAK
)
625 w
= omap_i2c_read_reg(dev
, OMAP_I2C_CON_REG
);
626 w
|= OMAP_I2C_CON_STP
;
627 omap_i2c_write_reg(dev
, OMAP_I2C_CON_REG
, w
);
636 * Prepare controller for a transaction and call omap_i2c_xfer_msg
637 * to do the work during IRQ processing.
640 omap_i2c_xfer(struct i2c_adapter
*adap
, struct i2c_msg msgs
[], int num
)
642 struct omap_i2c_dev
*dev
= i2c_get_adapdata(adap
);
646 omap_i2c_unidle(dev
);
648 r
= omap_i2c_wait_for_bb(dev
);
652 if (dev
->set_mpu_wkup_lat
!= NULL
)
653 dev
->set_mpu_wkup_lat(dev
->dev
, dev
->latency
);
655 for (i
= 0; i
< num
; i
++) {
656 r
= omap_i2c_xfer_msg(adap
, &msgs
[i
], (i
== (num
- 1)));
661 if (dev
->set_mpu_wkup_lat
!= NULL
)
662 dev
->set_mpu_wkup_lat(dev
->dev
, -1);
667 omap_i2c_wait_for_bb(dev
);
674 omap_i2c_func(struct i2c_adapter
*adap
)
676 return I2C_FUNC_I2C
| (I2C_FUNC_SMBUS_EMUL
& ~I2C_FUNC_SMBUS_QUICK
);
680 omap_i2c_complete_cmd(struct omap_i2c_dev
*dev
, u16 err
)
683 complete(&dev
->cmd_complete
);
687 omap_i2c_ack_stat(struct omap_i2c_dev
*dev
, u16 stat
)
689 omap_i2c_write_reg(dev
, OMAP_I2C_STAT_REG
, stat
);
692 static inline void i2c_omap_errata_i207(struct omap_i2c_dev
*dev
, u16 stat
)
695 * I2C Errata(Errata Nos. OMAP2: 1.67, OMAP3: 1.8)
696 * Not applicable for OMAP4.
697 * Under certain rare conditions, RDR could be set again
698 * when the bus is busy, then ignore the interrupt and
699 * clear the interrupt.
701 if (stat
& OMAP_I2C_STAT_RDR
) {
702 /* Step 1: If RDR is set, clear it */
703 omap_i2c_ack_stat(dev
, OMAP_I2C_STAT_RDR
);
706 if (!(omap_i2c_read_reg(dev
, OMAP_I2C_STAT_REG
)
707 & OMAP_I2C_STAT_BB
)) {
710 if (omap_i2c_read_reg(dev
, OMAP_I2C_STAT_REG
)
711 & OMAP_I2C_STAT_RDR
) {
712 omap_i2c_ack_stat(dev
, OMAP_I2C_STAT_RDR
);
713 dev_dbg(dev
->dev
, "RDR when bus is busy.\n");
720 /* rev1 devices are apparently only on some 15xx */
721 #ifdef CONFIG_ARCH_OMAP15XX
724 omap_i2c_rev1_isr(int this_irq
, void *dev_id
)
726 struct omap_i2c_dev
*dev
= dev_id
;
732 iv
= omap_i2c_read_reg(dev
, OMAP_I2C_IV_REG
);
734 case 0x00: /* None */
736 case 0x01: /* Arbitration lost */
737 dev_err(dev
->dev
, "Arbitration lost\n");
738 omap_i2c_complete_cmd(dev
, OMAP_I2C_STAT_AL
);
740 case 0x02: /* No acknowledgement */
741 omap_i2c_complete_cmd(dev
, OMAP_I2C_STAT_NACK
);
742 omap_i2c_write_reg(dev
, OMAP_I2C_CON_REG
, OMAP_I2C_CON_STP
);
744 case 0x03: /* Register access ready */
745 omap_i2c_complete_cmd(dev
, 0);
747 case 0x04: /* Receive data ready */
749 w
= omap_i2c_read_reg(dev
, OMAP_I2C_DATA_REG
);
753 *dev
->buf
++ = w
>> 8;
757 dev_err(dev
->dev
, "RRDY IRQ while no data requested\n");
759 case 0x05: /* Transmit data ready */
764 w
|= *dev
->buf
++ << 8;
767 omap_i2c_write_reg(dev
, OMAP_I2C_DATA_REG
, w
);
769 dev_err(dev
->dev
, "XRDY IRQ while no data to send\n");
778 #define omap_i2c_rev1_isr NULL
782 * OMAP3430 Errata 1.153: When an XRDY/XDR is hit, wait for XUDF before writing
783 * data to DATA_REG. Otherwise some data bytes can be lost while transferring
784 * them from the memory to the I2C interface.
786 static int errata_omap3_1p153(struct omap_i2c_dev
*dev
, u16
*stat
, int *err
)
788 unsigned long timeout
= 10000;
790 while (--timeout
&& !(*stat
& OMAP_I2C_STAT_XUDF
)) {
791 if (*stat
& (OMAP_I2C_STAT_NACK
| OMAP_I2C_STAT_AL
)) {
792 omap_i2c_ack_stat(dev
, *stat
& (OMAP_I2C_STAT_XRDY
|
794 *err
|= OMAP_I2C_STAT_XUDF
;
799 *stat
= omap_i2c_read_reg(dev
, OMAP_I2C_STAT_REG
);
803 dev_err(dev
->dev
, "timeout waiting on XUDF bit\n");
811 omap_i2c_isr(int this_irq
, void *dev_id
)
813 struct omap_i2c_dev
*dev
= dev_id
;
821 bits
= omap_i2c_read_reg(dev
, OMAP_I2C_IE_REG
);
822 while ((stat
= (omap_i2c_read_reg(dev
, OMAP_I2C_STAT_REG
))) & bits
) {
823 dev_dbg(dev
->dev
, "IRQ (ISR = 0x%04x)\n", stat
);
824 if (count
++ == 100) {
825 dev_warn(dev
->dev
, "Too much work in one IRQ\n");
832 * Ack the stat in one go, but [R/X]DR and [R/X]RDY should be
833 * acked after the data operation is complete.
834 * Ref: TRM SWPU114Q Figure 18-31
836 omap_i2c_write_reg(dev
, OMAP_I2C_STAT_REG
, stat
&
837 ~(OMAP_I2C_STAT_RRDY
| OMAP_I2C_STAT_RDR
|
838 OMAP_I2C_STAT_XRDY
| OMAP_I2C_STAT_XDR
));
840 if (stat
& OMAP_I2C_STAT_NACK
) {
841 err
|= OMAP_I2C_STAT_NACK
;
842 omap_i2c_write_reg(dev
, OMAP_I2C_CON_REG
,
845 if (stat
& OMAP_I2C_STAT_AL
) {
846 dev_err(dev
->dev
, "Arbitration lost\n");
847 err
|= OMAP_I2C_STAT_AL
;
850 * ProDB0017052: Clear ARDY bit twice
852 if (stat
& (OMAP_I2C_STAT_ARDY
| OMAP_I2C_STAT_NACK
|
854 omap_i2c_ack_stat(dev
, stat
&
855 (OMAP_I2C_STAT_RRDY
| OMAP_I2C_STAT_RDR
|
856 OMAP_I2C_STAT_XRDY
| OMAP_I2C_STAT_XDR
|
857 OMAP_I2C_STAT_ARDY
));
858 omap_i2c_complete_cmd(dev
, err
);
861 if (stat
& (OMAP_I2C_STAT_RRDY
| OMAP_I2C_STAT_RDR
)) {
864 if (dev
->errata
& I2C_OMAP_ERRATA_I207
)
865 i2c_omap_errata_i207(dev
, stat
);
867 if (dev
->fifo_size
) {
868 if (stat
& OMAP_I2C_STAT_RRDY
)
869 num_bytes
= dev
->fifo_size
;
870 else /* read RXSTAT on RDR interrupt */
871 num_bytes
= (omap_i2c_read_reg(dev
,
872 OMAP_I2C_BUFSTAT_REG
)
877 w
= omap_i2c_read_reg(dev
, OMAP_I2C_DATA_REG
);
882 * Data reg in 2430, omap3 and
883 * omap4 is 8 bit wide
885 if (cpu_class_is_omap1() ||
888 *dev
->buf
++ = w
>> 8;
893 if (stat
& OMAP_I2C_STAT_RRDY
)
895 "RRDY IRQ while no data"
897 if (stat
& OMAP_I2C_STAT_RDR
)
899 "RDR IRQ while no data"
904 omap_i2c_ack_stat(dev
,
905 stat
& (OMAP_I2C_STAT_RRDY
| OMAP_I2C_STAT_RDR
));
908 if (stat
& (OMAP_I2C_STAT_XRDY
| OMAP_I2C_STAT_XDR
)) {
910 if (dev
->fifo_size
) {
911 if (stat
& OMAP_I2C_STAT_XRDY
)
912 num_bytes
= dev
->fifo_size
;
913 else /* read TXSTAT on XDR interrupt */
914 num_bytes
= omap_i2c_read_reg(dev
,
915 OMAP_I2C_BUFSTAT_REG
)
925 * Data reg in 2430, omap3 and
926 * omap4 is 8 bit wide
928 if (cpu_class_is_omap1() ||
931 w
|= *dev
->buf
++ << 8;
936 if (stat
& OMAP_I2C_STAT_XRDY
)
940 if (stat
& OMAP_I2C_STAT_XDR
)
947 if ((dev
->errata
& I2C_OMAP3_1P153
) &&
948 errata_omap3_1p153(dev
, &stat
, &err
))
951 omap_i2c_write_reg(dev
, OMAP_I2C_DATA_REG
, w
);
953 omap_i2c_ack_stat(dev
,
954 stat
& (OMAP_I2C_STAT_XRDY
| OMAP_I2C_STAT_XDR
));
957 if (stat
& OMAP_I2C_STAT_ROVR
) {
958 dev_err(dev
->dev
, "Receive overrun\n");
959 dev
->cmd_err
|= OMAP_I2C_STAT_ROVR
;
961 if (stat
& OMAP_I2C_STAT_XUDF
) {
962 dev_err(dev
->dev
, "Transmit underflow\n");
963 dev
->cmd_err
|= OMAP_I2C_STAT_XUDF
;
967 return count
? IRQ_HANDLED
: IRQ_NONE
;
970 static const struct i2c_algorithm omap_i2c_algo
= {
971 .master_xfer
= omap_i2c_xfer
,
972 .functionality
= omap_i2c_func
,
976 omap_i2c_probe(struct platform_device
*pdev
)
978 struct omap_i2c_dev
*dev
;
979 struct i2c_adapter
*adap
;
980 struct resource
*mem
, *irq
, *ioarea
;
981 struct omap_i2c_bus_platform_data
*pdata
= pdev
->dev
.platform_data
;
986 /* NOTE: driver uses the static register mapping */
987 mem
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
989 dev_err(&pdev
->dev
, "no mem resource?\n");
992 irq
= platform_get_resource(pdev
, IORESOURCE_IRQ
, 0);
994 dev_err(&pdev
->dev
, "no irq resource?\n");
998 ioarea
= request_mem_region(mem
->start
, resource_size(mem
),
1001 dev_err(&pdev
->dev
, "I2C region already claimed\n");
1005 dev
= kzalloc(sizeof(struct omap_i2c_dev
), GFP_KERNEL
);
1008 goto err_release_region
;
1011 if (pdata
!= NULL
) {
1012 speed
= pdata
->clkrate
;
1013 dev
->set_mpu_wkup_lat
= pdata
->set_mpu_wkup_lat
;
1015 speed
= 100; /* Default speed */
1016 dev
->set_mpu_wkup_lat
= NULL
;
1021 dev
->dev
= &pdev
->dev
;
1022 dev
->irq
= irq
->start
;
1023 dev
->base
= ioremap(mem
->start
, resource_size(mem
));
1029 platform_set_drvdata(pdev
, dev
);
1031 if (cpu_is_omap7xx())
1033 else if (cpu_is_omap44xx())
1038 if (pdata
->rev
== OMAP_I2C_IP_VERSION_2
)
1039 dev
->regs
= (u8
*)reg_map_ip_v2
;
1041 dev
->regs
= (u8
*)reg_map_ip_v1
;
1043 pm_runtime_enable(&pdev
->dev
);
1044 omap_i2c_unidle(dev
);
1046 dev
->rev
= omap_i2c_read_reg(dev
, OMAP_I2C_REV_REG
) & 0xff;
1048 if (dev
->rev
<= OMAP_I2C_REV_ON_3430
)
1049 dev
->errata
|= I2C_OMAP3_1P153
;
1051 if (!(cpu_class_is_omap1() || cpu_is_omap2420())) {
1054 /* Set up the fifo size - Get total size */
1055 s
= (omap_i2c_read_reg(dev
, OMAP_I2C_BUFSTAT_REG
) >> 14) & 0x3;
1056 dev
->fifo_size
= 0x8 << s
;
1059 * Set up notification threshold as half the total available
1060 * size. This is to ensure that we can handle the status on int
1061 * call back latencies.
1063 if (dev
->rev
>= OMAP_I2C_REV_ON_4430
) {
1065 dev
->b_hw
= 0; /* Disable hardware fixes */
1067 dev
->fifo_size
= (dev
->fifo_size
/ 2);
1068 dev
->b_hw
= 1; /* Enable hardware fixes */
1070 /* calculate wakeup latency constraint for MPU */
1071 if (dev
->set_mpu_wkup_lat
!= NULL
)
1072 dev
->latency
= (1000000 * dev
->fifo_size
) /
1076 /* reset ASAP, clearing any IRQs */
1079 isr
= (dev
->rev
< OMAP_I2C_REV_2
) ? omap_i2c_rev1_isr
: omap_i2c_isr
;
1080 r
= request_irq(dev
->irq
, isr
, 0, pdev
->name
, dev
);
1083 dev_err(dev
->dev
, "failure requesting irq %i\n", dev
->irq
);
1084 goto err_unuse_clocks
;
1087 dev_info(dev
->dev
, "bus %d rev%d.%d at %d kHz\n",
1088 pdev
->id
, dev
->rev
>> 4, dev
->rev
& 0xf, dev
->speed
);
1092 adap
= &dev
->adapter
;
1093 i2c_set_adapdata(adap
, dev
);
1094 adap
->owner
= THIS_MODULE
;
1095 adap
->class = I2C_CLASS_HWMON
;
1096 strlcpy(adap
->name
, "OMAP I2C adapter", sizeof(adap
->name
));
1097 adap
->algo
= &omap_i2c_algo
;
1098 adap
->dev
.parent
= &pdev
->dev
;
1100 /* i2c device drivers may be active on return from add_adapter() */
1101 adap
->nr
= pdev
->id
;
1102 r
= i2c_add_numbered_adapter(adap
);
1104 dev_err(dev
->dev
, "failure adding adapter\n");
1111 free_irq(dev
->irq
, dev
);
1113 omap_i2c_write_reg(dev
, OMAP_I2C_CON_REG
, 0);
1117 platform_set_drvdata(pdev
, NULL
);
1120 release_mem_region(mem
->start
, resource_size(mem
));
1126 omap_i2c_remove(struct platform_device
*pdev
)
1128 struct omap_i2c_dev
*dev
= platform_get_drvdata(pdev
);
1129 struct resource
*mem
;
1131 platform_set_drvdata(pdev
, NULL
);
1133 free_irq(dev
->irq
, dev
);
1134 i2c_del_adapter(&dev
->adapter
);
1135 omap_i2c_write_reg(dev
, OMAP_I2C_CON_REG
, 0);
1138 mem
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1139 release_mem_region(mem
->start
, resource_size(mem
));
1143 static struct platform_driver omap_i2c_driver
= {
1144 .probe
= omap_i2c_probe
,
1145 .remove
= omap_i2c_remove
,
1148 .owner
= THIS_MODULE
,
1152 /* I2C may be needed to bring up other drivers */
1154 omap_i2c_init_driver(void)
1156 return platform_driver_register(&omap_i2c_driver
);
1158 subsys_initcall(omap_i2c_init_driver
);
1160 static void __exit
omap_i2c_exit_driver(void)
1162 platform_driver_unregister(&omap_i2c_driver
);
1164 module_exit(omap_i2c_exit_driver
);
1166 MODULE_AUTHOR("MontaVista Software, Inc. (and others)");
1167 MODULE_DESCRIPTION("TI OMAP I2C bus adapter");
1168 MODULE_LICENSE("GPL");
1169 MODULE_ALIAS("platform:omap_i2c");