2 * TI OMAP I2C master mode driver
4 * Copyright (C) 2003 MontaVista Software, Inc.
5 * Copyright (C) 2005 Nokia Corporation
6 * Copyright (C) 2004 - 2007 Texas Instruments.
8 * Originally written by MontaVista Software, Inc.
9 * Additional contributions by:
10 * Tony Lindgren <tony@atomide.com>
11 * Imre Deak <imre.deak@nokia.com>
12 * Juha Yrjölä <juha.yrjola@solidboot.com>
13 * Syed Khasim <x0khasim@ti.com>
14 * Nishant Menon <nm@ti.com>
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License as published by
18 * the Free Software Foundation; either version 2 of the License, or
19 * (at your option) any later version.
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
26 * You should have received a copy of the GNU General Public License
27 * along with this program; if not, write to the Free Software
28 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
31 #include <linux/module.h>
32 #include <linux/delay.h>
33 #include <linux/i2c.h>
34 #include <linux/err.h>
35 #include <linux/interrupt.h>
36 #include <linux/completion.h>
37 #include <linux/platform_device.h>
38 #include <linux/clk.h>
41 /* I2C controller revisions */
42 #define OMAP_I2C_REV_2 0x20
44 /* I2C controller revisions present on specific hardware */
45 #define OMAP_I2C_REV_ON_2430 0x36
46 #define OMAP_I2C_REV_ON_3430 0x3C
48 /* timeout waiting for the controller to respond */
49 #define OMAP_I2C_TIMEOUT (msecs_to_jiffies(1000))
51 #define OMAP_I2C_REV_REG 0x00
52 #define OMAP_I2C_IE_REG 0x01
53 #define OMAP_I2C_STAT_REG 0x02
54 #define OMAP_I2C_IV_REG 0x03
55 /* For OMAP3 I2C_IV has changed to I2C_WE (wakeup enable) */
56 #define OMAP_I2C_WE_REG 0x03
57 #define OMAP_I2C_SYSS_REG 0x04
58 #define OMAP_I2C_BUF_REG 0x05
59 #define OMAP_I2C_CNT_REG 0x06
60 #define OMAP_I2C_DATA_REG 0x07
61 #define OMAP_I2C_SYSC_REG 0x08
62 #define OMAP_I2C_CON_REG 0x09
63 #define OMAP_I2C_OA_REG 0x0a
64 #define OMAP_I2C_SA_REG 0x0b
65 #define OMAP_I2C_PSC_REG 0x0c
66 #define OMAP_I2C_SCLL_REG 0x0d
67 #define OMAP_I2C_SCLH_REG 0x0e
68 #define OMAP_I2C_SYSTEST_REG 0x0f
69 #define OMAP_I2C_BUFSTAT_REG 0x10
71 /* I2C Interrupt Enable Register (OMAP_I2C_IE): */
72 #define OMAP_I2C_IE_XDR (1 << 14) /* TX Buffer drain int enable */
73 #define OMAP_I2C_IE_RDR (1 << 13) /* RX Buffer drain int enable */
74 #define OMAP_I2C_IE_XRDY (1 << 4) /* TX data ready int enable */
75 #define OMAP_I2C_IE_RRDY (1 << 3) /* RX data ready int enable */
76 #define OMAP_I2C_IE_ARDY (1 << 2) /* Access ready int enable */
77 #define OMAP_I2C_IE_NACK (1 << 1) /* No ack interrupt enable */
78 #define OMAP_I2C_IE_AL (1 << 0) /* Arbitration lost int ena */
80 /* I2C Status Register (OMAP_I2C_STAT): */
81 #define OMAP_I2C_STAT_XDR (1 << 14) /* TX Buffer draining */
82 #define OMAP_I2C_STAT_RDR (1 << 13) /* RX Buffer draining */
83 #define OMAP_I2C_STAT_BB (1 << 12) /* Bus busy */
84 #define OMAP_I2C_STAT_ROVR (1 << 11) /* Receive overrun */
85 #define OMAP_I2C_STAT_XUDF (1 << 10) /* Transmit underflow */
86 #define OMAP_I2C_STAT_AAS (1 << 9) /* Address as slave */
87 #define OMAP_I2C_STAT_AD0 (1 << 8) /* Address zero */
88 #define OMAP_I2C_STAT_XRDY (1 << 4) /* Transmit data ready */
89 #define OMAP_I2C_STAT_RRDY (1 << 3) /* Receive data ready */
90 #define OMAP_I2C_STAT_ARDY (1 << 2) /* Register access ready */
91 #define OMAP_I2C_STAT_NACK (1 << 1) /* No ack interrupt enable */
92 #define OMAP_I2C_STAT_AL (1 << 0) /* Arbitration lost int ena */
94 /* I2C WE wakeup enable register */
95 #define OMAP_I2C_WE_XDR_WE (1 << 14) /* TX drain wakup */
96 #define OMAP_I2C_WE_RDR_WE (1 << 13) /* RX drain wakeup */
97 #define OMAP_I2C_WE_AAS_WE (1 << 9) /* Address as slave wakeup*/
98 #define OMAP_I2C_WE_BF_WE (1 << 8) /* Bus free wakeup */
99 #define OMAP_I2C_WE_STC_WE (1 << 6) /* Start condition wakeup */
100 #define OMAP_I2C_WE_GC_WE (1 << 5) /* General call wakeup */
101 #define OMAP_I2C_WE_DRDY_WE (1 << 3) /* TX/RX data ready wakeup */
102 #define OMAP_I2C_WE_ARDY_WE (1 << 2) /* Reg access ready wakeup */
103 #define OMAP_I2C_WE_NACK_WE (1 << 1) /* No acknowledgment wakeup */
104 #define OMAP_I2C_WE_AL_WE (1 << 0) /* Arbitration lost wakeup */
106 #define OMAP_I2C_WE_ALL (OMAP_I2C_WE_XDR_WE | OMAP_I2C_WE_RDR_WE | \
107 OMAP_I2C_WE_AAS_WE | OMAP_I2C_WE_BF_WE | \
108 OMAP_I2C_WE_STC_WE | OMAP_I2C_WE_GC_WE | \
109 OMAP_I2C_WE_DRDY_WE | OMAP_I2C_WE_ARDY_WE | \
110 OMAP_I2C_WE_NACK_WE | OMAP_I2C_WE_AL_WE)
112 /* I2C Buffer Configuration Register (OMAP_I2C_BUF): */
113 #define OMAP_I2C_BUF_RDMA_EN (1 << 15) /* RX DMA channel enable */
114 #define OMAP_I2C_BUF_RXFIF_CLR (1 << 14) /* RX FIFO Clear */
115 #define OMAP_I2C_BUF_XDMA_EN (1 << 7) /* TX DMA channel enable */
116 #define OMAP_I2C_BUF_TXFIF_CLR (1 << 6) /* TX FIFO Clear */
118 /* I2C Configuration Register (OMAP_I2C_CON): */
119 #define OMAP_I2C_CON_EN (1 << 15) /* I2C module enable */
120 #define OMAP_I2C_CON_BE (1 << 14) /* Big endian mode */
121 #define OMAP_I2C_CON_OPMODE_HS (1 << 12) /* High Speed support */
122 #define OMAP_I2C_CON_STB (1 << 11) /* Start byte mode (master) */
123 #define OMAP_I2C_CON_MST (1 << 10) /* Master/slave mode */
124 #define OMAP_I2C_CON_TRX (1 << 9) /* TX/RX mode (master only) */
125 #define OMAP_I2C_CON_XA (1 << 8) /* Expand address */
126 #define OMAP_I2C_CON_RM (1 << 2) /* Repeat mode (master only) */
127 #define OMAP_I2C_CON_STP (1 << 1) /* Stop cond (master only) */
128 #define OMAP_I2C_CON_STT (1 << 0) /* Start condition (master) */
130 /* I2C SCL time value when Master */
131 #define OMAP_I2C_SCLL_HSSCLL 8
132 #define OMAP_I2C_SCLH_HSSCLH 8
134 /* I2C System Test Register (OMAP_I2C_SYSTEST): */
136 #define OMAP_I2C_SYSTEST_ST_EN (1 << 15) /* System test enable */
137 #define OMAP_I2C_SYSTEST_FREE (1 << 14) /* Free running mode */
138 #define OMAP_I2C_SYSTEST_TMODE_MASK (3 << 12) /* Test mode select */
139 #define OMAP_I2C_SYSTEST_TMODE_SHIFT (12) /* Test mode select */
140 #define OMAP_I2C_SYSTEST_SCL_I (1 << 3) /* SCL line sense in */
141 #define OMAP_I2C_SYSTEST_SCL_O (1 << 2) /* SCL line drive out */
142 #define OMAP_I2C_SYSTEST_SDA_I (1 << 1) /* SDA line sense in */
143 #define OMAP_I2C_SYSTEST_SDA_O (1 << 0) /* SDA line drive out */
146 /* OCP_SYSSTATUS bit definitions */
147 #define SYSS_RESETDONE_MASK (1 << 0)
149 /* OCP_SYSCONFIG bit definitions */
150 #define SYSC_CLOCKACTIVITY_MASK (0x3 << 8)
151 #define SYSC_SIDLEMODE_MASK (0x3 << 3)
152 #define SYSC_ENAWAKEUP_MASK (1 << 2)
153 #define SYSC_SOFTRESET_MASK (1 << 1)
154 #define SYSC_AUTOIDLE_MASK (1 << 0)
156 #define SYSC_IDLEMODE_SMART 0x2
157 #define SYSC_CLOCKACTIVITY_FCLK 0x2
160 struct omap_i2c_dev
{
162 void __iomem
*base
; /* virtual */
164 int reg_shift
; /* bit shift for I2C register addresses */
165 struct clk
*iclk
; /* Interface clock */
166 struct clk
*fclk
; /* Functional clock */
167 struct completion cmd_complete
;
168 struct resource
*ioarea
;
169 u32 speed
; /* Speed of bus in Khz */
173 struct i2c_adapter adapter
;
174 u8 fifo_size
; /* use as flag and value
175 * fifo_size==0 implies no fifo
176 * if set, should be trsh+1
179 unsigned b_hw
:1; /* bad h/w fixes */
181 u16 iestate
; /* Saved interrupt register */
190 static inline void omap_i2c_write_reg(struct omap_i2c_dev
*i2c_dev
,
193 __raw_writew(val
, i2c_dev
->base
+ (reg
<< i2c_dev
->reg_shift
));
196 static inline u16
omap_i2c_read_reg(struct omap_i2c_dev
*i2c_dev
, int reg
)
198 return __raw_readw(i2c_dev
->base
+ (reg
<< i2c_dev
->reg_shift
));
201 static int __init
omap_i2c_get_clocks(struct omap_i2c_dev
*dev
)
205 dev
->iclk
= clk_get(dev
->dev
, "ick");
206 if (IS_ERR(dev
->iclk
)) {
207 ret
= PTR_ERR(dev
->iclk
);
212 dev
->fclk
= clk_get(dev
->dev
, "fck");
213 if (IS_ERR(dev
->fclk
)) {
214 ret
= PTR_ERR(dev
->fclk
);
215 if (dev
->iclk
!= NULL
) {
226 static void omap_i2c_put_clocks(struct omap_i2c_dev
*dev
)
234 static void omap_i2c_unidle(struct omap_i2c_dev
*dev
)
238 clk_enable(dev
->iclk
);
239 clk_enable(dev
->fclk
);
240 if (cpu_is_omap34xx()) {
241 omap_i2c_write_reg(dev
, OMAP_I2C_CON_REG
, 0);
242 omap_i2c_write_reg(dev
, OMAP_I2C_PSC_REG
, dev
->pscstate
);
243 omap_i2c_write_reg(dev
, OMAP_I2C_SCLL_REG
, dev
->scllstate
);
244 omap_i2c_write_reg(dev
, OMAP_I2C_SCLH_REG
, dev
->sclhstate
);
245 omap_i2c_write_reg(dev
, OMAP_I2C_BUF_REG
, dev
->bufstate
);
246 omap_i2c_write_reg(dev
, OMAP_I2C_SYSC_REG
, dev
->syscstate
);
247 omap_i2c_write_reg(dev
, OMAP_I2C_WE_REG
, dev
->westate
);
248 omap_i2c_write_reg(dev
, OMAP_I2C_CON_REG
, OMAP_I2C_CON_EN
);
253 * Don't write to this register if the IE state is 0 as it can
257 omap_i2c_write_reg(dev
, OMAP_I2C_IE_REG
, dev
->iestate
);
260 static void omap_i2c_idle(struct omap_i2c_dev
*dev
)
266 dev
->iestate
= omap_i2c_read_reg(dev
, OMAP_I2C_IE_REG
);
267 omap_i2c_write_reg(dev
, OMAP_I2C_IE_REG
, 0);
268 if (dev
->rev
< OMAP_I2C_REV_2
) {
269 iv
= omap_i2c_read_reg(dev
, OMAP_I2C_IV_REG
); /* Read clears */
271 omap_i2c_write_reg(dev
, OMAP_I2C_STAT_REG
, dev
->iestate
);
273 /* Flush posted write before the dev->idle store occurs */
274 omap_i2c_read_reg(dev
, OMAP_I2C_STAT_REG
);
277 clk_disable(dev
->fclk
);
278 clk_disable(dev
->iclk
);
281 static int omap_i2c_init(struct omap_i2c_dev
*dev
)
283 u16 psc
= 0, scll
= 0, sclh
= 0, buf
= 0;
284 u16 fsscll
= 0, fssclh
= 0, hsscll
= 0, hssclh
= 0;
285 unsigned long fclk_rate
= 12000000;
286 unsigned long timeout
;
287 unsigned long internal_clk
= 0;
289 if (dev
->rev
>= OMAP_I2C_REV_2
) {
290 /* Disable I2C controller before soft reset */
291 omap_i2c_write_reg(dev
, OMAP_I2C_CON_REG
,
292 omap_i2c_read_reg(dev
, OMAP_I2C_CON_REG
) &
295 omap_i2c_write_reg(dev
, OMAP_I2C_SYSC_REG
, SYSC_SOFTRESET_MASK
);
296 /* For some reason we need to set the EN bit before the
297 * reset done bit gets set. */
298 timeout
= jiffies
+ OMAP_I2C_TIMEOUT
;
299 omap_i2c_write_reg(dev
, OMAP_I2C_CON_REG
, OMAP_I2C_CON_EN
);
300 while (!(omap_i2c_read_reg(dev
, OMAP_I2C_SYSS_REG
) &
301 SYSS_RESETDONE_MASK
)) {
302 if (time_after(jiffies
, timeout
)) {
303 dev_warn(dev
->dev
, "timeout waiting "
304 "for controller reset\n");
310 /* SYSC register is cleared by the reset; rewrite it */
311 if (dev
->rev
== OMAP_I2C_REV_ON_2430
) {
313 omap_i2c_write_reg(dev
, OMAP_I2C_SYSC_REG
,
316 } else if (dev
->rev
>= OMAP_I2C_REV_ON_3430
) {
317 dev
->syscstate
= SYSC_AUTOIDLE_MASK
;
318 dev
->syscstate
|= SYSC_ENAWAKEUP_MASK
;
319 dev
->syscstate
|= (SYSC_IDLEMODE_SMART
<<
320 __ffs(SYSC_SIDLEMODE_MASK
));
321 dev
->syscstate
|= (SYSC_CLOCKACTIVITY_FCLK
<<
322 __ffs(SYSC_CLOCKACTIVITY_MASK
));
324 omap_i2c_write_reg(dev
, OMAP_I2C_SYSC_REG
,
327 * Enabling all wakup sources to stop I2C freezing on
329 * REVISIT: Some wkup sources might not be needed.
331 dev
->westate
= OMAP_I2C_WE_ALL
;
332 omap_i2c_write_reg(dev
, OMAP_I2C_WE_REG
, dev
->westate
);
335 omap_i2c_write_reg(dev
, OMAP_I2C_CON_REG
, 0);
337 if (cpu_class_is_omap1()) {
339 * The I2C functional clock is the armxor_ck, so there's
340 * no need to get "armxor_ck" separately. Now, if OMAP2420
341 * always returns 12MHz for the functional clock, we can
342 * do this bit unconditionally.
344 fclk_rate
= clk_get_rate(dev
->fclk
);
346 /* TRM for 5912 says the I2C clock must be prescaled to be
347 * between 7 - 12 MHz. The XOR input clock is typically
348 * 12, 13 or 19.2 MHz. So we should have code that produces:
350 * XOR MHz Divider Prescaler
355 if (fclk_rate
> 12000000)
356 psc
= fclk_rate
/ 12000000;
359 if (cpu_is_omap2430() || cpu_is_omap34xx()) {
362 * HSI2C controller internal clk rate should be 19.2 Mhz for
363 * HS and for all modes on 2430. On 34xx we can use lower rate
364 * to get longer filter period for better noise suppression.
365 * The filter is iclk (fclk for HS) period.
367 if (dev
->speed
> 400 || cpu_is_omap2430())
368 internal_clk
= 19200;
369 else if (dev
->speed
> 100)
373 fclk_rate
= clk_get_rate(dev
->fclk
) / 1000;
375 /* Compute prescaler divisor */
376 psc
= fclk_rate
/ internal_clk
;
379 /* If configured for High Speed */
380 if (dev
->speed
> 400) {
383 /* For first phase of HS mode */
384 scl
= internal_clk
/ 400;
385 fsscll
= scl
- (scl
/ 3) - 7;
386 fssclh
= (scl
/ 3) - 5;
388 /* For second phase of HS mode */
389 scl
= fclk_rate
/ dev
->speed
;
390 hsscll
= scl
- (scl
/ 3) - 7;
391 hssclh
= (scl
/ 3) - 5;
392 } else if (dev
->speed
> 100) {
396 scl
= internal_clk
/ dev
->speed
;
397 fsscll
= scl
- (scl
/ 3) - 7;
398 fssclh
= (scl
/ 3) - 5;
401 fsscll
= internal_clk
/ (dev
->speed
* 2) - 7;
402 fssclh
= internal_clk
/ (dev
->speed
* 2) - 5;
404 scll
= (hsscll
<< OMAP_I2C_SCLL_HSSCLL
) | fsscll
;
405 sclh
= (hssclh
<< OMAP_I2C_SCLH_HSSCLH
) | fssclh
;
407 /* Program desired operating rate */
408 fclk_rate
/= (psc
+ 1) * 1000;
411 scll
= fclk_rate
/ (dev
->speed
* 2) - 7 + psc
;
412 sclh
= fclk_rate
/ (dev
->speed
* 2) - 7 + psc
;
415 /* Setup clock prescaler to obtain approx 12MHz I2C module clock: */
416 omap_i2c_write_reg(dev
, OMAP_I2C_PSC_REG
, psc
);
418 /* SCL low and high time values */
419 omap_i2c_write_reg(dev
, OMAP_I2C_SCLL_REG
, scll
);
420 omap_i2c_write_reg(dev
, OMAP_I2C_SCLH_REG
, sclh
);
422 if (dev
->fifo_size
) {
423 /* Note: setup required fifo size - 1. RTRSH and XTRSH */
424 buf
= (dev
->fifo_size
- 1) << 8 | OMAP_I2C_BUF_RXFIF_CLR
|
425 (dev
->fifo_size
- 1) | OMAP_I2C_BUF_TXFIF_CLR
;
426 omap_i2c_write_reg(dev
, OMAP_I2C_BUF_REG
, buf
);
429 /* Take the I2C module out of reset: */
430 omap_i2c_write_reg(dev
, OMAP_I2C_CON_REG
, OMAP_I2C_CON_EN
);
432 /* Enable interrupts */
433 dev
->iestate
= (OMAP_I2C_IE_XRDY
| OMAP_I2C_IE_RRDY
|
434 OMAP_I2C_IE_ARDY
| OMAP_I2C_IE_NACK
|
435 OMAP_I2C_IE_AL
) | ((dev
->fifo_size
) ?
436 (OMAP_I2C_IE_RDR
| OMAP_I2C_IE_XDR
) : 0);
437 omap_i2c_write_reg(dev
, OMAP_I2C_IE_REG
, dev
->iestate
);
438 if (cpu_is_omap34xx()) {
440 dev
->scllstate
= scll
;
441 dev
->sclhstate
= sclh
;
448 * Waiting on Bus Busy
450 static int omap_i2c_wait_for_bb(struct omap_i2c_dev
*dev
)
452 unsigned long timeout
;
454 timeout
= jiffies
+ OMAP_I2C_TIMEOUT
;
455 while (omap_i2c_read_reg(dev
, OMAP_I2C_STAT_REG
) & OMAP_I2C_STAT_BB
) {
456 if (time_after(jiffies
, timeout
)) {
457 dev_warn(dev
->dev
, "timeout waiting for bus ready\n");
467 * Low level master read/write transaction.
469 static int omap_i2c_xfer_msg(struct i2c_adapter
*adap
,
470 struct i2c_msg
*msg
, int stop
)
472 struct omap_i2c_dev
*dev
= i2c_get_adapdata(adap
);
476 dev_dbg(dev
->dev
, "addr: 0x%04x, len: %d, flags: 0x%x, stop: %d\n",
477 msg
->addr
, msg
->len
, msg
->flags
, stop
);
482 omap_i2c_write_reg(dev
, OMAP_I2C_SA_REG
, msg
->addr
);
484 /* REVISIT: Could the STB bit of I2C_CON be used with probing? */
486 dev
->buf_len
= msg
->len
;
488 omap_i2c_write_reg(dev
, OMAP_I2C_CNT_REG
, dev
->buf_len
);
490 /* Clear the FIFO Buffers */
491 w
= omap_i2c_read_reg(dev
, OMAP_I2C_BUF_REG
);
492 w
|= OMAP_I2C_BUF_RXFIF_CLR
| OMAP_I2C_BUF_TXFIF_CLR
;
493 omap_i2c_write_reg(dev
, OMAP_I2C_BUF_REG
, w
);
495 init_completion(&dev
->cmd_complete
);
498 w
= OMAP_I2C_CON_EN
| OMAP_I2C_CON_MST
| OMAP_I2C_CON_STT
;
500 /* High speed configuration */
501 if (dev
->speed
> 400)
502 w
|= OMAP_I2C_CON_OPMODE_HS
;
504 if (msg
->flags
& I2C_M_TEN
)
505 w
|= OMAP_I2C_CON_XA
;
506 if (!(msg
->flags
& I2C_M_RD
))
507 w
|= OMAP_I2C_CON_TRX
;
509 if (!dev
->b_hw
&& stop
)
510 w
|= OMAP_I2C_CON_STP
;
512 omap_i2c_write_reg(dev
, OMAP_I2C_CON_REG
, w
);
515 * Don't write stt and stp together on some hardware.
517 if (dev
->b_hw
&& stop
) {
518 unsigned long delay
= jiffies
+ OMAP_I2C_TIMEOUT
;
519 u16 con
= omap_i2c_read_reg(dev
, OMAP_I2C_CON_REG
);
520 while (con
& OMAP_I2C_CON_STT
) {
521 con
= omap_i2c_read_reg(dev
, OMAP_I2C_CON_REG
);
523 /* Let the user know if i2c is in a bad state */
524 if (time_after(jiffies
, delay
)) {
525 dev_err(dev
->dev
, "controller timed out "
526 "waiting for start condition to finish\n");
532 w
|= OMAP_I2C_CON_STP
;
533 w
&= ~OMAP_I2C_CON_STT
;
534 omap_i2c_write_reg(dev
, OMAP_I2C_CON_REG
, w
);
538 * REVISIT: We should abort the transfer on signals, but the bus goes
539 * into arbitration and we're currently unable to recover from it.
541 r
= wait_for_completion_timeout(&dev
->cmd_complete
,
547 dev_err(dev
->dev
, "controller timed out\n");
552 if (likely(!dev
->cmd_err
))
555 /* We have an error */
556 if (dev
->cmd_err
& (OMAP_I2C_STAT_AL
| OMAP_I2C_STAT_ROVR
|
557 OMAP_I2C_STAT_XUDF
)) {
562 if (dev
->cmd_err
& OMAP_I2C_STAT_NACK
) {
563 if (msg
->flags
& I2C_M_IGNORE_NAK
)
566 w
= omap_i2c_read_reg(dev
, OMAP_I2C_CON_REG
);
567 w
|= OMAP_I2C_CON_STP
;
568 omap_i2c_write_reg(dev
, OMAP_I2C_CON_REG
, w
);
577 * Prepare controller for a transaction and call omap_i2c_xfer_msg
578 * to do the work during IRQ processing.
581 omap_i2c_xfer(struct i2c_adapter
*adap
, struct i2c_msg msgs
[], int num
)
583 struct omap_i2c_dev
*dev
= i2c_get_adapdata(adap
);
587 omap_i2c_unidle(dev
);
589 r
= omap_i2c_wait_for_bb(dev
);
593 for (i
= 0; i
< num
; i
++) {
594 r
= omap_i2c_xfer_msg(adap
, &msgs
[i
], (i
== (num
- 1)));
607 omap_i2c_func(struct i2c_adapter
*adap
)
609 return I2C_FUNC_I2C
| (I2C_FUNC_SMBUS_EMUL
& ~I2C_FUNC_SMBUS_QUICK
);
613 omap_i2c_complete_cmd(struct omap_i2c_dev
*dev
, u16 err
)
616 complete(&dev
->cmd_complete
);
620 omap_i2c_ack_stat(struct omap_i2c_dev
*dev
, u16 stat
)
622 omap_i2c_write_reg(dev
, OMAP_I2C_STAT_REG
, stat
);
625 /* rev1 devices are apparently only on some 15xx */
626 #ifdef CONFIG_ARCH_OMAP15XX
629 omap_i2c_rev1_isr(int this_irq
, void *dev_id
)
631 struct omap_i2c_dev
*dev
= dev_id
;
637 iv
= omap_i2c_read_reg(dev
, OMAP_I2C_IV_REG
);
639 case 0x00: /* None */
641 case 0x01: /* Arbitration lost */
642 dev_err(dev
->dev
, "Arbitration lost\n");
643 omap_i2c_complete_cmd(dev
, OMAP_I2C_STAT_AL
);
645 case 0x02: /* No acknowledgement */
646 omap_i2c_complete_cmd(dev
, OMAP_I2C_STAT_NACK
);
647 omap_i2c_write_reg(dev
, OMAP_I2C_CON_REG
, OMAP_I2C_CON_STP
);
649 case 0x03: /* Register access ready */
650 omap_i2c_complete_cmd(dev
, 0);
652 case 0x04: /* Receive data ready */
654 w
= omap_i2c_read_reg(dev
, OMAP_I2C_DATA_REG
);
658 *dev
->buf
++ = w
>> 8;
662 dev_err(dev
->dev
, "RRDY IRQ while no data requested\n");
664 case 0x05: /* Transmit data ready */
669 w
|= *dev
->buf
++ << 8;
672 omap_i2c_write_reg(dev
, OMAP_I2C_DATA_REG
, w
);
674 dev_err(dev
->dev
, "XRDY IRQ while no data to send\n");
683 #define omap_i2c_rev1_isr NULL
687 omap_i2c_isr(int this_irq
, void *dev_id
)
689 struct omap_i2c_dev
*dev
= dev_id
;
697 bits
= omap_i2c_read_reg(dev
, OMAP_I2C_IE_REG
);
698 while ((stat
= (omap_i2c_read_reg(dev
, OMAP_I2C_STAT_REG
))) & bits
) {
699 dev_dbg(dev
->dev
, "IRQ (ISR = 0x%04x)\n", stat
);
700 if (count
++ == 100) {
701 dev_warn(dev
->dev
, "Too much work in one IRQ\n");
708 * Ack the stat in one go, but [R/X]DR and [R/X]RDY should be
709 * acked after the data operation is complete.
710 * Ref: TRM SWPU114Q Figure 18-31
712 omap_i2c_write_reg(dev
, OMAP_I2C_STAT_REG
, stat
&
713 ~(OMAP_I2C_STAT_RRDY
| OMAP_I2C_STAT_RDR
|
714 OMAP_I2C_STAT_XRDY
| OMAP_I2C_STAT_XDR
));
716 if (stat
& OMAP_I2C_STAT_NACK
) {
717 err
|= OMAP_I2C_STAT_NACK
;
718 omap_i2c_write_reg(dev
, OMAP_I2C_CON_REG
,
721 if (stat
& OMAP_I2C_STAT_AL
) {
722 dev_err(dev
->dev
, "Arbitration lost\n");
723 err
|= OMAP_I2C_STAT_AL
;
725 if (stat
& (OMAP_I2C_STAT_ARDY
| OMAP_I2C_STAT_NACK
|
727 omap_i2c_ack_stat(dev
, stat
&
728 (OMAP_I2C_STAT_RRDY
| OMAP_I2C_STAT_RDR
|
729 OMAP_I2C_STAT_XRDY
| OMAP_I2C_STAT_XDR
));
730 omap_i2c_complete_cmd(dev
, err
);
733 if (stat
& (OMAP_I2C_STAT_RRDY
| OMAP_I2C_STAT_RDR
)) {
735 if (dev
->fifo_size
) {
736 if (stat
& OMAP_I2C_STAT_RRDY
)
737 num_bytes
= dev
->fifo_size
;
738 else /* read RXSTAT on RDR interrupt */
739 num_bytes
= (omap_i2c_read_reg(dev
,
740 OMAP_I2C_BUFSTAT_REG
)
745 w
= omap_i2c_read_reg(dev
, OMAP_I2C_DATA_REG
);
749 /* Data reg from 2430 is 8 bit wide */
750 if (!cpu_is_omap2430() &&
751 !cpu_is_omap34xx()) {
753 *dev
->buf
++ = w
>> 8;
758 if (stat
& OMAP_I2C_STAT_RRDY
)
760 "RRDY IRQ while no data"
762 if (stat
& OMAP_I2C_STAT_RDR
)
764 "RDR IRQ while no data"
769 omap_i2c_ack_stat(dev
,
770 stat
& (OMAP_I2C_STAT_RRDY
| OMAP_I2C_STAT_RDR
));
773 if (stat
& (OMAP_I2C_STAT_XRDY
| OMAP_I2C_STAT_XDR
)) {
775 if (dev
->fifo_size
) {
776 if (stat
& OMAP_I2C_STAT_XRDY
)
777 num_bytes
= dev
->fifo_size
;
778 else /* read TXSTAT on XDR interrupt */
779 num_bytes
= omap_i2c_read_reg(dev
,
780 OMAP_I2C_BUFSTAT_REG
)
789 /* Data reg from 2430 is 8 bit wide */
790 if (!cpu_is_omap2430() &&
791 !cpu_is_omap34xx()) {
793 w
|= *dev
->buf
++ << 8;
798 if (stat
& OMAP_I2C_STAT_XRDY
)
802 if (stat
& OMAP_I2C_STAT_XDR
)
810 * OMAP3430 Errata 1.153: When an XRDY/XDR
811 * is hit, wait for XUDF before writing data
812 * to DATA_REG. Otherwise some data bytes can
813 * be lost while transferring them from the
814 * memory to the I2C interface.
817 if (dev
->rev
<= OMAP_I2C_REV_ON_3430
) {
818 while (!(stat
& OMAP_I2C_STAT_XUDF
)) {
819 if (stat
& (OMAP_I2C_STAT_NACK
| OMAP_I2C_STAT_AL
)) {
820 omap_i2c_ack_stat(dev
, stat
& (OMAP_I2C_STAT_XRDY
| OMAP_I2C_STAT_XDR
));
821 err
|= OMAP_I2C_STAT_XUDF
;
825 stat
= omap_i2c_read_reg(dev
, OMAP_I2C_STAT_REG
);
829 omap_i2c_write_reg(dev
, OMAP_I2C_DATA_REG
, w
);
831 omap_i2c_ack_stat(dev
,
832 stat
& (OMAP_I2C_STAT_XRDY
| OMAP_I2C_STAT_XDR
));
835 if (stat
& OMAP_I2C_STAT_ROVR
) {
836 dev_err(dev
->dev
, "Receive overrun\n");
837 dev
->cmd_err
|= OMAP_I2C_STAT_ROVR
;
839 if (stat
& OMAP_I2C_STAT_XUDF
) {
840 dev_err(dev
->dev
, "Transmit underflow\n");
841 dev
->cmd_err
|= OMAP_I2C_STAT_XUDF
;
845 return count
? IRQ_HANDLED
: IRQ_NONE
;
848 static const struct i2c_algorithm omap_i2c_algo
= {
849 .master_xfer
= omap_i2c_xfer
,
850 .functionality
= omap_i2c_func
,
854 omap_i2c_probe(struct platform_device
*pdev
)
856 struct omap_i2c_dev
*dev
;
857 struct i2c_adapter
*adap
;
858 struct resource
*mem
, *irq
, *ioarea
;
863 /* NOTE: driver uses the static register mapping */
864 mem
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
866 dev_err(&pdev
->dev
, "no mem resource?\n");
869 irq
= platform_get_resource(pdev
, IORESOURCE_IRQ
, 0);
871 dev_err(&pdev
->dev
, "no irq resource?\n");
875 ioarea
= request_mem_region(mem
->start
, resource_size(mem
),
878 dev_err(&pdev
->dev
, "I2C region already claimed\n");
882 dev
= kzalloc(sizeof(struct omap_i2c_dev
), GFP_KERNEL
);
885 goto err_release_region
;
888 if (pdev
->dev
.platform_data
!= NULL
)
889 speed
= *(u32
*)pdev
->dev
.platform_data
;
891 speed
= 100; /* Defualt speed */
895 dev
->dev
= &pdev
->dev
;
896 dev
->irq
= irq
->start
;
897 dev
->base
= ioremap(mem
->start
, resource_size(mem
));
903 platform_set_drvdata(pdev
, dev
);
905 if ((r
= omap_i2c_get_clocks(dev
)) != 0)
908 omap_i2c_unidle(dev
);
910 dev
->rev
= omap_i2c_read_reg(dev
, OMAP_I2C_REV_REG
) & 0xff;
912 if (cpu_is_omap2430() || cpu_is_omap34xx()) {
915 /* Set up the fifo size - Get total size */
916 s
= (omap_i2c_read_reg(dev
, OMAP_I2C_BUFSTAT_REG
) >> 14) & 0x3;
917 dev
->fifo_size
= 0x8 << s
;
920 * Set up notification threshold as half the total available
921 * size. This is to ensure that we can handle the status on int
922 * call back latencies.
924 dev
->fifo_size
= (dev
->fifo_size
/ 2);
925 dev
->b_hw
= 1; /* Enable hardware fixes */
928 if (cpu_is_omap7xx())
933 /* reset ASAP, clearing any IRQs */
936 isr
= (dev
->rev
< OMAP_I2C_REV_2
) ? omap_i2c_rev1_isr
: omap_i2c_isr
;
937 r
= request_irq(dev
->irq
, isr
, 0, pdev
->name
, dev
);
940 dev_err(dev
->dev
, "failure requesting irq %i\n", dev
->irq
);
941 goto err_unuse_clocks
;
944 dev_info(dev
->dev
, "bus %d rev%d.%d at %d kHz\n",
945 pdev
->id
, dev
->rev
>> 4, dev
->rev
& 0xf, dev
->speed
);
949 adap
= &dev
->adapter
;
950 i2c_set_adapdata(adap
, dev
);
951 adap
->owner
= THIS_MODULE
;
952 adap
->class = I2C_CLASS_HWMON
;
953 strlcpy(adap
->name
, "OMAP I2C adapter", sizeof(adap
->name
));
954 adap
->algo
= &omap_i2c_algo
;
955 adap
->dev
.parent
= &pdev
->dev
;
957 /* i2c device drivers may be active on return from add_adapter() */
959 r
= i2c_add_numbered_adapter(adap
);
961 dev_err(dev
->dev
, "failure adding adapter\n");
968 free_irq(dev
->irq
, dev
);
970 omap_i2c_write_reg(dev
, OMAP_I2C_CON_REG
, 0);
972 omap_i2c_put_clocks(dev
);
976 platform_set_drvdata(pdev
, NULL
);
979 release_mem_region(mem
->start
, resource_size(mem
));
985 omap_i2c_remove(struct platform_device
*pdev
)
987 struct omap_i2c_dev
*dev
= platform_get_drvdata(pdev
);
988 struct resource
*mem
;
990 platform_set_drvdata(pdev
, NULL
);
992 free_irq(dev
->irq
, dev
);
993 i2c_del_adapter(&dev
->adapter
);
994 omap_i2c_write_reg(dev
, OMAP_I2C_CON_REG
, 0);
995 omap_i2c_put_clocks(dev
);
998 mem
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
999 release_mem_region(mem
->start
, resource_size(mem
));
1003 static struct platform_driver omap_i2c_driver
= {
1004 .probe
= omap_i2c_probe
,
1005 .remove
= omap_i2c_remove
,
1008 .owner
= THIS_MODULE
,
1012 /* I2C may be needed to bring up other drivers */
1014 omap_i2c_init_driver(void)
1016 return platform_driver_register(&omap_i2c_driver
);
1018 subsys_initcall(omap_i2c_init_driver
);
1020 static void __exit
omap_i2c_exit_driver(void)
1022 platform_driver_unregister(&omap_i2c_driver
);
1024 module_exit(omap_i2c_exit_driver
);
1026 MODULE_AUTHOR("MontaVista Software, Inc. (and others)");
1027 MODULE_DESCRIPTION("TI OMAP I2C bus adapter");
1028 MODULE_LICENSE("GPL");
1029 MODULE_ALIAS("platform:i2c_omap");