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[mirror_ubuntu-zesty-kernel.git] / drivers / i2c / busses / i2c-omap.c
1 /*
2 * TI OMAP I2C master mode driver
3 *
4 * Copyright (C) 2003 MontaVista Software, Inc.
5 * Copyright (C) 2005 Nokia Corporation
6 * Copyright (C) 2004 - 2007 Texas Instruments.
7 *
8 * Originally written by MontaVista Software, Inc.
9 * Additional contributions by:
10 * Tony Lindgren <tony@atomide.com>
11 * Imre Deak <imre.deak@nokia.com>
12 * Juha Yrjölä <juha.yrjola@solidboot.com>
13 * Syed Khasim <x0khasim@ti.com>
14 * Nishant Menon <nm@ti.com>
15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License as published by
18 * the Free Software Foundation; either version 2 of the License, or
19 * (at your option) any later version.
20 *
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
25 *
26 * You should have received a copy of the GNU General Public License
27 * along with this program; if not, write to the Free Software
28 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
29 */
30
31 #include <linux/module.h>
32 #include <linux/delay.h>
33 #include <linux/i2c.h>
34 #include <linux/err.h>
35 #include <linux/interrupt.h>
36 #include <linux/completion.h>
37 #include <linux/platform_device.h>
38 #include <linux/clk.h>
39 #include <linux/io.h>
40
41 /* I2C controller revisions */
42 #define OMAP_I2C_REV_2 0x20
43
44 /* I2C controller revisions present on specific hardware */
45 #define OMAP_I2C_REV_ON_2430 0x36
46 #define OMAP_I2C_REV_ON_3430 0x3C
47
48 /* timeout waiting for the controller to respond */
49 #define OMAP_I2C_TIMEOUT (msecs_to_jiffies(1000))
50
51 #define OMAP_I2C_REV_REG 0x00
52 #define OMAP_I2C_IE_REG 0x04
53 #define OMAP_I2C_STAT_REG 0x08
54 #define OMAP_I2C_IV_REG 0x0c
55 /* For OMAP3 I2C_IV has changed to I2C_WE (wakeup enable) */
56 #define OMAP_I2C_WE_REG 0x0c
57 #define OMAP_I2C_SYSS_REG 0x10
58 #define OMAP_I2C_BUF_REG 0x14
59 #define OMAP_I2C_CNT_REG 0x18
60 #define OMAP_I2C_DATA_REG 0x1c
61 #define OMAP_I2C_SYSC_REG 0x20
62 #define OMAP_I2C_CON_REG 0x24
63 #define OMAP_I2C_OA_REG 0x28
64 #define OMAP_I2C_SA_REG 0x2c
65 #define OMAP_I2C_PSC_REG 0x30
66 #define OMAP_I2C_SCLL_REG 0x34
67 #define OMAP_I2C_SCLH_REG 0x38
68 #define OMAP_I2C_SYSTEST_REG 0x3c
69 #define OMAP_I2C_BUFSTAT_REG 0x40
70
71 /* I2C Interrupt Enable Register (OMAP_I2C_IE): */
72 #define OMAP_I2C_IE_XDR (1 << 14) /* TX Buffer drain int enable */
73 #define OMAP_I2C_IE_RDR (1 << 13) /* RX Buffer drain int enable */
74 #define OMAP_I2C_IE_XRDY (1 << 4) /* TX data ready int enable */
75 #define OMAP_I2C_IE_RRDY (1 << 3) /* RX data ready int enable */
76 #define OMAP_I2C_IE_ARDY (1 << 2) /* Access ready int enable */
77 #define OMAP_I2C_IE_NACK (1 << 1) /* No ack interrupt enable */
78 #define OMAP_I2C_IE_AL (1 << 0) /* Arbitration lost int ena */
79
80 /* I2C Status Register (OMAP_I2C_STAT): */
81 #define OMAP_I2C_STAT_XDR (1 << 14) /* TX Buffer draining */
82 #define OMAP_I2C_STAT_RDR (1 << 13) /* RX Buffer draining */
83 #define OMAP_I2C_STAT_BB (1 << 12) /* Bus busy */
84 #define OMAP_I2C_STAT_ROVR (1 << 11) /* Receive overrun */
85 #define OMAP_I2C_STAT_XUDF (1 << 10) /* Transmit underflow */
86 #define OMAP_I2C_STAT_AAS (1 << 9) /* Address as slave */
87 #define OMAP_I2C_STAT_AD0 (1 << 8) /* Address zero */
88 #define OMAP_I2C_STAT_XRDY (1 << 4) /* Transmit data ready */
89 #define OMAP_I2C_STAT_RRDY (1 << 3) /* Receive data ready */
90 #define OMAP_I2C_STAT_ARDY (1 << 2) /* Register access ready */
91 #define OMAP_I2C_STAT_NACK (1 << 1) /* No ack interrupt enable */
92 #define OMAP_I2C_STAT_AL (1 << 0) /* Arbitration lost int ena */
93
94 /* I2C WE wakeup enable register */
95 #define OMAP_I2C_WE_XDR_WE (1 << 14) /* TX drain wakup */
96 #define OMAP_I2C_WE_RDR_WE (1 << 13) /* RX drain wakeup */
97 #define OMAP_I2C_WE_AAS_WE (1 << 9) /* Address as slave wakeup*/
98 #define OMAP_I2C_WE_BF_WE (1 << 8) /* Bus free wakeup */
99 #define OMAP_I2C_WE_STC_WE (1 << 6) /* Start condition wakeup */
100 #define OMAP_I2C_WE_GC_WE (1 << 5) /* General call wakeup */
101 #define OMAP_I2C_WE_DRDY_WE (1 << 3) /* TX/RX data ready wakeup */
102 #define OMAP_I2C_WE_ARDY_WE (1 << 2) /* Reg access ready wakeup */
103 #define OMAP_I2C_WE_NACK_WE (1 << 1) /* No acknowledgment wakeup */
104 #define OMAP_I2C_WE_AL_WE (1 << 0) /* Arbitration lost wakeup */
105
106 #define OMAP_I2C_WE_ALL (OMAP_I2C_WE_XDR_WE | OMAP_I2C_WE_RDR_WE | \
107 OMAP_I2C_WE_AAS_WE | OMAP_I2C_WE_BF_WE | \
108 OMAP_I2C_WE_STC_WE | OMAP_I2C_WE_GC_WE | \
109 OMAP_I2C_WE_DRDY_WE | OMAP_I2C_WE_ARDY_WE | \
110 OMAP_I2C_WE_NACK_WE | OMAP_I2C_WE_AL_WE)
111
112 /* I2C Buffer Configuration Register (OMAP_I2C_BUF): */
113 #define OMAP_I2C_BUF_RDMA_EN (1 << 15) /* RX DMA channel enable */
114 #define OMAP_I2C_BUF_RXFIF_CLR (1 << 14) /* RX FIFO Clear */
115 #define OMAP_I2C_BUF_XDMA_EN (1 << 7) /* TX DMA channel enable */
116 #define OMAP_I2C_BUF_TXFIF_CLR (1 << 6) /* TX FIFO Clear */
117
118 /* I2C Configuration Register (OMAP_I2C_CON): */
119 #define OMAP_I2C_CON_EN (1 << 15) /* I2C module enable */
120 #define OMAP_I2C_CON_BE (1 << 14) /* Big endian mode */
121 #define OMAP_I2C_CON_OPMODE_HS (1 << 12) /* High Speed support */
122 #define OMAP_I2C_CON_STB (1 << 11) /* Start byte mode (master) */
123 #define OMAP_I2C_CON_MST (1 << 10) /* Master/slave mode */
124 #define OMAP_I2C_CON_TRX (1 << 9) /* TX/RX mode (master only) */
125 #define OMAP_I2C_CON_XA (1 << 8) /* Expand address */
126 #define OMAP_I2C_CON_RM (1 << 2) /* Repeat mode (master only) */
127 #define OMAP_I2C_CON_STP (1 << 1) /* Stop cond (master only) */
128 #define OMAP_I2C_CON_STT (1 << 0) /* Start condition (master) */
129
130 /* I2C SCL time value when Master */
131 #define OMAP_I2C_SCLL_HSSCLL 8
132 #define OMAP_I2C_SCLH_HSSCLH 8
133
134 /* I2C System Test Register (OMAP_I2C_SYSTEST): */
135 #ifdef DEBUG
136 #define OMAP_I2C_SYSTEST_ST_EN (1 << 15) /* System test enable */
137 #define OMAP_I2C_SYSTEST_FREE (1 << 14) /* Free running mode */
138 #define OMAP_I2C_SYSTEST_TMODE_MASK (3 << 12) /* Test mode select */
139 #define OMAP_I2C_SYSTEST_TMODE_SHIFT (12) /* Test mode select */
140 #define OMAP_I2C_SYSTEST_SCL_I (1 << 3) /* SCL line sense in */
141 #define OMAP_I2C_SYSTEST_SCL_O (1 << 2) /* SCL line drive out */
142 #define OMAP_I2C_SYSTEST_SDA_I (1 << 1) /* SDA line sense in */
143 #define OMAP_I2C_SYSTEST_SDA_O (1 << 0) /* SDA line drive out */
144 #endif
145
146 /* OCP_SYSSTATUS bit definitions */
147 #define SYSS_RESETDONE_MASK (1 << 0)
148
149 /* OCP_SYSCONFIG bit definitions */
150 #define SYSC_CLOCKACTIVITY_MASK (0x3 << 8)
151 #define SYSC_SIDLEMODE_MASK (0x3 << 3)
152 #define SYSC_ENAWAKEUP_MASK (1 << 2)
153 #define SYSC_SOFTRESET_MASK (1 << 1)
154 #define SYSC_AUTOIDLE_MASK (1 << 0)
155
156 #define SYSC_IDLEMODE_SMART 0x2
157 #define SYSC_CLOCKACTIVITY_FCLK 0x2
158
159
160 struct omap_i2c_dev {
161 struct device *dev;
162 void __iomem *base; /* virtual */
163 int irq;
164 struct clk *iclk; /* Interface clock */
165 struct clk *fclk; /* Functional clock */
166 struct completion cmd_complete;
167 struct resource *ioarea;
168 u32 speed; /* Speed of bus in Khz */
169 u16 cmd_err;
170 u8 *buf;
171 size_t buf_len;
172 struct i2c_adapter adapter;
173 u8 fifo_size; /* use as flag and value
174 * fifo_size==0 implies no fifo
175 * if set, should be trsh+1
176 */
177 u8 rev;
178 unsigned b_hw:1; /* bad h/w fixes */
179 unsigned idle:1;
180 u16 iestate; /* Saved interrupt register */
181 u16 pscstate;
182 u16 scllstate;
183 u16 sclhstate;
184 u16 bufstate;
185 u16 syscstate;
186 u16 westate;
187 };
188
189 static inline void omap_i2c_write_reg(struct omap_i2c_dev *i2c_dev,
190 int reg, u16 val)
191 {
192 __raw_writew(val, i2c_dev->base + reg);
193 }
194
195 static inline u16 omap_i2c_read_reg(struct omap_i2c_dev *i2c_dev, int reg)
196 {
197 return __raw_readw(i2c_dev->base + reg);
198 }
199
200 static int __init omap_i2c_get_clocks(struct omap_i2c_dev *dev)
201 {
202 int ret;
203
204 dev->iclk = clk_get(dev->dev, "ick");
205 if (IS_ERR(dev->iclk)) {
206 ret = PTR_ERR(dev->iclk);
207 dev->iclk = NULL;
208 return ret;
209 }
210
211 dev->fclk = clk_get(dev->dev, "fck");
212 if (IS_ERR(dev->fclk)) {
213 ret = PTR_ERR(dev->fclk);
214 if (dev->iclk != NULL) {
215 clk_put(dev->iclk);
216 dev->iclk = NULL;
217 }
218 dev->fclk = NULL;
219 return ret;
220 }
221
222 return 0;
223 }
224
225 static void omap_i2c_put_clocks(struct omap_i2c_dev *dev)
226 {
227 clk_put(dev->fclk);
228 dev->fclk = NULL;
229 clk_put(dev->iclk);
230 dev->iclk = NULL;
231 }
232
233 static void omap_i2c_unidle(struct omap_i2c_dev *dev)
234 {
235 WARN_ON(!dev->idle);
236
237 clk_enable(dev->iclk);
238 clk_enable(dev->fclk);
239 if (cpu_is_omap34xx()) {
240 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
241 omap_i2c_write_reg(dev, OMAP_I2C_PSC_REG, dev->pscstate);
242 omap_i2c_write_reg(dev, OMAP_I2C_SCLL_REG, dev->scllstate);
243 omap_i2c_write_reg(dev, OMAP_I2C_SCLH_REG, dev->sclhstate);
244 omap_i2c_write_reg(dev, OMAP_I2C_BUF_REG, dev->bufstate);
245 omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG, dev->syscstate);
246 omap_i2c_write_reg(dev, OMAP_I2C_WE_REG, dev->westate);
247 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
248 }
249 dev->idle = 0;
250
251 /*
252 * Don't write to this register if the IE state is 0 as it can
253 * cause deadlock.
254 */
255 if (dev->iestate)
256 omap_i2c_write_reg(dev, OMAP_I2C_IE_REG, dev->iestate);
257 }
258
259 static void omap_i2c_idle(struct omap_i2c_dev *dev)
260 {
261 u16 iv;
262
263 WARN_ON(dev->idle);
264
265 dev->iestate = omap_i2c_read_reg(dev, OMAP_I2C_IE_REG);
266 omap_i2c_write_reg(dev, OMAP_I2C_IE_REG, 0);
267 if (dev->rev < OMAP_I2C_REV_2) {
268 iv = omap_i2c_read_reg(dev, OMAP_I2C_IV_REG); /* Read clears */
269 } else {
270 omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, dev->iestate);
271
272 /* Flush posted write before the dev->idle store occurs */
273 omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG);
274 }
275 dev->idle = 1;
276 clk_disable(dev->fclk);
277 clk_disable(dev->iclk);
278 }
279
280 static int omap_i2c_init(struct omap_i2c_dev *dev)
281 {
282 u16 psc = 0, scll = 0, sclh = 0, buf = 0;
283 u16 fsscll = 0, fssclh = 0, hsscll = 0, hssclh = 0;
284 unsigned long fclk_rate = 12000000;
285 unsigned long timeout;
286 unsigned long internal_clk = 0;
287
288 if (dev->rev >= OMAP_I2C_REV_2) {
289 /* Disable I2C controller before soft reset */
290 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG,
291 omap_i2c_read_reg(dev, OMAP_I2C_CON_REG) &
292 ~(OMAP_I2C_CON_EN));
293
294 omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG, SYSC_SOFTRESET_MASK);
295 /* For some reason we need to set the EN bit before the
296 * reset done bit gets set. */
297 timeout = jiffies + OMAP_I2C_TIMEOUT;
298 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
299 while (!(omap_i2c_read_reg(dev, OMAP_I2C_SYSS_REG) &
300 SYSS_RESETDONE_MASK)) {
301 if (time_after(jiffies, timeout)) {
302 dev_warn(dev->dev, "timeout waiting "
303 "for controller reset\n");
304 return -ETIMEDOUT;
305 }
306 msleep(1);
307 }
308
309 /* SYSC register is cleared by the reset; rewrite it */
310 if (dev->rev == OMAP_I2C_REV_ON_2430) {
311
312 omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG,
313 SYSC_AUTOIDLE_MASK);
314
315 } else if (dev->rev >= OMAP_I2C_REV_ON_3430) {
316 dev->syscstate = SYSC_AUTOIDLE_MASK;
317 dev->syscstate |= SYSC_ENAWAKEUP_MASK;
318 dev->syscstate |= (SYSC_IDLEMODE_SMART <<
319 __ffs(SYSC_SIDLEMODE_MASK));
320 dev->syscstate |= (SYSC_CLOCKACTIVITY_FCLK <<
321 __ffs(SYSC_CLOCKACTIVITY_MASK));
322
323 omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG,
324 dev->syscstate);
325 /*
326 * Enabling all wakup sources to stop I2C freezing on
327 * WFI instruction.
328 * REVISIT: Some wkup sources might not be needed.
329 */
330 dev->westate = OMAP_I2C_WE_ALL;
331 omap_i2c_write_reg(dev, OMAP_I2C_WE_REG, dev->westate);
332 }
333 }
334 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
335
336 if (cpu_class_is_omap1()) {
337 /*
338 * The I2C functional clock is the armxor_ck, so there's
339 * no need to get "armxor_ck" separately. Now, if OMAP2420
340 * always returns 12MHz for the functional clock, we can
341 * do this bit unconditionally.
342 */
343 fclk_rate = clk_get_rate(dev->fclk);
344
345 /* TRM for 5912 says the I2C clock must be prescaled to be
346 * between 7 - 12 MHz. The XOR input clock is typically
347 * 12, 13 or 19.2 MHz. So we should have code that produces:
348 *
349 * XOR MHz Divider Prescaler
350 * 12 1 0
351 * 13 2 1
352 * 19.2 2 1
353 */
354 if (fclk_rate > 12000000)
355 psc = fclk_rate / 12000000;
356 }
357
358 if (cpu_is_omap2430() || cpu_is_omap34xx()) {
359
360 /*
361 * HSI2C controller internal clk rate should be 19.2 Mhz for
362 * HS and for all modes on 2430. On 34xx we can use lower rate
363 * to get longer filter period for better noise suppression.
364 * The filter is iclk (fclk for HS) period.
365 */
366 if (dev->speed > 400 || cpu_is_omap2430())
367 internal_clk = 19200;
368 else if (dev->speed > 100)
369 internal_clk = 9600;
370 else
371 internal_clk = 4000;
372 fclk_rate = clk_get_rate(dev->fclk) / 1000;
373
374 /* Compute prescaler divisor */
375 psc = fclk_rate / internal_clk;
376 psc = psc - 1;
377
378 /* If configured for High Speed */
379 if (dev->speed > 400) {
380 unsigned long scl;
381
382 /* For first phase of HS mode */
383 scl = internal_clk / 400;
384 fsscll = scl - (scl / 3) - 7;
385 fssclh = (scl / 3) - 5;
386
387 /* For second phase of HS mode */
388 scl = fclk_rate / dev->speed;
389 hsscll = scl - (scl / 3) - 7;
390 hssclh = (scl / 3) - 5;
391 } else if (dev->speed > 100) {
392 unsigned long scl;
393
394 /* Fast mode */
395 scl = internal_clk / dev->speed;
396 fsscll = scl - (scl / 3) - 7;
397 fssclh = (scl / 3) - 5;
398 } else {
399 /* Standard mode */
400 fsscll = internal_clk / (dev->speed * 2) - 7;
401 fssclh = internal_clk / (dev->speed * 2) - 5;
402 }
403 scll = (hsscll << OMAP_I2C_SCLL_HSSCLL) | fsscll;
404 sclh = (hssclh << OMAP_I2C_SCLH_HSSCLH) | fssclh;
405 } else {
406 /* Program desired operating rate */
407 fclk_rate /= (psc + 1) * 1000;
408 if (psc > 2)
409 psc = 2;
410 scll = fclk_rate / (dev->speed * 2) - 7 + psc;
411 sclh = fclk_rate / (dev->speed * 2) - 7 + psc;
412 }
413
414 /* Setup clock prescaler to obtain approx 12MHz I2C module clock: */
415 omap_i2c_write_reg(dev, OMAP_I2C_PSC_REG, psc);
416
417 /* SCL low and high time values */
418 omap_i2c_write_reg(dev, OMAP_I2C_SCLL_REG, scll);
419 omap_i2c_write_reg(dev, OMAP_I2C_SCLH_REG, sclh);
420
421 if (dev->fifo_size) {
422 /* Note: setup required fifo size - 1. RTRSH and XTRSH */
423 buf = (dev->fifo_size - 1) << 8 | OMAP_I2C_BUF_RXFIF_CLR |
424 (dev->fifo_size - 1) | OMAP_I2C_BUF_TXFIF_CLR;
425 omap_i2c_write_reg(dev, OMAP_I2C_BUF_REG, buf);
426 }
427
428 /* Take the I2C module out of reset: */
429 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
430
431 /* Enable interrupts */
432 dev->iestate = (OMAP_I2C_IE_XRDY | OMAP_I2C_IE_RRDY |
433 OMAP_I2C_IE_ARDY | OMAP_I2C_IE_NACK |
434 OMAP_I2C_IE_AL) | ((dev->fifo_size) ?
435 (OMAP_I2C_IE_RDR | OMAP_I2C_IE_XDR) : 0);
436 omap_i2c_write_reg(dev, OMAP_I2C_IE_REG, dev->iestate);
437 if (cpu_is_omap34xx()) {
438 dev->pscstate = psc;
439 dev->scllstate = scll;
440 dev->sclhstate = sclh;
441 dev->bufstate = buf;
442 }
443 return 0;
444 }
445
446 /*
447 * Waiting on Bus Busy
448 */
449 static int omap_i2c_wait_for_bb(struct omap_i2c_dev *dev)
450 {
451 unsigned long timeout;
452
453 timeout = jiffies + OMAP_I2C_TIMEOUT;
454 while (omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG) & OMAP_I2C_STAT_BB) {
455 if (time_after(jiffies, timeout)) {
456 dev_warn(dev->dev, "timeout waiting for bus ready\n");
457 return -ETIMEDOUT;
458 }
459 msleep(1);
460 }
461
462 return 0;
463 }
464
465 /*
466 * Low level master read/write transaction.
467 */
468 static int omap_i2c_xfer_msg(struct i2c_adapter *adap,
469 struct i2c_msg *msg, int stop)
470 {
471 struct omap_i2c_dev *dev = i2c_get_adapdata(adap);
472 int r;
473 u16 w;
474
475 dev_dbg(dev->dev, "addr: 0x%04x, len: %d, flags: 0x%x, stop: %d\n",
476 msg->addr, msg->len, msg->flags, stop);
477
478 if (msg->len == 0)
479 return -EINVAL;
480
481 omap_i2c_write_reg(dev, OMAP_I2C_SA_REG, msg->addr);
482
483 /* REVISIT: Could the STB bit of I2C_CON be used with probing? */
484 dev->buf = msg->buf;
485 dev->buf_len = msg->len;
486
487 omap_i2c_write_reg(dev, OMAP_I2C_CNT_REG, dev->buf_len);
488
489 /* Clear the FIFO Buffers */
490 w = omap_i2c_read_reg(dev, OMAP_I2C_BUF_REG);
491 w |= OMAP_I2C_BUF_RXFIF_CLR | OMAP_I2C_BUF_TXFIF_CLR;
492 omap_i2c_write_reg(dev, OMAP_I2C_BUF_REG, w);
493
494 init_completion(&dev->cmd_complete);
495 dev->cmd_err = 0;
496
497 w = OMAP_I2C_CON_EN | OMAP_I2C_CON_MST | OMAP_I2C_CON_STT;
498
499 /* High speed configuration */
500 if (dev->speed > 400)
501 w |= OMAP_I2C_CON_OPMODE_HS;
502
503 if (msg->flags & I2C_M_TEN)
504 w |= OMAP_I2C_CON_XA;
505 if (!(msg->flags & I2C_M_RD))
506 w |= OMAP_I2C_CON_TRX;
507
508 if (!dev->b_hw && stop)
509 w |= OMAP_I2C_CON_STP;
510
511 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w);
512
513 /*
514 * Don't write stt and stp together on some hardware.
515 */
516 if (dev->b_hw && stop) {
517 unsigned long delay = jiffies + OMAP_I2C_TIMEOUT;
518 u16 con = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG);
519 while (con & OMAP_I2C_CON_STT) {
520 con = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG);
521
522 /* Let the user know if i2c is in a bad state */
523 if (time_after(jiffies, delay)) {
524 dev_err(dev->dev, "controller timed out "
525 "waiting for start condition to finish\n");
526 return -ETIMEDOUT;
527 }
528 cpu_relax();
529 }
530
531 w |= OMAP_I2C_CON_STP;
532 w &= ~OMAP_I2C_CON_STT;
533 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w);
534 }
535
536 /*
537 * REVISIT: We should abort the transfer on signals, but the bus goes
538 * into arbitration and we're currently unable to recover from it.
539 */
540 r = wait_for_completion_timeout(&dev->cmd_complete,
541 OMAP_I2C_TIMEOUT);
542 dev->buf_len = 0;
543 if (r < 0)
544 return r;
545 if (r == 0) {
546 dev_err(dev->dev, "controller timed out\n");
547 omap_i2c_init(dev);
548 return -ETIMEDOUT;
549 }
550
551 if (likely(!dev->cmd_err))
552 return 0;
553
554 /* We have an error */
555 if (dev->cmd_err & (OMAP_I2C_STAT_AL | OMAP_I2C_STAT_ROVR |
556 OMAP_I2C_STAT_XUDF)) {
557 omap_i2c_init(dev);
558 return -EIO;
559 }
560
561 if (dev->cmd_err & OMAP_I2C_STAT_NACK) {
562 if (msg->flags & I2C_M_IGNORE_NAK)
563 return 0;
564 if (stop) {
565 w = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG);
566 w |= OMAP_I2C_CON_STP;
567 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w);
568 }
569 return -EREMOTEIO;
570 }
571 return -EIO;
572 }
573
574
575 /*
576 * Prepare controller for a transaction and call omap_i2c_xfer_msg
577 * to do the work during IRQ processing.
578 */
579 static int
580 omap_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
581 {
582 struct omap_i2c_dev *dev = i2c_get_adapdata(adap);
583 int i;
584 int r;
585
586 omap_i2c_unidle(dev);
587
588 r = omap_i2c_wait_for_bb(dev);
589 if (r < 0)
590 goto out;
591
592 for (i = 0; i < num; i++) {
593 r = omap_i2c_xfer_msg(adap, &msgs[i], (i == (num - 1)));
594 if (r != 0)
595 break;
596 }
597
598 if (r == 0)
599 r = num;
600 out:
601 omap_i2c_idle(dev);
602 return r;
603 }
604
605 static u32
606 omap_i2c_func(struct i2c_adapter *adap)
607 {
608 return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK);
609 }
610
611 static inline void
612 omap_i2c_complete_cmd(struct omap_i2c_dev *dev, u16 err)
613 {
614 dev->cmd_err |= err;
615 complete(&dev->cmd_complete);
616 }
617
618 static inline void
619 omap_i2c_ack_stat(struct omap_i2c_dev *dev, u16 stat)
620 {
621 omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, stat);
622 }
623
624 /* rev1 devices are apparently only on some 15xx */
625 #ifdef CONFIG_ARCH_OMAP15XX
626
627 static irqreturn_t
628 omap_i2c_rev1_isr(int this_irq, void *dev_id)
629 {
630 struct omap_i2c_dev *dev = dev_id;
631 u16 iv, w;
632
633 if (dev->idle)
634 return IRQ_NONE;
635
636 iv = omap_i2c_read_reg(dev, OMAP_I2C_IV_REG);
637 switch (iv) {
638 case 0x00: /* None */
639 break;
640 case 0x01: /* Arbitration lost */
641 dev_err(dev->dev, "Arbitration lost\n");
642 omap_i2c_complete_cmd(dev, OMAP_I2C_STAT_AL);
643 break;
644 case 0x02: /* No acknowledgement */
645 omap_i2c_complete_cmd(dev, OMAP_I2C_STAT_NACK);
646 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_STP);
647 break;
648 case 0x03: /* Register access ready */
649 omap_i2c_complete_cmd(dev, 0);
650 break;
651 case 0x04: /* Receive data ready */
652 if (dev->buf_len) {
653 w = omap_i2c_read_reg(dev, OMAP_I2C_DATA_REG);
654 *dev->buf++ = w;
655 dev->buf_len--;
656 if (dev->buf_len) {
657 *dev->buf++ = w >> 8;
658 dev->buf_len--;
659 }
660 } else
661 dev_err(dev->dev, "RRDY IRQ while no data requested\n");
662 break;
663 case 0x05: /* Transmit data ready */
664 if (dev->buf_len) {
665 w = *dev->buf++;
666 dev->buf_len--;
667 if (dev->buf_len) {
668 w |= *dev->buf++ << 8;
669 dev->buf_len--;
670 }
671 omap_i2c_write_reg(dev, OMAP_I2C_DATA_REG, w);
672 } else
673 dev_err(dev->dev, "XRDY IRQ while no data to send\n");
674 break;
675 default:
676 return IRQ_NONE;
677 }
678
679 return IRQ_HANDLED;
680 }
681 #else
682 #define omap_i2c_rev1_isr NULL
683 #endif
684
685 static irqreturn_t
686 omap_i2c_isr(int this_irq, void *dev_id)
687 {
688 struct omap_i2c_dev *dev = dev_id;
689 u16 bits;
690 u16 stat, w;
691 int err, count = 0;
692
693 if (dev->idle)
694 return IRQ_NONE;
695
696 bits = omap_i2c_read_reg(dev, OMAP_I2C_IE_REG);
697 while ((stat = (omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG))) & bits) {
698 dev_dbg(dev->dev, "IRQ (ISR = 0x%04x)\n", stat);
699 if (count++ == 100) {
700 dev_warn(dev->dev, "Too much work in one IRQ\n");
701 break;
702 }
703
704 err = 0;
705 complete:
706 /*
707 * Ack the stat in one go, but [R/X]DR and [R/X]RDY should be
708 * acked after the data operation is complete.
709 * Ref: TRM SWPU114Q Figure 18-31
710 */
711 omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, stat &
712 ~(OMAP_I2C_STAT_RRDY | OMAP_I2C_STAT_RDR |
713 OMAP_I2C_STAT_XRDY | OMAP_I2C_STAT_XDR));
714
715 if (stat & OMAP_I2C_STAT_NACK) {
716 err |= OMAP_I2C_STAT_NACK;
717 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG,
718 OMAP_I2C_CON_STP);
719 }
720 if (stat & OMAP_I2C_STAT_AL) {
721 dev_err(dev->dev, "Arbitration lost\n");
722 err |= OMAP_I2C_STAT_AL;
723 }
724 if (stat & (OMAP_I2C_STAT_ARDY | OMAP_I2C_STAT_NACK |
725 OMAP_I2C_STAT_AL)) {
726 omap_i2c_ack_stat(dev, stat &
727 (OMAP_I2C_STAT_RRDY | OMAP_I2C_STAT_RDR |
728 OMAP_I2C_STAT_XRDY | OMAP_I2C_STAT_XDR));
729 omap_i2c_complete_cmd(dev, err);
730 return IRQ_HANDLED;
731 }
732 if (stat & (OMAP_I2C_STAT_RRDY | OMAP_I2C_STAT_RDR)) {
733 u8 num_bytes = 1;
734 if (dev->fifo_size) {
735 if (stat & OMAP_I2C_STAT_RRDY)
736 num_bytes = dev->fifo_size;
737 else /* read RXSTAT on RDR interrupt */
738 num_bytes = (omap_i2c_read_reg(dev,
739 OMAP_I2C_BUFSTAT_REG)
740 >> 8) & 0x3F;
741 }
742 while (num_bytes) {
743 num_bytes--;
744 w = omap_i2c_read_reg(dev, OMAP_I2C_DATA_REG);
745 if (dev->buf_len) {
746 *dev->buf++ = w;
747 dev->buf_len--;
748 /* Data reg from 2430 is 8 bit wide */
749 if (!cpu_is_omap2430() &&
750 !cpu_is_omap34xx()) {
751 if (dev->buf_len) {
752 *dev->buf++ = w >> 8;
753 dev->buf_len--;
754 }
755 }
756 } else {
757 if (stat & OMAP_I2C_STAT_RRDY)
758 dev_err(dev->dev,
759 "RRDY IRQ while no data"
760 " requested\n");
761 if (stat & OMAP_I2C_STAT_RDR)
762 dev_err(dev->dev,
763 "RDR IRQ while no data"
764 " requested\n");
765 break;
766 }
767 }
768 omap_i2c_ack_stat(dev,
769 stat & (OMAP_I2C_STAT_RRDY | OMAP_I2C_STAT_RDR));
770 continue;
771 }
772 if (stat & (OMAP_I2C_STAT_XRDY | OMAP_I2C_STAT_XDR)) {
773 u8 num_bytes = 1;
774 if (dev->fifo_size) {
775 if (stat & OMAP_I2C_STAT_XRDY)
776 num_bytes = dev->fifo_size;
777 else /* read TXSTAT on XDR interrupt */
778 num_bytes = omap_i2c_read_reg(dev,
779 OMAP_I2C_BUFSTAT_REG)
780 & 0x3F;
781 }
782 while (num_bytes) {
783 num_bytes--;
784 w = 0;
785 if (dev->buf_len) {
786 w = *dev->buf++;
787 dev->buf_len--;
788 /* Data reg from 2430 is 8 bit wide */
789 if (!cpu_is_omap2430() &&
790 !cpu_is_omap34xx()) {
791 if (dev->buf_len) {
792 w |= *dev->buf++ << 8;
793 dev->buf_len--;
794 }
795 }
796 } else {
797 if (stat & OMAP_I2C_STAT_XRDY)
798 dev_err(dev->dev,
799 "XRDY IRQ while no "
800 "data to send\n");
801 if (stat & OMAP_I2C_STAT_XDR)
802 dev_err(dev->dev,
803 "XDR IRQ while no "
804 "data to send\n");
805 break;
806 }
807
808 /*
809 * OMAP3430 Errata 1.153: When an XRDY/XDR
810 * is hit, wait for XUDF before writing data
811 * to DATA_REG. Otherwise some data bytes can
812 * be lost while transferring them from the
813 * memory to the I2C interface.
814 */
815
816 if (dev->rev <= OMAP_I2C_REV_ON_3430) {
817 while (!(stat & OMAP_I2C_STAT_XUDF)) {
818 if (stat & (OMAP_I2C_STAT_NACK | OMAP_I2C_STAT_AL)) {
819 omap_i2c_ack_stat(dev, stat & (OMAP_I2C_STAT_XRDY | OMAP_I2C_STAT_XDR));
820 err |= OMAP_I2C_STAT_XUDF;
821 goto complete;
822 }
823 cpu_relax();
824 stat = omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG);
825 }
826 }
827
828 omap_i2c_write_reg(dev, OMAP_I2C_DATA_REG, w);
829 }
830 omap_i2c_ack_stat(dev,
831 stat & (OMAP_I2C_STAT_XRDY | OMAP_I2C_STAT_XDR));
832 continue;
833 }
834 if (stat & OMAP_I2C_STAT_ROVR) {
835 dev_err(dev->dev, "Receive overrun\n");
836 dev->cmd_err |= OMAP_I2C_STAT_ROVR;
837 }
838 if (stat & OMAP_I2C_STAT_XUDF) {
839 dev_err(dev->dev, "Transmit underflow\n");
840 dev->cmd_err |= OMAP_I2C_STAT_XUDF;
841 }
842 }
843
844 return count ? IRQ_HANDLED : IRQ_NONE;
845 }
846
847 static const struct i2c_algorithm omap_i2c_algo = {
848 .master_xfer = omap_i2c_xfer,
849 .functionality = omap_i2c_func,
850 };
851
852 static int __init
853 omap_i2c_probe(struct platform_device *pdev)
854 {
855 struct omap_i2c_dev *dev;
856 struct i2c_adapter *adap;
857 struct resource *mem, *irq, *ioarea;
858 irq_handler_t isr;
859 int r;
860 u32 speed = 0;
861
862 /* NOTE: driver uses the static register mapping */
863 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
864 if (!mem) {
865 dev_err(&pdev->dev, "no mem resource?\n");
866 return -ENODEV;
867 }
868 irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
869 if (!irq) {
870 dev_err(&pdev->dev, "no irq resource?\n");
871 return -ENODEV;
872 }
873
874 ioarea = request_mem_region(mem->start, resource_size(mem),
875 pdev->name);
876 if (!ioarea) {
877 dev_err(&pdev->dev, "I2C region already claimed\n");
878 return -EBUSY;
879 }
880
881 dev = kzalloc(sizeof(struct omap_i2c_dev), GFP_KERNEL);
882 if (!dev) {
883 r = -ENOMEM;
884 goto err_release_region;
885 }
886
887 if (pdev->dev.platform_data != NULL)
888 speed = *(u32 *)pdev->dev.platform_data;
889 else
890 speed = 100; /* Defualt speed */
891
892 dev->speed = speed;
893 dev->idle = 1;
894 dev->dev = &pdev->dev;
895 dev->irq = irq->start;
896 dev->base = ioremap(mem->start, resource_size(mem));
897 if (!dev->base) {
898 r = -ENOMEM;
899 goto err_free_mem;
900 }
901
902 platform_set_drvdata(pdev, dev);
903
904 if ((r = omap_i2c_get_clocks(dev)) != 0)
905 goto err_iounmap;
906
907 omap_i2c_unidle(dev);
908
909 dev->rev = omap_i2c_read_reg(dev, OMAP_I2C_REV_REG) & 0xff;
910
911 if (cpu_is_omap2430() || cpu_is_omap34xx()) {
912 u16 s;
913
914 /* Set up the fifo size - Get total size */
915 s = (omap_i2c_read_reg(dev, OMAP_I2C_BUFSTAT_REG) >> 14) & 0x3;
916 dev->fifo_size = 0x8 << s;
917
918 /*
919 * Set up notification threshold as half the total available
920 * size. This is to ensure that we can handle the status on int
921 * call back latencies.
922 */
923 dev->fifo_size = (dev->fifo_size / 2);
924 dev->b_hw = 1; /* Enable hardware fixes */
925 }
926
927 /* reset ASAP, clearing any IRQs */
928 omap_i2c_init(dev);
929
930 isr = (dev->rev < OMAP_I2C_REV_2) ? omap_i2c_rev1_isr : omap_i2c_isr;
931 r = request_irq(dev->irq, isr, 0, pdev->name, dev);
932
933 if (r) {
934 dev_err(dev->dev, "failure requesting irq %i\n", dev->irq);
935 goto err_unuse_clocks;
936 }
937
938 dev_info(dev->dev, "bus %d rev%d.%d at %d kHz\n",
939 pdev->id, dev->rev >> 4, dev->rev & 0xf, dev->speed);
940
941 omap_i2c_idle(dev);
942
943 adap = &dev->adapter;
944 i2c_set_adapdata(adap, dev);
945 adap->owner = THIS_MODULE;
946 adap->class = I2C_CLASS_HWMON;
947 strlcpy(adap->name, "OMAP I2C adapter", sizeof(adap->name));
948 adap->algo = &omap_i2c_algo;
949 adap->dev.parent = &pdev->dev;
950
951 /* i2c device drivers may be active on return from add_adapter() */
952 adap->nr = pdev->id;
953 r = i2c_add_numbered_adapter(adap);
954 if (r) {
955 dev_err(dev->dev, "failure adding adapter\n");
956 goto err_free_irq;
957 }
958
959 return 0;
960
961 err_free_irq:
962 free_irq(dev->irq, dev);
963 err_unuse_clocks:
964 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
965 omap_i2c_idle(dev);
966 omap_i2c_put_clocks(dev);
967 err_iounmap:
968 iounmap(dev->base);
969 err_free_mem:
970 platform_set_drvdata(pdev, NULL);
971 kfree(dev);
972 err_release_region:
973 release_mem_region(mem->start, resource_size(mem));
974
975 return r;
976 }
977
978 static int
979 omap_i2c_remove(struct platform_device *pdev)
980 {
981 struct omap_i2c_dev *dev = platform_get_drvdata(pdev);
982 struct resource *mem;
983
984 platform_set_drvdata(pdev, NULL);
985
986 free_irq(dev->irq, dev);
987 i2c_del_adapter(&dev->adapter);
988 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
989 omap_i2c_put_clocks(dev);
990 iounmap(dev->base);
991 kfree(dev);
992 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
993 release_mem_region(mem->start, resource_size(mem));
994 return 0;
995 }
996
997 static struct platform_driver omap_i2c_driver = {
998 .probe = omap_i2c_probe,
999 .remove = omap_i2c_remove,
1000 .driver = {
1001 .name = "i2c_omap",
1002 .owner = THIS_MODULE,
1003 },
1004 };
1005
1006 /* I2C may be needed to bring up other drivers */
1007 static int __init
1008 omap_i2c_init_driver(void)
1009 {
1010 return platform_driver_register(&omap_i2c_driver);
1011 }
1012 subsys_initcall(omap_i2c_init_driver);
1013
1014 static void __exit omap_i2c_exit_driver(void)
1015 {
1016 platform_driver_unregister(&omap_i2c_driver);
1017 }
1018 module_exit(omap_i2c_exit_driver);
1019
1020 MODULE_AUTHOR("MontaVista Software, Inc. (and others)");
1021 MODULE_DESCRIPTION("TI OMAP I2C bus adapter");
1022 MODULE_LICENSE("GPL");
1023 MODULE_ALIAS("platform:i2c_omap");
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