drivers/i2c/busses/i2c-pnx.c

   1 /*
   2  * Provides I2C support for Philips PNX010x/PNX4008 boards.
   3  *
   4  * Authors: Dennis Kovalev <dkovalev@ru.mvista.com>
   5  *          Vitaly Wool <vwool@ru.mvista.com>
   6  *
   7  * 2004-2006 (c) MontaVista Software, Inc. This file is licensed under
   8  * the terms of the GNU General Public License version 2. This program
   9  * is licensed "as is" without any warranty of any kind, whether express
  10  * or implied.
  11  */
  12
  13 #include <linux/module.h>
  14 #include <linux/interrupt.h>
  15 #include <linux/ioport.h>
  16 #include <linux/delay.h>
  17 #include <linux/i2c.h>
  18 #include <linux/timer.h>
  19 #include <linux/completion.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/i2c-pnx.h>
  22 #include <linux/io.h>
  23 #include <linux/err.h>
  24 #include <linux/clk.h>
  25 #include <linux/slab.h>
  26 #include <linux/of.h>
  27
  28 #define I2C_PNX_TIMEOUT_DEFAULT         10 /* msec */
  29 #define I2C_PNX_SPEED_KHZ_DEFAULT       100
  30 #define I2C_PNX_REGION_SIZE             0x100
  31
  32 enum {
  33         mstatus_tdi = 0x00000001,
  34         mstatus_afi = 0x00000002,
  35         mstatus_nai = 0x00000004,
  36         mstatus_drmi = 0x00000008,
  37         mstatus_active = 0x00000020,
  38         mstatus_scl = 0x00000040,
  39         mstatus_sda = 0x00000080,
  40         mstatus_rff = 0x00000100,
  41         mstatus_rfe = 0x00000200,
  42         mstatus_tff = 0x00000400,
  43         mstatus_tfe = 0x00000800,
  44 };
  45
  46 enum {
  47         mcntrl_tdie = 0x00000001,
  48         mcntrl_afie = 0x00000002,
  49         mcntrl_naie = 0x00000004,
  50         mcntrl_drmie = 0x00000008,
  51         mcntrl_drsie = 0x00000010,
  52         mcntrl_rffie = 0x00000020,
  53         mcntrl_daie = 0x00000040,
  54         mcntrl_tffie = 0x00000080,
  55         mcntrl_reset = 0x00000100,
  56         mcntrl_cdbmode = 0x00000400,
  57 };
  58
  59 enum {
  60         rw_bit = 1 << 0,
  61         start_bit = 1 << 8,
  62         stop_bit = 1 << 9,
  63 };
  64
  65 #define I2C_REG_RX(a)   ((a)->ioaddr)           /* Rx FIFO reg (RO) */
  66 #define I2C_REG_TX(a)   ((a)->ioaddr)           /* Tx FIFO reg (WO) */
  67 #define I2C_REG_STS(a)  ((a)->ioaddr + 0x04)    /* Status reg (RO) */
  68 #define I2C_REG_CTL(a)  ((a)->ioaddr + 0x08)    /* Ctl reg */
  69 #define I2C_REG_CKL(a)  ((a)->ioaddr + 0x0c)    /* Clock divider low */
  70 #define I2C_REG_CKH(a)  ((a)->ioaddr + 0x10)    /* Clock divider high */
  71 #define I2C_REG_ADR(a)  ((a)->ioaddr + 0x14)    /* I2C address */
  72 #define I2C_REG_RFL(a)  ((a)->ioaddr + 0x18)    /* Rx FIFO level (RO) */
  73 #define I2C_REG_TFL(a)  ((a)->ioaddr + 0x1c)    /* Tx FIFO level (RO) */
  74 #define I2C_REG_RXB(a)  ((a)->ioaddr + 0x20)    /* Num of bytes Rx-ed (RO) */
  75 #define I2C_REG_TXB(a)  ((a)->ioaddr + 0x24)    /* Num of bytes Tx-ed (RO) */
  76 #define I2C_REG_TXS(a)  ((a)->ioaddr + 0x28)    /* Tx slave FIFO (RO) */
  77 #define I2C_REG_STFL(a) ((a)->ioaddr + 0x2c)    /* Tx slave FIFO level (RO) */
  78
  79 static inline int wait_timeout(struct i2c_pnx_algo_data *data)
  80 {
  81         long timeout = data->timeout;
  82         while (timeout > 0 &&
  83                         (ioread32(I2C_REG_STS(data)) & mstatus_active)) {
  84                 mdelay(1);
  85                 timeout--;
  86         }
  87         return (timeout <= 0);
  88 }
  89
  90 static inline int wait_reset(struct i2c_pnx_algo_data *data)
  91 {
  92         long timeout = data->timeout;
  93         while (timeout > 0 &&
  94                         (ioread32(I2C_REG_CTL(data)) & mcntrl_reset)) {
  95                 mdelay(1);
  96                 timeout--;
  97         }
  98         return (timeout <= 0);
  99 }
 100
 101 static inline void i2c_pnx_arm_timer(struct i2c_pnx_algo_data *alg_data)
 102 {
 103         struct timer_list *timer = &alg_data->mif.timer;
 104         unsigned long expires = msecs_to_jiffies(alg_data->timeout);
 105
 106         if (expires <= 1)
 107                 expires = 2;
 108
 109         del_timer_sync(timer);
 110
 111         dev_dbg(&alg_data->adapter.dev, "Timer armed at %lu plus %lu jiffies.\n",
 112                 jiffies, expires);
 113
 114         timer->expires = jiffies + expires;
 115
 116         add_timer(timer);
 117 }
 118
 119 /**
 120  * i2c_pnx_start - start a device
 121  * @slave_addr:         slave address
 122  * @adap:               pointer to adapter structure
 123  *
 124  * Generate a START signal in the desired mode.
 125  */
 126 static int i2c_pnx_start(unsigned char slave_addr,
 127         struct i2c_pnx_algo_data *alg_data)
 128 {
 129         dev_dbg(&alg_data->adapter.dev, "%s(): addr 0x%x mode %d\n", __func__,
 130                 slave_addr, alg_data->mif.mode);
 131
 132         /* Check for 7 bit slave addresses only */
 133         if (slave_addr & ~0x7f) {
 134                 dev_err(&alg_data->adapter.dev,
 135                         "%s: Invalid slave address %x. Only 7-bit addresses are supported\n",
 136                         alg_data->adapter.name, slave_addr);
 137                 return -EINVAL;
 138         }
 139
 140         /* First, make sure bus is idle */
 141         if (wait_timeout(alg_data)) {
 142                 /* Somebody else is monopolizing the bus */
 143                 dev_err(&alg_data->adapter.dev,
 144                         "%s: Bus busy. Slave addr = %02x, cntrl = %x, stat = %x\n",
 145                         alg_data->adapter.name, slave_addr,
 146                         ioread32(I2C_REG_CTL(alg_data)),
 147                         ioread32(I2C_REG_STS(alg_data)));
 148                 return -EBUSY;
 149         } else if (ioread32(I2C_REG_STS(alg_data)) & mstatus_afi) {
 150                 /* Sorry, we lost the bus */
 151                 dev_err(&alg_data->adapter.dev,
 152                         "%s: Arbitration failure. Slave addr = %02x\n",
 153                         alg_data->adapter.name, slave_addr);
 154                 return -EIO;
 155         }
 156
 157         /*
 158          * OK, I2C is enabled and we have the bus.
 159          * Clear the current TDI and AFI status flags.
 160          */
 161         iowrite32(ioread32(I2C_REG_STS(alg_data)) | mstatus_tdi | mstatus_afi,
 162                   I2C_REG_STS(alg_data));
 163
 164         dev_dbg(&alg_data->adapter.dev, "%s(): sending %#x\n", __func__,
 165                 (slave_addr << 1) | start_bit | alg_data->mif.mode);
 166
 167         /* Write the slave address, START bit and R/W bit */
 168         iowrite32((slave_addr << 1) | start_bit | alg_data->mif.mode,
 169                   I2C_REG_TX(alg_data));
 170
 171         dev_dbg(&alg_data->adapter.dev, "%s(): exit\n", __func__);
 172
 173         return 0;
 174 }
 175
 176 /**
 177  * i2c_pnx_stop - stop a device
 178  * @adap:               pointer to I2C adapter structure
 179  *
 180  * Generate a STOP signal to terminate the master transaction.
 181  */
 182 static void i2c_pnx_stop(struct i2c_pnx_algo_data *alg_data)
 183 {
 184         /* Only 1 msec max timeout due to interrupt context */
 185         long timeout = 1000;
 186
 187         dev_dbg(&alg_data->adapter.dev, "%s(): entering: stat = %04x.\n",
 188                 __func__, ioread32(I2C_REG_STS(alg_data)));
 189
 190         /* Write a STOP bit to TX FIFO */
 191         iowrite32(0xff | stop_bit, I2C_REG_TX(alg_data));
 192
 193         /* Wait until the STOP is seen. */
 194         while (timeout > 0 &&
 195                (ioread32(I2C_REG_STS(alg_data)) & mstatus_active)) {
 196                 /* may be called from interrupt context */
 197                 udelay(1);
 198                 timeout--;
 199         }
 200
 201         dev_dbg(&alg_data->adapter.dev, "%s(): exiting: stat = %04x.\n",
 202                 __func__, ioread32(I2C_REG_STS(alg_data)));
 203 }
 204
 205 /**
 206  * i2c_pnx_master_xmit - transmit data to slave
 207  * @adap:               pointer to I2C adapter structure
 208  *
 209  * Sends one byte of data to the slave
 210  */
 211 static int i2c_pnx_master_xmit(struct i2c_pnx_algo_data *alg_data)
 212 {
 213         u32 val;
 214
 215         dev_dbg(&alg_data->adapter.dev, "%s(): entering: stat = %04x.\n",
 216                 __func__, ioread32(I2C_REG_STS(alg_data)));
 217
 218         if (alg_data->mif.len > 0) {
 219                 /* We still have something to talk about... */
 220                 val = *alg_data->mif.buf++;
 221
 222                 if (alg_data->mif.len == 1)
 223                         val |= stop_bit;
 224
 225                 alg_data->mif.len--;
 226                 iowrite32(val, I2C_REG_TX(alg_data));
 227
 228                 dev_dbg(&alg_data->adapter.dev, "%s(): xmit %#x [%d]\n",
 229                         __func__, val, alg_data->mif.len + 1);
 230
 231                 if (alg_data->mif.len == 0) {
 232                         if (alg_data->last) {
 233                                 /* Wait until the STOP is seen. */
 234                                 if (wait_timeout(alg_data))
 235                                         dev_err(&alg_data->adapter.dev,
 236                                                 "The bus is still active after timeout\n");
 237                         }
 238                         /* Disable master interrupts */
 239                         iowrite32(ioread32(I2C_REG_CTL(alg_data)) &
 240                                 ~(mcntrl_afie | mcntrl_naie | mcntrl_drmie),
 241                                   I2C_REG_CTL(alg_data));
 242
 243                         del_timer_sync(&alg_data->mif.timer);
 244
 245                         dev_dbg(&alg_data->adapter.dev,
 246                                 "%s(): Waking up xfer routine.\n",
 247                                 __func__);
 248
 249                         complete(&alg_data->mif.complete);
 250                 }
 251         } else if (alg_data->mif.len == 0) {
 252                 /* zero-sized transfer */
 253                 i2c_pnx_stop(alg_data);
 254
 255                 /* Disable master interrupts. */
 256                 iowrite32(ioread32(I2C_REG_CTL(alg_data)) &
 257                         ~(mcntrl_afie | mcntrl_naie | mcntrl_drmie),
 258                           I2C_REG_CTL(alg_data));
 259
 260                 /* Stop timer. */
 261                 del_timer_sync(&alg_data->mif.timer);
 262                 dev_dbg(&alg_data->adapter.dev,
 263                         "%s(): Waking up xfer routine after zero-xfer.\n",
 264                         __func__);
 265
 266                 complete(&alg_data->mif.complete);
 267         }
 268
 269         dev_dbg(&alg_data->adapter.dev, "%s(): exiting: stat = %04x.\n",
 270                 __func__, ioread32(I2C_REG_STS(alg_data)));
 271
 272         return 0;
 273 }
 274
 275 /**
 276  * i2c_pnx_master_rcv - receive data from slave
 277  * @adap:               pointer to I2C adapter structure
 278  *
 279  * Reads one byte data from the slave
 280  */
 281 static int i2c_pnx_master_rcv(struct i2c_pnx_algo_data *alg_data)
 282 {
 283         unsigned int val = 0;
 284         u32 ctl = 0;
 285
 286         dev_dbg(&alg_data->adapter.dev, "%s(): entering: stat = %04x.\n",
 287                 __func__, ioread32(I2C_REG_STS(alg_data)));
 288
 289         /* Check, whether there is already data,
 290          * or we didn't 'ask' for it yet.
 291          */
 292         if (ioread32(I2C_REG_STS(alg_data)) & mstatus_rfe) {
 293                 /* 'Asking' is done asynchronously, e.g. dummy TX of several
 294                  * bytes is done before the first actual RX arrives in FIFO.
 295                  * Therefore, ordered bytes (via TX) are counted separately.
 296                  */
 297                 if (alg_data->mif.order) {
 298                         dev_dbg(&alg_data->adapter.dev,
 299                                 "%s(): Write dummy data to fill Rx-fifo...\n",
 300                                 __func__);
 301
 302                         if (alg_data->mif.order == 1) {
 303                                 /* Last byte, do not acknowledge next rcv. */
 304                                 val |= stop_bit;
 305
 306                                 /*
 307                                  * Enable interrupt RFDAIE (data in Rx fifo),
 308                                  * and disable DRMIE (need data for Tx)
 309                                  */
 310                                 ctl = ioread32(I2C_REG_CTL(alg_data));
 311                                 ctl |= mcntrl_rffie | mcntrl_daie;
 312                                 ctl &= ~mcntrl_drmie;
 313                                 iowrite32(ctl, I2C_REG_CTL(alg_data));
 314                         }
 315
 316                         /*
 317                          * Now we'll 'ask' for data:
 318                          * For each byte we want to receive, we must
 319                          * write a (dummy) byte to the Tx-FIFO.
 320                          */
 321                         iowrite32(val, I2C_REG_TX(alg_data));
 322                         alg_data->mif.order--;
 323                 }
 324                 return 0;
 325         }
 326
 327         /* Handle data. */
 328         if (alg_data->mif.len > 0) {
 329                 val = ioread32(I2C_REG_RX(alg_data));
 330                 *alg_data->mif.buf++ = (u8) (val & 0xff);
 331                 dev_dbg(&alg_data->adapter.dev, "%s(): rcv 0x%x [%d]\n",
 332                         __func__, val, alg_data->mif.len);
 333
 334                 alg_data->mif.len--;
 335                 if (alg_data->mif.len == 0) {
 336                         if (alg_data->last)
 337                                 /* Wait until the STOP is seen. */
 338                                 if (wait_timeout(alg_data))
 339                                         dev_err(&alg_data->adapter.dev,
 340                                                 "The bus is still active after timeout\n");
 341
 342                         /* Disable master interrupts */
 343                         ctl = ioread32(I2C_REG_CTL(alg_data));
 344                         ctl &= ~(mcntrl_afie | mcntrl_naie | mcntrl_rffie |
 345                                  mcntrl_drmie | mcntrl_daie);
 346                         iowrite32(ctl, I2C_REG_CTL(alg_data));
 347
 348                         /* Kill timer. */
 349                         del_timer_sync(&alg_data->mif.timer);
 350                         complete(&alg_data->mif.complete);
 351                 }
 352         }
 353
 354         dev_dbg(&alg_data->adapter.dev, "%s(): exiting: stat = %04x.\n",
 355                 __func__, ioread32(I2C_REG_STS(alg_data)));
 356
 357         return 0;
 358 }
 359
 360 static irqreturn_t i2c_pnx_interrupt(int irq, void *dev_id)
 361 {
 362         struct i2c_pnx_algo_data *alg_data = dev_id;
 363         u32 stat, ctl;
 364
 365         dev_dbg(&alg_data->adapter.dev,
 366                 "%s(): mstat = %x mctrl = %x, mode = %d\n",
 367                 __func__,
 368                 ioread32(I2C_REG_STS(alg_data)),
 369                 ioread32(I2C_REG_CTL(alg_data)),
 370                 alg_data->mif.mode);
 371         stat = ioread32(I2C_REG_STS(alg_data));
 372
 373         /* let's see what kind of event this is */
 374         if (stat & mstatus_afi) {
 375                 /* We lost arbitration in the midst of a transfer */
 376                 alg_data->mif.ret = -EIO;
 377
 378                 /* Disable master interrupts. */
 379                 ctl = ioread32(I2C_REG_CTL(alg_data));
 380                 ctl &= ~(mcntrl_afie | mcntrl_naie | mcntrl_rffie |
 381                          mcntrl_drmie);
 382                 iowrite32(ctl, I2C_REG_CTL(alg_data));
 383
 384                 /* Stop timer, to prevent timeout. */
 385                 del_timer_sync(&alg_data->mif.timer);
 386                 complete(&alg_data->mif.complete);
 387         } else if (stat & mstatus_nai) {
 388                 /* Slave did not acknowledge, generate a STOP */
 389                 dev_dbg(&alg_data->adapter.dev,
 390                         "%s(): Slave did not acknowledge, generating a STOP.\n",
 391                         __func__);
 392                 i2c_pnx_stop(alg_data);
 393
 394                 /* Disable master interrupts. */
 395                 ctl = ioread32(I2C_REG_CTL(alg_data));
 396                 ctl &= ~(mcntrl_afie | mcntrl_naie | mcntrl_rffie |
 397                          mcntrl_drmie);
 398                 iowrite32(ctl, I2C_REG_CTL(alg_data));
 399
 400                 /* Our return value. */
 401                 alg_data->mif.ret = -EIO;
 402
 403                 /* Stop timer, to prevent timeout. */
 404                 del_timer_sync(&alg_data->mif.timer);
 405                 complete(&alg_data->mif.complete);
 406         } else {
 407                 /*
 408                  * Two options:
 409                  * - Master Tx needs data.
 410                  * - There is data in the Rx-fifo
 411                  * The latter is only the case if we have requested for data,
 412                  * via a dummy write. (See 'i2c_pnx_master_rcv'.)
 413                  * We therefore check, as a sanity check, whether that interrupt
 414                  * has been enabled.
 415                  */
 416                 if ((stat & mstatus_drmi) || !(stat & mstatus_rfe)) {
 417                         if (alg_data->mif.mode == I2C_SMBUS_WRITE) {
 418                                 i2c_pnx_master_xmit(alg_data);
 419                         } else if (alg_data->mif.mode == I2C_SMBUS_READ) {
 420                                 i2c_pnx_master_rcv(alg_data);
 421                         }
 422                 }
 423         }
 424
 425         /* Clear TDI and AFI bits */
 426         stat = ioread32(I2C_REG_STS(alg_data));
 427         iowrite32(stat | mstatus_tdi | mstatus_afi, I2C_REG_STS(alg_data));
 428
 429         dev_dbg(&alg_data->adapter.dev,
 430                 "%s(): exiting, stat = %x ctrl = %x.\n",
 431                  __func__, ioread32(I2C_REG_STS(alg_data)),
 432                  ioread32(I2C_REG_CTL(alg_data)));
 433
 434         return IRQ_HANDLED;
 435 }
 436
 437 static void i2c_pnx_timeout(struct timer_list *t)
 438 {
 439         struct i2c_pnx_algo_data *alg_data = from_timer(alg_data, t, mif.timer);
 440         u32 ctl;
 441
 442         dev_err(&alg_data->adapter.dev,
 443                 "Master timed out. stat = %04x, cntrl = %04x. Resetting master...\n",
 444                 ioread32(I2C_REG_STS(alg_data)),
 445                 ioread32(I2C_REG_CTL(alg_data)));
 446
 447         /* Reset master and disable interrupts */
 448         ctl = ioread32(I2C_REG_CTL(alg_data));
 449         ctl &= ~(mcntrl_afie | mcntrl_naie | mcntrl_rffie | mcntrl_drmie);
 450         iowrite32(ctl, I2C_REG_CTL(alg_data));
 451
 452         ctl |= mcntrl_reset;
 453         iowrite32(ctl, I2C_REG_CTL(alg_data));
 454         wait_reset(alg_data);
 455         alg_data->mif.ret = -EIO;
 456         complete(&alg_data->mif.complete);
 457 }
 458
 459 static inline void bus_reset_if_active(struct i2c_pnx_algo_data *alg_data)
 460 {
 461         u32 stat;
 462
 463         if ((stat = ioread32(I2C_REG_STS(alg_data))) & mstatus_active) {
 464                 dev_err(&alg_data->adapter.dev,
 465                         "%s: Bus is still active after xfer. Reset it...\n",
 466                         alg_data->adapter.name);
 467                 iowrite32(ioread32(I2C_REG_CTL(alg_data)) | mcntrl_reset,
 468                           I2C_REG_CTL(alg_data));
 469                 wait_reset(alg_data);
 470         } else if (!(stat & mstatus_rfe) || !(stat & mstatus_tfe)) {
 471                 /* If there is data in the fifo's after transfer,
 472                  * flush fifo's by reset.
 473                  */
 474                 iowrite32(ioread32(I2C_REG_CTL(alg_data)) | mcntrl_reset,
 475                           I2C_REG_CTL(alg_data));
 476                 wait_reset(alg_data);
 477         } else if (stat & mstatus_nai) {
 478                 iowrite32(ioread32(I2C_REG_CTL(alg_data)) | mcntrl_reset,
 479                           I2C_REG_CTL(alg_data));
 480                 wait_reset(alg_data);
 481         }
 482 }
 483
 484 /**
 485  * i2c_pnx_xfer - generic transfer entry point
 486  * @adap:               pointer to I2C adapter structure
 487  * @msgs:               array of messages
 488  * @num:                number of messages
 489  *
 490  * Initiates the transfer
 491  */
 492 static int
 493 i2c_pnx_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
 494 {
 495         struct i2c_msg *pmsg;
 496         int rc = 0, completed = 0, i;
 497         struct i2c_pnx_algo_data *alg_data = adap->algo_data;
 498         u32 stat;
 499
 500         dev_dbg(&alg_data->adapter.dev,
 501                 "%s(): entering: %d messages, stat = %04x.\n",
 502                 __func__, num, ioread32(I2C_REG_STS(alg_data)));
 503
 504         bus_reset_if_active(alg_data);
 505
 506         /* Process transactions in a loop. */
 507         for (i = 0; rc >= 0 && i < num; i++) {
 508                 u8 addr;
 509
 510                 pmsg = &msgs[i];
 511                 addr = pmsg->addr;
 512
 513                 if (pmsg->flags & I2C_M_TEN) {
 514                         dev_err(&alg_data->adapter.dev,
 515                                 "%s: 10 bits addr not supported!\n",
 516                                 alg_data->adapter.name);
 517                         rc = -EINVAL;
 518                         break;
 519                 }
 520
 521                 alg_data->mif.buf = pmsg->buf;
 522                 alg_data->mif.len = pmsg->len;
 523                 alg_data->mif.order = pmsg->len;
 524                 alg_data->mif.mode = (pmsg->flags & I2C_M_RD) ?
 525                         I2C_SMBUS_READ : I2C_SMBUS_WRITE;
 526                 alg_data->mif.ret = 0;
 527                 alg_data->last = (i == num - 1);
 528
 529                 dev_dbg(&alg_data->adapter.dev, "%s(): mode %d, %d bytes\n",
 530                         __func__, alg_data->mif.mode, alg_data->mif.len);
 531
 532                 i2c_pnx_arm_timer(alg_data);
 533
 534                 /* initialize the completion var */
 535                 init_completion(&alg_data->mif.complete);
 536
 537                 /* Enable master interrupt */
 538                 iowrite32(ioread32(I2C_REG_CTL(alg_data)) | mcntrl_afie |
 539                                 mcntrl_naie | mcntrl_drmie,
 540                           I2C_REG_CTL(alg_data));
 541
 542                 /* Put start-code and slave-address on the bus. */
 543                 rc = i2c_pnx_start(addr, alg_data);
 544                 if (rc < 0)
 545                         break;
 546
 547                 /* Wait for completion */
 548                 wait_for_completion(&alg_data->mif.complete);
 549
 550                 if (!(rc = alg_data->mif.ret))
 551                         completed++;
 552                 dev_dbg(&alg_data->adapter.dev,
 553                         "%s(): Complete, return code = %d.\n",
 554                         __func__, rc);
 555
 556                 /* Clear TDI and AFI bits in case they are set. */
 557                 if ((stat = ioread32(I2C_REG_STS(alg_data))) & mstatus_tdi) {
 558                         dev_dbg(&alg_data->adapter.dev,
 559                                 "%s: TDI still set... clearing now.\n",
 560                                 alg_data->adapter.name);
 561                         iowrite32(stat, I2C_REG_STS(alg_data));
 562                 }
 563                 if ((stat = ioread32(I2C_REG_STS(alg_data))) & mstatus_afi) {
 564                         dev_dbg(&alg_data->adapter.dev,
 565                                 "%s: AFI still set... clearing now.\n",
 566                                 alg_data->adapter.name);
 567                         iowrite32(stat, I2C_REG_STS(alg_data));
 568                 }
 569         }
 570
 571         bus_reset_if_active(alg_data);
 572
 573         /* Cleanup to be sure... */
 574         alg_data->mif.buf = NULL;
 575         alg_data->mif.len = 0;
 576         alg_data->mif.order = 0;
 577
 578         dev_dbg(&alg_data->adapter.dev, "%s(): exiting, stat = %x\n",
 579                 __func__, ioread32(I2C_REG_STS(alg_data)));
 580
 581         if (completed != num)
 582                 return ((rc < 0) ? rc : -EREMOTEIO);
 583
 584         return num;
 585 }
 586
 587 static u32 i2c_pnx_func(struct i2c_adapter *adapter)
 588 {
 589         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
 590 }
 591
 592 static const struct i2c_algorithm pnx_algorithm = {
 593         .master_xfer = i2c_pnx_xfer,
 594         .functionality = i2c_pnx_func,
 595 };
 596
 597 #ifdef CONFIG_PM_SLEEP
 598 static int i2c_pnx_controller_suspend(struct device *dev)
 599 {
 600         struct i2c_pnx_algo_data *alg_data = dev_get_drvdata(dev);
 601
 602         clk_disable_unprepare(alg_data->clk);
 603
 604         return 0;
 605 }
 606
 607 static int i2c_pnx_controller_resume(struct device *dev)
 608 {
 609         struct i2c_pnx_algo_data *alg_data = dev_get_drvdata(dev);
 610
 611         return clk_prepare_enable(alg_data->clk);
 612 }
 613
 614 static SIMPLE_DEV_PM_OPS(i2c_pnx_pm,
 615                          i2c_pnx_controller_suspend, i2c_pnx_controller_resume);
 616 #define PNX_I2C_PM      (&i2c_pnx_pm)
 617 #else
 618 #define PNX_I2C_PM      NULL
 619 #endif
 620
 621 static int i2c_pnx_probe(struct platform_device *pdev)
 622 {
 623         unsigned long tmp;
 624         int ret = 0;
 625         struct i2c_pnx_algo_data *alg_data;
 626         unsigned long freq;
 627         struct resource *res;
 628         u32 speed = I2C_PNX_SPEED_KHZ_DEFAULT * 1000;
 629
 630         alg_data = devm_kzalloc(&pdev->dev, sizeof(*alg_data), GFP_KERNEL);
 631         if (!alg_data)
 632                 return -ENOMEM;
 633
 634         platform_set_drvdata(pdev, alg_data);
 635
 636         alg_data->adapter.dev.parent = &pdev->dev;
 637         alg_data->adapter.algo = &pnx_algorithm;
 638         alg_data->adapter.algo_data = alg_data;
 639         alg_data->adapter.nr = pdev->id;
 640
 641         alg_data->timeout = I2C_PNX_TIMEOUT_DEFAULT;
 642 #ifdef CONFIG_OF
 643         alg_data->adapter.dev.of_node = of_node_get(pdev->dev.of_node);
 644         if (pdev->dev.of_node) {
 645                 of_property_read_u32(pdev->dev.of_node, "clock-frequency",
 646                                      &speed);
 647                 /*
 648                  * At this point, it is planned to add an OF timeout property.
 649                  * As soon as there is a consensus about how to call and handle
 650                  * this, sth. like the following can be put here:
 651                  *
 652                  * of_property_read_u32(pdev->dev.of_node, "timeout",
 653                  *                      &alg_data->timeout);
 654                  */
 655         }
 656 #endif
 657         alg_data->clk = devm_clk_get(&pdev->dev, NULL);
 658         if (IS_ERR(alg_data->clk))
 659                 return PTR_ERR(alg_data->clk);
 660
 661         timer_setup(&alg_data->mif.timer, i2c_pnx_timeout, 0);
 662
 663         snprintf(alg_data->adapter.name, sizeof(alg_data->adapter.name),
 664                  "%s", pdev->name);
 665
 666         /* Register I/O resource */
 667         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 668         alg_data->ioaddr = devm_ioremap_resource(&pdev->dev, res);
 669         if (IS_ERR(alg_data->ioaddr))
 670                 return PTR_ERR(alg_data->ioaddr);
 671
 672         ret = clk_prepare_enable(alg_data->clk);
 673         if (ret)
 674                 return ret;
 675
 676         freq = clk_get_rate(alg_data->clk);
 677
 678         /*
 679          * Clock Divisor High This value is the number of system clocks
 680          * the serial clock (SCL) will be high.
 681          * For example, if the system clock period is 50 ns and the maximum
 682          * desired serial period is 10000 ns (100 kHz), then CLKHI would be
 683          * set to 0.5*(f_sys/f_i2c)-2=0.5*(20e6/100e3)-2=98. The actual value
 684          * programmed into CLKHI will vary from this slightly due to
 685          * variations in the output pad's rise and fall times as well as
 686          * the deglitching filter length.
 687          */
 688
 689         tmp = (freq / speed) / 2 - 2;
 690         if (tmp > 0x3FF)
 691                 tmp = 0x3FF;
 692         iowrite32(tmp, I2C_REG_CKH(alg_data));
 693         iowrite32(tmp, I2C_REG_CKL(alg_data));
 694
 695         iowrite32(mcntrl_reset, I2C_REG_CTL(alg_data));
 696         if (wait_reset(alg_data)) {
 697                 ret = -ENODEV;
 698                 goto out_clock;
 699         }
 700         init_completion(&alg_data->mif.complete);
 701
 702         alg_data->irq = platform_get_irq(pdev, 0);
 703         if (alg_data->irq < 0) {
 704                 dev_err(&pdev->dev, "Failed to get IRQ from platform resource\n");
 705                 ret = alg_data->irq;
 706                 goto out_clock;
 707         }
 708         ret = devm_request_irq(&pdev->dev, alg_data->irq, i2c_pnx_interrupt,
 709                                0, pdev->name, alg_data);
 710         if (ret)
 711                 goto out_clock;
 712
 713         /* Register this adapter with the I2C subsystem */
 714         ret = i2c_add_numbered_adapter(&alg_data->adapter);
 715         if (ret < 0)
 716                 goto out_clock;
 717
 718         dev_dbg(&pdev->dev, "%s: Master at %#8x, irq %d.\n",
 719                 alg_data->adapter.name, res->start, alg_data->irq);
 720
 721         return 0;
 722
 723 out_clock:
 724         clk_disable_unprepare(alg_data->clk);
 725         return ret;
 726 }
 727
 728 static int i2c_pnx_remove(struct platform_device *pdev)
 729 {
 730         struct i2c_pnx_algo_data *alg_data = platform_get_drvdata(pdev);
 731
 732         i2c_del_adapter(&alg_data->adapter);
 733         clk_disable_unprepare(alg_data->clk);
 734
 735         return 0;
 736 }
 737
 738 #ifdef CONFIG_OF
 739 static const struct of_device_id i2c_pnx_of_match[] = {
 740         { .compatible = "nxp,pnx-i2c" },
 741         { },
 742 };
 743 MODULE_DEVICE_TABLE(of, i2c_pnx_of_match);
 744 #endif
 745
 746 static struct platform_driver i2c_pnx_driver = {
 747         .driver = {
 748                 .name = "pnx-i2c",
 749                 .of_match_table = of_match_ptr(i2c_pnx_of_match),
 750                 .pm = PNX_I2C_PM,
 751         },
 752         .probe = i2c_pnx_probe,
 753         .remove = i2c_pnx_remove,
 754 };
 755
 756 static int __init i2c_adap_pnx_init(void)
 757 {
 758         return platform_driver_register(&i2c_pnx_driver);
 759 }
 760
 761 static void __exit i2c_adap_pnx_exit(void)
 762 {
 763         platform_driver_unregister(&i2c_pnx_driver);
 764 }
 765
 766 MODULE_AUTHOR("Vitaly Wool, Dennis Kovalev <source@mvista.com>");
 767 MODULE_DESCRIPTION("I2C driver for Philips IP3204-based I2C busses");
 768 MODULE_LICENSE("GPL");
 769 MODULE_ALIAS("platform:pnx-i2c");
 770
 771 /* We need to make sure I2C is initialized before USB */
 772 subsys_initcall(i2c_adap_pnx_init);
 773 module_exit(i2c_adap_pnx_exit);