drivers/i2c/busses/i2c-qcom-cci.c

   1 /* Copyright (c) 2012-2016, The Linux Foundation. All rights reserved.
   2  * Copyright (C) 2017 Linaro Ltd.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 and
   6  * only version 2 as published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  */
  13
  14 #include <linux/clk.h>
  15 #include <linux/completion.h>
  16 #include <linux/i2c.h>
  17 #include <linux/io.h>
  18 #include <linux/interrupt.h>
  19 #include <linux/module.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/of.h>
  22
  23 #define CCI_HW_VERSION                  0x0
  24 #define CCI_RESET_CMD                   0x004
  25 #define CCI_RESET_CMD_MASK              0x0f73f3f7
  26 #define CCI_RESET_CMD_M0_MASK           0x000003f1
  27 #define CCI_RESET_CMD_M1_MASK           0x0003f001
  28 #define CCI_QUEUE_START                 0x008
  29 #define CCI_HALT_REQ                    0x034
  30 #define CCI_HALT_REQ_I2C_M0_Q0Q1        BIT(0)
  31 #define CCI_HALT_REQ_I2C_M1_Q0Q1        BIT(1)
  32
  33 #define CCI_I2C_Mm_SCL_CTL(m)           (0x100 + 0x100 * (m))
  34 #define CCI_I2C_Mm_SDA_CTL_0(m)         (0x104 + 0x100 * (m))
  35 #define CCI_I2C_Mm_SDA_CTL_1(m)         (0x108 + 0x100 * (m))
  36 #define CCI_I2C_Mm_SDA_CTL_2(m)         (0x10c + 0x100 * (m))
  37 #define CCI_I2C_Mm_MISC_CTL(m)          (0x110 + 0x100 * (m))
  38
  39 #define CCI_I2C_Mm_READ_DATA(m)                 (0x118 + 0x100 * (m))
  40 #define CCI_I2C_Mm_READ_BUF_LEVEL(m)            (0x11c + 0x100 * (m))
  41 #define CCI_I2C_Mm_Qn_EXEC_WORD_CNT(m, n)       (0x300 + 0x200 * (m) + 0x100 * (n))
  42 #define CCI_I2C_Mm_Qn_CUR_WORD_CNT(m, n)        (0x304 + 0x200 * (m) + 0x100 * (n))
  43 #define CCI_I2C_Mm_Qn_CUR_CMD(m, n)             (0x308 + 0x200 * (m) + 0x100 * (n))
  44 #define CCI_I2C_Mm_Qn_REPORT_STATUS(m, n)       (0x30c + 0x200 * (m) + 0x100 * (n))
  45 #define CCI_I2C_Mm_Qn_LOAD_DATA(m, n)           (0x310 + 0x200 * (m) + 0x100 * (n))
  46
  47 #define CCI_IRQ_GLOBAL_CLEAR_CMD        0xc00
  48 #define CCI_IRQ_MASK_0                  0xc04
  49 #define CCI_IRQ_MASK_0_I2C_M0_RD_DONE           BIT(0)
  50 #define CCI_IRQ_MASK_0_I2C_M0_Q0_REPORT         BIT(4)
  51 #define CCI_IRQ_MASK_0_I2C_M0_Q1_REPORT         BIT(8)
  52 #define CCI_IRQ_MASK_0_I2C_M1_RD_DONE           BIT(12)
  53 #define CCI_IRQ_MASK_0_I2C_M1_Q0_REPORT         BIT(16)
  54 #define CCI_IRQ_MASK_0_I2C_M1_Q1_REPORT         BIT(20)
  55 #define CCI_IRQ_MASK_0_RST_DONE_ACK             BIT(24)
  56 #define CCI_IRQ_MASK_0_I2C_M0_Q0Q1_HALT_ACK     BIT(25)
  57 #define CCI_IRQ_MASK_0_I2C_M1_Q0Q1_HALT_ACK     BIT(26)
  58 #define CCI_IRQ_MASK_0_I2C_M0_ERROR             0x18000ee6
  59 #define CCI_IRQ_MASK_0_I2C_M1_ERROR             0x60ee6000
  60 #define CCI_IRQ_CLEAR_0                 0xc08
  61 #define CCI_IRQ_STATUS_0                0xc0c
  62 #define CCI_IRQ_STATUS_0_I2C_M0_RD_DONE         BIT(0)
  63 #define CCI_IRQ_STATUS_0_I2C_M0_Q0_REPORT       BIT(4)
  64 #define CCI_IRQ_STATUS_0_I2C_M0_Q1_REPORT       BIT(8)
  65 #define CCI_IRQ_STATUS_0_I2C_M1_RD_DONE         BIT(12)
  66 #define CCI_IRQ_STATUS_0_I2C_M1_Q0_REPORT       BIT(16)
  67 #define CCI_IRQ_STATUS_0_I2C_M1_Q1_REPORT       BIT(20)
  68 #define CCI_IRQ_STATUS_0_RST_DONE_ACK           BIT(24)
  69 #define CCI_IRQ_STATUS_0_I2C_M0_Q0Q1_HALT_ACK   BIT(25)
  70 #define CCI_IRQ_STATUS_0_I2C_M1_Q0Q1_HALT_ACK   BIT(26)
  71 #define CCI_IRQ_STATUS_0_I2C_M0_ERROR           0x18000ee6
  72 #define CCI_IRQ_STATUS_0_I2C_M1_ERROR           0x60ee6000
  73
  74 #define CCI_TIMEOUT_MS 100
  75 #define NUM_MASTERS 1
  76 #define NUM_QUEUES 2
  77
  78 /* Max number of resources + 1 for a NULL terminator */
  79 #define CCI_RES_MAX 6
  80
  81 enum cci_i2c_cmd {
  82         CCI_I2C_SET_PARAM = 1,
  83         CCI_I2C_WAIT,
  84         CCI_I2C_WAIT_SYNC,
  85         CCI_I2C_WAIT_GPIO_EVENT,
  86         CCI_I2C_TRIG_I2C_EVENT,
  87         CCI_I2C_LOCK,
  88         CCI_I2C_UNLOCK,
  89         CCI_I2C_REPORT,
  90         CCI_I2C_WRITE,
  91         CCI_I2C_READ,
  92         CCI_I2C_WRITE_DISABLE_P,
  93         CCI_I2C_READ_DISABLE_P,
  94 };
  95
  96 enum {
  97         I2C_MODE_STANDARD,
  98         I2C_MODE_FAST,
  99         I2C_MODE_FAST_PLUS,
 100 };
 101
 102 enum cci_i2c_queue_t {
 103         QUEUE_0,
 104         QUEUE_1
 105 };
 106
 107 struct cci_res {
 108         char *clock[CCI_RES_MAX];
 109         u32 clock_rate[CCI_RES_MAX];
 110 };
 111
 112 struct hw_params {
 113         u16 thigh;
 114         u16 tlow;
 115         u16 tsu_sto;
 116         u16 tsu_sta;
 117         u16 thd_dat;
 118         u16 thd_sta;
 119         u16 tbuf;
 120         u8 scl_stretch_en;
 121         u16 trdhld;
 122         u16 tsp;
 123 };
 124
 125 struct cci_clock {
 126         struct clk *clk;
 127         const char *name;
 128         u32 freq;
 129 };
 130
 131 struct cci_master {
 132         int status;
 133         bool complete_pending;
 134         struct completion irq_complete;
 135 };
 136
 137 struct cci {
 138         struct device *dev;
 139         struct i2c_adapter adap;
 140         void __iomem *base;
 141         u32 irq;
 142         struct clk_bulk_data *clock;
 143         u32 *clock_freq;
 144         int nclocks;
 145         u16 queue_size[NUM_QUEUES];
 146         struct cci_master master[NUM_MASTERS];
 147 };
 148
 149 static const struct cci_res res_v1_0_8 = {
 150         .clock = { "camss_top_ahb",
 151                    "cci_ahb",
 152                    "camss_ahb",
 153                    "cci" },
 154         .clock_rate = { 0,
 155                         80000000,
 156                         0,
 157                         19200000 }
 158 };
 159
 160 static const struct cci_res res_v1_4_0 = {
 161         .clock = { "mmss_mmagic_ahb",
 162                    "camss_top_ahb",
 163                    "cci_ahb",
 164                    "camss_ahb",
 165                    "cci" },
 166         .clock_rate = { 0,
 167                         0,
 168                         0,
 169                         0,
 170                         37500000 }
 171 };
 172
 173 static const struct hw_params hw_params_v1_0_8[3] = {
 174         {       /* I2C_MODE_STANDARD */
 175                 .thigh = 78,
 176                 .tlow = 114,
 177                 .tsu_sto = 28,
 178                 .tsu_sta = 28,
 179                 .thd_dat = 10,
 180                 .thd_sta = 77,
 181                 .tbuf = 118,
 182                 .scl_stretch_en = 0,
 183                 .trdhld = 6,
 184                 .tsp = 1
 185         },
 186         {       /* I2C_MODE_FAST */
 187                 .thigh = 20,
 188                 .tlow = 28,
 189                 .tsu_sto = 21,
 190                 .tsu_sta = 21,
 191                 .thd_dat = 13,
 192                 .thd_sta = 18,
 193                 .tbuf = 32,
 194                 .scl_stretch_en = 0,
 195                 .trdhld = 6,
 196                 .tsp = 3
 197         }
 198 };
 199
 200 static const struct hw_params hw_params_v1_4_0[3] = {
 201         {       /* I2C_MODE_STANDARD */
 202                 .thigh = 201,
 203                 .tlow = 174,
 204                 .tsu_sto = 204,
 205                 .tsu_sta = 231,
 206                 .thd_dat = 22,
 207                 .thd_sta = 162,
 208                 .tbuf = 227,
 209                 .scl_stretch_en = 0,
 210                 .trdhld = 6,
 211                 .tsp = 3
 212         },
 213         {       /* I2C_MODE_FAST */
 214                 .thigh = 38,
 215                 .tlow = 56,
 216                 .tsu_sto = 40,
 217                 .tsu_sta = 40,
 218                 .thd_dat = 22,
 219                 .thd_sta = 35,
 220                 .tbuf = 62,
 221                 .scl_stretch_en = 0,
 222                 .trdhld = 6,
 223                 .tsp = 3
 224         },
 225         {       /* I2C_MODE_FAST_PLUS */
 226                 .thigh = 16,
 227                 .tlow = 22,
 228                 .tsu_sto = 17,
 229                 .tsu_sta = 18,
 230                 .thd_dat = 16,
 231                 .thd_sta = 15,
 232                 .tbuf = 24,
 233                 .scl_stretch_en = 0,
 234                 .trdhld = 3,
 235                 .tsp = 3
 236         }
 237 };
 238
 239 static const u16 queue_0_size_v1_0_8 = 64;
 240 static const u16 queue_1_size_v1_0_8 = 16;
 241
 242 static const u16 queue_0_size_v1_4_0 = 64;
 243 static const u16 queue_1_size_v1_4_0 = 16;
 244
 245 /**
 246  * cci_clock_set_rate() - Set clock frequency rates
 247  * @nclocks: Number of clocks
 248  * @clock: Clock array
 249  * @clock_freq: Clock frequency rate array
 250  * @dev: Device
 251  *
 252  * Return 0 on success or a negative error code otherwise
 253  */
 254 int cci_clock_set_rate(int nclocks, struct clk_bulk_data *clock,
 255                        u32 *clock_freq, struct device *dev)
 256 {
 257         int i;
 258
 259         for (i = 0; i < nclocks; i++)
 260                 if (clock_freq[i]) {
 261                         long rate;
 262                         int ret;
 263
 264                         rate = clk_round_rate(clock[i].clk, clock_freq[i]);
 265                         if (rate < 0) {
 266                                 dev_err(dev, "clk round rate failed: %ld\n",
 267                                         rate);
 268                                 return rate;
 269                         }
 270
 271                         ret = clk_set_rate(clock[i].clk, clock_freq[i]);
 272                         if (ret < 0) {
 273                                 dev_err(dev, "clk set rate failed: %d\n", ret);
 274                                 return ret;
 275                         }
 276                 }
 277
 278         return 0;
 279 }
 280
 281 static irqreturn_t cci_isr(int irq, void *dev)
 282 {
 283         struct cci *cci = dev;
 284         u32 reset = 0;
 285         u32 val;
 286
 287         val = readl(cci->base + CCI_IRQ_STATUS_0);
 288         writel(val, cci->base + CCI_IRQ_CLEAR_0);
 289         writel(0x1, cci->base + CCI_IRQ_GLOBAL_CLEAR_CMD);
 290
 291         if (val & CCI_IRQ_STATUS_0_RST_DONE_ACK) {
 292                 if (cci->master[0].complete_pending) {
 293                         cci->master[0].complete_pending = false;
 294                         complete(&cci->master[0].irq_complete);
 295                 }
 296
 297                 if (cci->master[1].complete_pending) {
 298                         cci->master[1].complete_pending = false;
 299                         complete(&cci->master[1].irq_complete);
 300                 }
 301         }
 302
 303         if (val & CCI_IRQ_STATUS_0_I2C_M0_RD_DONE ||
 304                         val & CCI_IRQ_STATUS_0_I2C_M0_Q0_REPORT ||
 305                         val & CCI_IRQ_STATUS_0_I2C_M0_Q1_REPORT) {
 306                 cci->master[0].status = 0;
 307                 complete(&cci->master[0].irq_complete);
 308         }
 309
 310         if (val & CCI_IRQ_STATUS_0_I2C_M1_RD_DONE ||
 311                         val & CCI_IRQ_STATUS_0_I2C_M1_Q0_REPORT ||
 312                         val & CCI_IRQ_STATUS_0_I2C_M1_Q1_REPORT) {
 313                 cci->master[1].status = 0;
 314                 complete(&cci->master[1].irq_complete);
 315         }
 316
 317         if (unlikely(val & CCI_IRQ_STATUS_0_I2C_M0_Q0Q1_HALT_ACK)) {
 318                 cci->master[0].complete_pending = true;
 319                 reset = CCI_RESET_CMD_M0_MASK;
 320         }
 321
 322         if (unlikely(val & CCI_IRQ_STATUS_0_I2C_M1_Q0Q1_HALT_ACK)) {
 323                 cci->master[1].complete_pending = true;
 324                 reset = CCI_RESET_CMD_M1_MASK;
 325         }
 326
 327         if (unlikely(reset))
 328                 writel(reset, cci->base + CCI_RESET_CMD);
 329
 330         if (unlikely(val & CCI_IRQ_STATUS_0_I2C_M0_ERROR)) {
 331                 dev_err_ratelimited(cci->dev, "Master 0 error 0x%08x\n", val);
 332                 cci->master[0].status = -EIO;
 333                 writel(CCI_HALT_REQ_I2C_M0_Q0Q1, cci->base + CCI_HALT_REQ);
 334         }
 335
 336         if (unlikely(val & CCI_IRQ_STATUS_0_I2C_M1_ERROR)) {
 337                 dev_err_ratelimited(cci->dev, "Master 1 error 0x%08x\n", val);
 338                 cci->master[1].status = -EIO;
 339                 writel(CCI_HALT_REQ_I2C_M1_Q0Q1, cci->base + CCI_HALT_REQ);
 340         }
 341
 342         return IRQ_HANDLED;
 343 }
 344
 345 static void cci_halt(struct cci *cci)
 346 {
 347         unsigned long time;
 348         u32 val = CCI_HALT_REQ_I2C_M0_Q0Q1 | CCI_HALT_REQ_I2C_M1_Q0Q1;
 349
 350         cci->master[0].complete_pending = true;
 351         writel(val, cci->base + CCI_HALT_REQ);
 352         time = wait_for_completion_timeout(
 353                                 &cci->master[0].irq_complete,
 354                                 msecs_to_jiffies(CCI_TIMEOUT_MS));
 355         if (!time)
 356                 dev_err(cci->dev, "CCI halt timeout\n");
 357 }
 358
 359 static int cci_reset(struct cci *cci)
 360 {
 361         unsigned long time;
 362
 363         cci->master[0].complete_pending = true;
 364         writel(CCI_RESET_CMD_MASK, cci->base + CCI_RESET_CMD);
 365         time = wait_for_completion_timeout(
 366                                 &cci->master[0].irq_complete,
 367                                 msecs_to_jiffies(CCI_TIMEOUT_MS));
 368         if (!time) {
 369                 dev_err(cci->dev, "CCI reset timeout\n");
 370                 return -ETIMEDOUT;
 371         }
 372
 373         return 0;
 374 }
 375
 376 static int cci_init(struct cci *cci, const struct hw_params *hw)
 377 {
 378         u32 val = CCI_IRQ_MASK_0_I2C_M0_RD_DONE |
 379                         CCI_IRQ_MASK_0_I2C_M0_Q0_REPORT |
 380                         CCI_IRQ_MASK_0_I2C_M0_Q1_REPORT |
 381                         CCI_IRQ_MASK_0_I2C_M1_RD_DONE |
 382                         CCI_IRQ_MASK_0_I2C_M1_Q0_REPORT |
 383                         CCI_IRQ_MASK_0_I2C_M1_Q1_REPORT |
 384                         CCI_IRQ_MASK_0_RST_DONE_ACK |
 385                         CCI_IRQ_MASK_0_I2C_M0_Q0Q1_HALT_ACK |
 386                         CCI_IRQ_MASK_0_I2C_M1_Q0Q1_HALT_ACK |
 387                         CCI_IRQ_MASK_0_I2C_M0_ERROR |
 388                         CCI_IRQ_MASK_0_I2C_M1_ERROR;
 389         int i;
 390
 391         writel(val, cci->base + CCI_IRQ_MASK_0);
 392
 393         for (i = 0; i < NUM_MASTERS; i++) {
 394                 val = hw->thigh << 16 | hw->tlow;
 395                 writel(val, cci->base + CCI_I2C_Mm_SCL_CTL(i));
 396
 397                 val = hw->tsu_sto << 16 | hw->tsu_sta;
 398                 writel(val, cci->base + CCI_I2C_Mm_SDA_CTL_0(i));
 399
 400                 val = hw->thd_dat << 16 | hw->thd_sta;
 401                 writel(val, cci->base + CCI_I2C_Mm_SDA_CTL_1(i));
 402
 403                 val = hw->tbuf;
 404                 writel(val, cci->base + CCI_I2C_Mm_SDA_CTL_2(i));
 405
 406                 val = hw->scl_stretch_en << 8 | hw->trdhld << 4 | hw->tsp;
 407                 writel(val, cci->base + CCI_I2C_Mm_MISC_CTL(i));
 408         }
 409
 410         return 0;
 411 }
 412
 413 static int cci_run_queue(struct cci *cci, u8 master, u8 queue)
 414 {
 415         unsigned long time;
 416         u32 val;
 417         int ret;
 418
 419         val = readl(cci->base + CCI_I2C_Mm_Qn_CUR_WORD_CNT(master, queue));
 420         writel(val, cci->base + CCI_I2C_Mm_Qn_EXEC_WORD_CNT(master, queue));
 421
 422         val = BIT(master * 2 + queue);
 423         writel(val, cci->base + CCI_QUEUE_START);
 424
 425         time = wait_for_completion_timeout(&cci->master[master].irq_complete,
 426                                            CCI_TIMEOUT_MS);
 427         if (!time) {
 428                 dev_err(cci->dev, "master %d queue %d timeout\n",
 429                         master, queue);
 430
 431                 cci_halt(cci);
 432
 433                 return -ETIMEDOUT;
 434         }
 435
 436         ret = cci->master[master].status;
 437         if (ret < 0)
 438                 dev_err(cci->dev, "master %d queue %d error %d\n",
 439                         master, queue, ret);
 440
 441         return ret;
 442 }
 443
 444 static int cci_validate_queue(struct cci *cci, u8 master, u8 queue)
 445 {
 446         int ret = 0;
 447         u32 val;
 448
 449         val = readl(cci->base + CCI_I2C_Mm_Qn_CUR_WORD_CNT(master, queue));
 450
 451         if (val == cci->queue_size[queue])
 452                 return -EINVAL;
 453
 454         if (val) {
 455                 val = CCI_I2C_REPORT | BIT(8);
 456                 writel(val, cci->base + CCI_I2C_Mm_Qn_LOAD_DATA(master, queue));
 457
 458                 ret = cci_run_queue(cci, master, queue);
 459         }
 460
 461         return ret;
 462 }
 463
 464 static int cci_i2c_read(struct cci *cci, u16 addr, u8 *buf, u16 len)
 465 {
 466         u8 master = 0;
 467         u8 queue = QUEUE_1;
 468         u32 val;
 469         u32 words_read, words_exp;
 470         int i, index;
 471         bool first;
 472         int ret;
 473
 474         /*
 475          * Call validate queue to make sure queue is empty before starting.
 476          * This is to avoid overflow / underflow of queue.
 477          */
 478         ret = cci_validate_queue(cci, master, queue);
 479         if (ret < 0)
 480                 return ret;
 481
 482         val = CCI_I2C_SET_PARAM | ((addr >> 1) & 0x7f) << 4;
 483         writel(val, cci->base + CCI_I2C_Mm_Qn_LOAD_DATA(master, queue));
 484
 485         val = CCI_I2C_READ | len << 4;
 486         writel(val, cci->base + CCI_I2C_Mm_Qn_LOAD_DATA(master, queue));
 487
 488         ret = cci_run_queue(cci, master, queue);
 489         if (ret < 0)
 490                 return ret;
 491
 492         words_read = readl(cci->base + CCI_I2C_Mm_READ_BUF_LEVEL(master));
 493         words_exp = len / 4 + 1;
 494         if (words_read != words_exp) {
 495                 dev_err(cci->dev, "words read = %d, words expected = %d\n",
 496                         words_read, words_exp);
 497                 return -EIO;
 498         }
 499
 500         index = 0;
 501         first = true;
 502         do {
 503                 val = readl(cci->base + CCI_I2C_Mm_READ_DATA(master));
 504
 505                 for (i = 0; i < 4 && index < len; i++) {
 506                         if (first) {
 507                                 first = false;
 508                                 continue;
 509                         }
 510                         buf[index++] = (val >> (i * 8)) & 0xff;
 511                 }
 512         } while (--words_read);
 513
 514         return 0;
 515 }
 516
 517 static int cci_i2c_write(struct cci *cci, u16 addr, u8 *buf, u16 len)
 518 {
 519         u8 master = 0;
 520         u8 queue = QUEUE_0;
 521         u8 load[12] = { 0 };
 522         int i, j;
 523         u32 val;
 524         int ret;
 525
 526         /*
 527          * Call validate queue to make sure queue is empty before starting.
 528          * This is to avoid overflow / underflow of queue.
 529          */
 530         ret = cci_validate_queue(cci, master, queue);
 531         if (ret < 0)
 532                 return ret;
 533
 534         val = CCI_I2C_SET_PARAM | ((addr >> 1) & 0x7f) << 4;
 535         writel(val, cci->base + CCI_I2C_Mm_Qn_LOAD_DATA(master, queue));
 536
 537         i = 0;
 538         load[i++] = CCI_I2C_WRITE | len << 4;
 539
 540         for (j = 0; j < len; j++)
 541                 load[i++] = buf[j];
 542
 543         for (j = 0; j < i; j += 4) {
 544                 val = load[j];
 545                 val |= load[j + 1] << 8;
 546                 val |= load[j + 2] << 16;
 547                 val |= load[j + 3] << 24;
 548                 writel(val, cci->base + CCI_I2C_Mm_Qn_LOAD_DATA(master, queue));
 549         }
 550
 551         val = CCI_I2C_REPORT | BIT(8);
 552         writel(val, cci->base + CCI_I2C_Mm_Qn_LOAD_DATA(master, queue));
 553
 554         return cci_run_queue(cci, master, queue);
 555 }
 556
 557 static int cci_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
 558 {
 559         struct cci *cci = i2c_get_adapdata(adap);
 560         int i;
 561         int ret = 0;
 562
 563         for (i = 0; i < num; i++) {
 564                 if (msgs[i].flags & I2C_M_RD)
 565                         ret = cci_i2c_read(cci, msgs[i].addr, msgs[i].buf,
 566                                            msgs[i].len);
 567                 else
 568                         ret = cci_i2c_write(cci, msgs[i].addr, msgs[i].buf,
 569                                             msgs[i].len);
 570
 571                 if (ret < 0) {
 572                         dev_err(cci->dev, "cci i2c xfer error %d", ret);
 573                         break;
 574                 }
 575         }
 576
 577         if (!ret)
 578                 ret = num;
 579
 580         return ret;
 581 }
 582
 583 static u32 cci_func(struct i2c_adapter *adap)
 584 {
 585         return I2C_FUNC_I2C;
 586 }
 587
 588 static const struct i2c_algorithm cci_algo = {
 589         .master_xfer    = cci_xfer,
 590         .functionality  = cci_func,
 591 };
 592
 593 static const struct i2c_adapter_quirks cci_quirks_v1_0_8 = {
 594         .max_write_len = 10,
 595         .max_read_len = 12,
 596 };
 597
 598 static const struct i2c_adapter_quirks cci_quirks_v1_4_0 = {
 599         .max_write_len = 11,
 600         .max_read_len = 12,
 601 };
 602
 603 /**
 604  * cci_probe() - Probe CCI platform device
 605  * @pdev: Pointer to CCI platform device
 606  *
 607  * Return 0 on success or a negative error code on failure
 608  */
 609 static int cci_probe(struct platform_device *pdev)
 610 {
 611         struct device *dev = &pdev->dev;
 612         const struct cci_res *res;
 613         const struct hw_params *hw;
 614         struct cci *cci;
 615         struct resource *r;
 616         int ret = 0;
 617         u8 mode;
 618         u32 val;
 619         int i;
 620
 621         cci = devm_kzalloc(dev, sizeof(*cci), GFP_KERNEL);
 622         if (!cci)
 623                 return -ENOMEM;
 624
 625         cci->dev = dev;
 626         platform_set_drvdata(pdev, cci);
 627
 628         if (of_device_is_compatible(dev->of_node, "qcom,cci-v1.0.8")) {
 629                 res = &res_v1_0_8;
 630                 hw = hw_params_v1_0_8;
 631                 cci->queue_size[0] = queue_0_size_v1_0_8;
 632                 cci->queue_size[1] = queue_1_size_v1_0_8;
 633                 cci->adap.quirks = &cci_quirks_v1_0_8;
 634         } else if (of_device_is_compatible(dev->of_node, "qcom,cci-v1.4.0")) {
 635                 res = &res_v1_4_0;
 636                 hw = hw_params_v1_4_0;
 637                 cci->queue_size[0] = queue_0_size_v1_4_0;
 638                 cci->queue_size[1] = queue_1_size_v1_4_0;
 639                 cci->adap.quirks = &cci_quirks_v1_4_0;
 640         } else {
 641                 return -EINVAL;
 642         }
 643
 644         cci->adap.algo = &cci_algo;
 645         cci->adap.dev.parent = cci->dev;
 646         cci->adap.dev.of_node = dev->of_node;
 647         i2c_set_adapdata(&cci->adap, cci);
 648
 649         strlcpy(cci->adap.name, "Qualcomm Camera Control Interface",
 650                 sizeof(cci->adap.name));
 651
 652         mode = I2C_MODE_STANDARD;
 653         ret = of_property_read_u32(pdev->dev.of_node, "clock-frequency", &val);
 654         if (!ret) {
 655                 if (val == 400000)
 656                         mode = I2C_MODE_FAST;
 657                 else if (val == 1000000)
 658                         mode = I2C_MODE_FAST_PLUS;
 659         }
 660
 661         /* Memory */
 662
 663         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 664         cci->base = devm_ioremap_resource(dev, r);
 665         if (IS_ERR(cci->base)) {
 666                 dev_err(dev, "could not map memory\n");
 667                 return PTR_ERR(cci->base);
 668         }
 669
 670         /* Interrupt */
 671
 672         cci->irq = platform_get_irq(pdev, 0);
 673         if (cci->irq < 0) {
 674                 dev_err(dev, "missing IRQ\n");
 675                 return cci->irq;
 676         }
 677
 678         ret = devm_request_irq(dev, cci->irq, cci_isr,
 679                                IRQF_TRIGGER_RISING, dev_name(dev), cci);
 680         if (ret < 0) {
 681                 dev_err(dev, "request_irq failed, ret: %d\n", ret);
 682                 return ret;
 683         }
 684
 685         disable_irq(cci->irq);
 686
 687         /* Clocks */
 688
 689         cci->nclocks = 0;
 690         while (res->clock[cci->nclocks])
 691                 cci->nclocks++;
 692
 693         cci->clock = devm_kzalloc(dev, cci->nclocks *
 694                                   sizeof(*cci->clock), GFP_KERNEL);
 695         if (!cci->clock)
 696                 return -ENOMEM;
 697
 698         cci->clock_freq = devm_kzalloc(dev, cci->nclocks *
 699                                        sizeof(*cci->clock_freq), GFP_KERNEL);
 700         if (!cci->clock_freq)
 701                 return -ENOMEM;
 702
 703         for (i = 0; i < cci->nclocks; i++) {
 704                 struct clk_bulk_data *clock = &cci->clock[i];
 705
 706                 clock->clk = devm_clk_get(dev, res->clock[i]);
 707                 if (IS_ERR(clock->clk))
 708                         return PTR_ERR(clock->clk);
 709
 710                 clock->id = res->clock[i];
 711                 cci->clock_freq[i] = res->clock_rate[i];
 712         }
 713
 714         ret = cci_clock_set_rate(cci->nclocks, cci->clock,
 715                                  cci->clock_freq, dev);
 716         if (ret < 0)
 717                 return ret;
 718
 719         ret = clk_bulk_prepare_enable(cci->nclocks, cci->clock);
 720         if (ret < 0)
 721                 return ret;
 722
 723         val = readl_relaxed(cci->base + CCI_HW_VERSION);
 724         dev_dbg(dev, "%s: CCI HW version = 0x%08x", __func__, val);
 725
 726         init_completion(&cci->master[0].irq_complete);
 727         init_completion(&cci->master[1].irq_complete);
 728
 729         enable_irq(cci->irq);
 730
 731         ret = cci_reset(cci);
 732         if (ret < 0)
 733                 goto error;
 734
 735         ret = cci_init(cci, &hw[mode]);
 736         if (ret < 0)
 737                 goto error;
 738
 739         ret = i2c_add_adapter(&cci->adap);
 740         if (ret < 0)
 741                 goto error;
 742
 743         return 0;
 744
 745 error:
 746         clk_bulk_disable_unprepare(cci->nclocks, cci->clock);
 747
 748         return ret;
 749 }
 750
 751 /**
 752  * cci_remove() - Remove CCI platform device
 753  * @pdev: Pointer to CCI platform device
 754  *
 755  * Always returns 0.
 756  */
 757 static int cci_remove(struct platform_device *pdev)
 758 {
 759         struct cci *cci = platform_get_drvdata(pdev);
 760
 761         disable_irq(cci->irq);
 762         clk_bulk_disable_unprepare(cci->nclocks, cci->clock);
 763
 764         i2c_del_adapter(&cci->adap);
 765
 766         return 0;
 767 }
 768
 769 static const struct of_device_id cci_dt_match[] = {
 770         { .compatible = "qcom,cci-v1.0.8" },
 771         { .compatible = "qcom,cci-v1.4.0" },
 772         {}
 773 };
 774 MODULE_DEVICE_TABLE(of, cci_dt_match);
 775
 776 static struct platform_driver qcom_cci_driver = {
 777         .probe  = cci_probe,
 778         .remove = cci_remove,
 779         .driver = {
 780                 .name = "i2c-qcom-cci",
 781                 .of_match_table = cci_dt_match,
 782         },
 783 };
 784
 785 module_platform_driver(qcom_cci_driver);
 786
 787 MODULE_DESCRIPTION("Qualcomm Camera Control Interface driver");
 788 MODULE_AUTHOR("Todor Tomov <todor.tomov@linaro.org>");
 789 MODULE_LICENSE("GPL v2");