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Merge branch 'acpica-fixes'
[mirror_ubuntu-eoan-kernel.git] / drivers / i2c / busses / i2c-qup.c
1 /*
2 * Copyright (c) 2009-2013, The Linux Foundation. All rights reserved.
3 * Copyright (c) 2014, Sony Mobile Communications AB.
4 *
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 and
8 * only version 2 as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 */
16
17 #include <linux/atomic.h>
18 #include <linux/clk.h>
19 #include <linux/delay.h>
20 #include <linux/dmaengine.h>
21 #include <linux/dmapool.h>
22 #include <linux/dma-mapping.h>
23 #include <linux/err.h>
24 #include <linux/i2c.h>
25 #include <linux/interrupt.h>
26 #include <linux/io.h>
27 #include <linux/module.h>
28 #include <linux/of.h>
29 #include <linux/platform_device.h>
30 #include <linux/pm_runtime.h>
31 #include <linux/scatterlist.h>
32
33 /* QUP Registers */
34 #define QUP_CONFIG 0x000
35 #define QUP_STATE 0x004
36 #define QUP_IO_MODE 0x008
37 #define QUP_SW_RESET 0x00c
38 #define QUP_OPERATIONAL 0x018
39 #define QUP_ERROR_FLAGS 0x01c
40 #define QUP_ERROR_FLAGS_EN 0x020
41 #define QUP_OPERATIONAL_MASK 0x028
42 #define QUP_HW_VERSION 0x030
43 #define QUP_MX_OUTPUT_CNT 0x100
44 #define QUP_OUT_FIFO_BASE 0x110
45 #define QUP_MX_WRITE_CNT 0x150
46 #define QUP_MX_INPUT_CNT 0x200
47 #define QUP_MX_READ_CNT 0x208
48 #define QUP_IN_FIFO_BASE 0x218
49 #define QUP_I2C_CLK_CTL 0x400
50 #define QUP_I2C_STATUS 0x404
51 #define QUP_I2C_MASTER_GEN 0x408
52
53 /* QUP States and reset values */
54 #define QUP_RESET_STATE 0
55 #define QUP_RUN_STATE 1
56 #define QUP_PAUSE_STATE 3
57 #define QUP_STATE_MASK 3
58
59 #define QUP_STATE_VALID BIT(2)
60 #define QUP_I2C_MAST_GEN BIT(4)
61 #define QUP_I2C_FLUSH BIT(6)
62
63 #define QUP_OPERATIONAL_RESET 0x000ff0
64 #define QUP_I2C_STATUS_RESET 0xfffffc
65
66 /* QUP OPERATIONAL FLAGS */
67 #define QUP_I2C_NACK_FLAG BIT(3)
68 #define QUP_OUT_NOT_EMPTY BIT(4)
69 #define QUP_IN_NOT_EMPTY BIT(5)
70 #define QUP_OUT_FULL BIT(6)
71 #define QUP_OUT_SVC_FLAG BIT(8)
72 #define QUP_IN_SVC_FLAG BIT(9)
73 #define QUP_MX_OUTPUT_DONE BIT(10)
74 #define QUP_MX_INPUT_DONE BIT(11)
75
76 /* I2C mini core related values */
77 #define QUP_CLOCK_AUTO_GATE BIT(13)
78 #define I2C_MINI_CORE (2 << 8)
79 #define I2C_N_VAL 15
80 #define I2C_N_VAL_V2 7
81
82 /* Most significant word offset in FIFO port */
83 #define QUP_MSW_SHIFT (I2C_N_VAL + 1)
84
85 /* Packing/Unpacking words in FIFOs, and IO modes */
86 #define QUP_OUTPUT_BLK_MODE (1 << 10)
87 #define QUP_OUTPUT_BAM_MODE (3 << 10)
88 #define QUP_INPUT_BLK_MODE (1 << 12)
89 #define QUP_INPUT_BAM_MODE (3 << 12)
90 #define QUP_BAM_MODE (QUP_OUTPUT_BAM_MODE | QUP_INPUT_BAM_MODE)
91 #define QUP_UNPACK_EN BIT(14)
92 #define QUP_PACK_EN BIT(15)
93
94 #define QUP_REPACK_EN (QUP_UNPACK_EN | QUP_PACK_EN)
95 #define QUP_V2_TAGS_EN 1
96
97 #define QUP_OUTPUT_BLOCK_SIZE(x)(((x) >> 0) & 0x03)
98 #define QUP_OUTPUT_FIFO_SIZE(x) (((x) >> 2) & 0x07)
99 #define QUP_INPUT_BLOCK_SIZE(x) (((x) >> 5) & 0x03)
100 #define QUP_INPUT_FIFO_SIZE(x) (((x) >> 7) & 0x07)
101
102 /* QUP tags */
103 #define QUP_TAG_START (1 << 8)
104 #define QUP_TAG_DATA (2 << 8)
105 #define QUP_TAG_STOP (3 << 8)
106 #define QUP_TAG_REC (4 << 8)
107 #define QUP_BAM_INPUT_EOT 0x93
108 #define QUP_BAM_FLUSH_STOP 0x96
109
110 /* QUP v2 tags */
111 #define QUP_TAG_V2_START 0x81
112 #define QUP_TAG_V2_DATAWR 0x82
113 #define QUP_TAG_V2_DATAWR_STOP 0x83
114 #define QUP_TAG_V2_DATARD 0x85
115 #define QUP_TAG_V2_DATARD_STOP 0x87
116
117 /* Status, Error flags */
118 #define I2C_STATUS_WR_BUFFER_FULL BIT(0)
119 #define I2C_STATUS_BUS_ACTIVE BIT(8)
120 #define I2C_STATUS_ERROR_MASK 0x38000fc
121 #define QUP_STATUS_ERROR_FLAGS 0x7c
122
123 #define QUP_READ_LIMIT 256
124 #define SET_BIT 0x1
125 #define RESET_BIT 0x0
126 #define ONE_BYTE 0x1
127 #define QUP_I2C_MX_CONFIG_DURING_RUN BIT(31)
128
129 #define MX_TX_RX_LEN SZ_64K
130 #define MX_BLOCKS (MX_TX_RX_LEN / QUP_READ_LIMIT)
131
132 /* Max timeout in ms for 32k bytes */
133 #define TOUT_MAX 300
134
135 struct qup_i2c_block {
136 int count;
137 int pos;
138 int tx_tag_len;
139 int rx_tag_len;
140 int data_len;
141 u8 tags[6];
142 };
143
144 struct qup_i2c_tag {
145 u8 *start;
146 dma_addr_t addr;
147 };
148
149 struct qup_i2c_bam {
150 struct qup_i2c_tag tag;
151 struct dma_chan *dma;
152 struct scatterlist *sg;
153 };
154
155 struct qup_i2c_dev {
156 struct device *dev;
157 void __iomem *base;
158 int irq;
159 struct clk *clk;
160 struct clk *pclk;
161 struct i2c_adapter adap;
162
163 int clk_ctl;
164 int out_fifo_sz;
165 int in_fifo_sz;
166 int out_blk_sz;
167 int in_blk_sz;
168
169 unsigned long one_byte_t;
170 struct qup_i2c_block blk;
171
172 struct i2c_msg *msg;
173 /* Current posion in user message buffer */
174 int pos;
175 /* I2C protocol errors */
176 u32 bus_err;
177 /* QUP core errors */
178 u32 qup_err;
179
180 /* To check if this is the last msg */
181 bool is_last;
182
183 /* To configure when bus is in run state */
184 int config_run;
185
186 /* dma parameters */
187 bool is_dma;
188 struct dma_pool *dpool;
189 struct qup_i2c_tag start_tag;
190 struct qup_i2c_bam brx;
191 struct qup_i2c_bam btx;
192
193 struct completion xfer;
194 };
195
196 static irqreturn_t qup_i2c_interrupt(int irq, void *dev)
197 {
198 struct qup_i2c_dev *qup = dev;
199 u32 bus_err;
200 u32 qup_err;
201 u32 opflags;
202
203 bus_err = readl(qup->base + QUP_I2C_STATUS);
204 qup_err = readl(qup->base + QUP_ERROR_FLAGS);
205 opflags = readl(qup->base + QUP_OPERATIONAL);
206
207 if (!qup->msg) {
208 /* Clear Error interrupt */
209 writel(QUP_RESET_STATE, qup->base + QUP_STATE);
210 return IRQ_HANDLED;
211 }
212
213 bus_err &= I2C_STATUS_ERROR_MASK;
214 qup_err &= QUP_STATUS_ERROR_FLAGS;
215
216 if (qup_err) {
217 /* Clear Error interrupt */
218 writel(qup_err, qup->base + QUP_ERROR_FLAGS);
219 goto done;
220 }
221
222 if (bus_err) {
223 /* Clear Error interrupt */
224 writel(QUP_RESET_STATE, qup->base + QUP_STATE);
225 goto done;
226 }
227
228 if (opflags & QUP_IN_SVC_FLAG)
229 writel(QUP_IN_SVC_FLAG, qup->base + QUP_OPERATIONAL);
230
231 if (opflags & QUP_OUT_SVC_FLAG)
232 writel(QUP_OUT_SVC_FLAG, qup->base + QUP_OPERATIONAL);
233
234 done:
235 qup->qup_err = qup_err;
236 qup->bus_err = bus_err;
237 complete(&qup->xfer);
238 return IRQ_HANDLED;
239 }
240
241 static int qup_i2c_poll_state_mask(struct qup_i2c_dev *qup,
242 u32 req_state, u32 req_mask)
243 {
244 int retries = 1;
245 u32 state;
246
247 /*
248 * State transition takes 3 AHB clocks cycles + 3 I2C master clock
249 * cycles. So retry once after a 1uS delay.
250 */
251 do {
252 state = readl(qup->base + QUP_STATE);
253
254 if (state & QUP_STATE_VALID &&
255 (state & req_mask) == req_state)
256 return 0;
257
258 udelay(1);
259 } while (retries--);
260
261 return -ETIMEDOUT;
262 }
263
264 static int qup_i2c_poll_state(struct qup_i2c_dev *qup, u32 req_state)
265 {
266 return qup_i2c_poll_state_mask(qup, req_state, QUP_STATE_MASK);
267 }
268
269 static void qup_i2c_flush(struct qup_i2c_dev *qup)
270 {
271 u32 val = readl(qup->base + QUP_STATE);
272
273 val |= QUP_I2C_FLUSH;
274 writel(val, qup->base + QUP_STATE);
275 }
276
277 static int qup_i2c_poll_state_valid(struct qup_i2c_dev *qup)
278 {
279 return qup_i2c_poll_state_mask(qup, 0, 0);
280 }
281
282 static int qup_i2c_poll_state_i2c_master(struct qup_i2c_dev *qup)
283 {
284 return qup_i2c_poll_state_mask(qup, QUP_I2C_MAST_GEN, QUP_I2C_MAST_GEN);
285 }
286
287 static int qup_i2c_change_state(struct qup_i2c_dev *qup, u32 state)
288 {
289 if (qup_i2c_poll_state_valid(qup) != 0)
290 return -EIO;
291
292 writel(state, qup->base + QUP_STATE);
293
294 if (qup_i2c_poll_state(qup, state) != 0)
295 return -EIO;
296 return 0;
297 }
298
299 /**
300 * qup_i2c_wait_ready - wait for a give number of bytes in tx/rx path
301 * @qup: The qup_i2c_dev device
302 * @op: The bit/event to wait on
303 * @val: value of the bit to wait on, 0 or 1
304 * @len: The length the bytes to be transferred
305 */
306 static int qup_i2c_wait_ready(struct qup_i2c_dev *qup, int op, bool val,
307 int len)
308 {
309 unsigned long timeout;
310 u32 opflags;
311 u32 status;
312 u32 shift = __ffs(op);
313
314 len *= qup->one_byte_t;
315 /* timeout after a wait of twice the max time */
316 timeout = jiffies + len * 4;
317
318 for (;;) {
319 opflags = readl(qup->base + QUP_OPERATIONAL);
320 status = readl(qup->base + QUP_I2C_STATUS);
321
322 if (((opflags & op) >> shift) == val) {
323 if ((op == QUP_OUT_NOT_EMPTY) && qup->is_last) {
324 if (!(status & I2C_STATUS_BUS_ACTIVE))
325 return 0;
326 } else {
327 return 0;
328 }
329 }
330
331 if (time_after(jiffies, timeout))
332 return -ETIMEDOUT;
333
334 usleep_range(len, len * 2);
335 }
336 }
337
338 static void qup_i2c_set_write_mode_v2(struct qup_i2c_dev *qup,
339 struct i2c_msg *msg)
340 {
341 /* Number of entries to shift out, including the tags */
342 int total = msg->len + qup->blk.tx_tag_len;
343
344 total |= qup->config_run;
345
346 if (total < qup->out_fifo_sz) {
347 /* FIFO mode */
348 writel(QUP_REPACK_EN, qup->base + QUP_IO_MODE);
349 writel(total, qup->base + QUP_MX_WRITE_CNT);
350 } else {
351 /* BLOCK mode (transfer data on chunks) */
352 writel(QUP_OUTPUT_BLK_MODE | QUP_REPACK_EN,
353 qup->base + QUP_IO_MODE);
354 writel(total, qup->base + QUP_MX_OUTPUT_CNT);
355 }
356 }
357
358 static void qup_i2c_set_write_mode(struct qup_i2c_dev *qup, struct i2c_msg *msg)
359 {
360 /* Number of entries to shift out, including the start */
361 int total = msg->len + 1;
362
363 if (total < qup->out_fifo_sz) {
364 /* FIFO mode */
365 writel(QUP_REPACK_EN, qup->base + QUP_IO_MODE);
366 writel(total, qup->base + QUP_MX_WRITE_CNT);
367 } else {
368 /* BLOCK mode (transfer data on chunks) */
369 writel(QUP_OUTPUT_BLK_MODE | QUP_REPACK_EN,
370 qup->base + QUP_IO_MODE);
371 writel(total, qup->base + QUP_MX_OUTPUT_CNT);
372 }
373 }
374
375 static int check_for_fifo_space(struct qup_i2c_dev *qup)
376 {
377 int ret;
378
379 ret = qup_i2c_change_state(qup, QUP_PAUSE_STATE);
380 if (ret)
381 goto out;
382
383 ret = qup_i2c_wait_ready(qup, QUP_OUT_FULL,
384 RESET_BIT, 4 * ONE_BYTE);
385 if (ret) {
386 /* Fifo is full. Drain out the fifo */
387 ret = qup_i2c_change_state(qup, QUP_RUN_STATE);
388 if (ret)
389 goto out;
390
391 ret = qup_i2c_wait_ready(qup, QUP_OUT_NOT_EMPTY,
392 RESET_BIT, 256 * ONE_BYTE);
393 if (ret) {
394 dev_err(qup->dev, "timeout for fifo out full");
395 goto out;
396 }
397
398 ret = qup_i2c_change_state(qup, QUP_PAUSE_STATE);
399 if (ret)
400 goto out;
401 }
402
403 out:
404 return ret;
405 }
406
407 static int qup_i2c_issue_write(struct qup_i2c_dev *qup, struct i2c_msg *msg)
408 {
409 u32 addr = msg->addr << 1;
410 u32 qup_tag;
411 int idx;
412 u32 val;
413 int ret = 0;
414
415 if (qup->pos == 0) {
416 val = QUP_TAG_START | addr;
417 idx = 1;
418 } else {
419 val = 0;
420 idx = 0;
421 }
422
423 while (qup->pos < msg->len) {
424 /* Check that there's space in the FIFO for our pair */
425 ret = check_for_fifo_space(qup);
426 if (ret)
427 return ret;
428
429 if (qup->pos == msg->len - 1)
430 qup_tag = QUP_TAG_STOP;
431 else
432 qup_tag = QUP_TAG_DATA;
433
434 if (idx & 1)
435 val |= (qup_tag | msg->buf[qup->pos]) << QUP_MSW_SHIFT;
436 else
437 val = qup_tag | msg->buf[qup->pos];
438
439 /* Write out the pair and the last odd value */
440 if (idx & 1 || qup->pos == msg->len - 1)
441 writel(val, qup->base + QUP_OUT_FIFO_BASE);
442
443 qup->pos++;
444 idx++;
445 }
446
447 ret = qup_i2c_change_state(qup, QUP_RUN_STATE);
448
449 return ret;
450 }
451
452 static void qup_i2c_set_blk_data(struct qup_i2c_dev *qup,
453 struct i2c_msg *msg)
454 {
455 memset(&qup->blk, 0, sizeof(qup->blk));
456
457 qup->blk.data_len = msg->len;
458 qup->blk.count = (msg->len + QUP_READ_LIMIT - 1) / QUP_READ_LIMIT;
459
460 /* 4 bytes for first block and 2 writes for rest */
461 qup->blk.tx_tag_len = 4 + (qup->blk.count - 1) * 2;
462
463 /* There are 2 tag bytes that are read in to fifo for every block */
464 if (msg->flags & I2C_M_RD)
465 qup->blk.rx_tag_len = qup->blk.count * 2;
466 }
467
468 static int qup_i2c_send_data(struct qup_i2c_dev *qup, int tlen, u8 *tbuf,
469 int dlen, u8 *dbuf)
470 {
471 u32 val = 0, idx = 0, pos = 0, i = 0, t;
472 int len = tlen + dlen;
473 u8 *buf = tbuf;
474 int ret = 0;
475
476 while (len > 0) {
477 ret = check_for_fifo_space(qup);
478 if (ret)
479 return ret;
480
481 t = (len >= 4) ? 4 : len;
482
483 while (idx < t) {
484 if (!i && (pos >= tlen)) {
485 buf = dbuf;
486 pos = 0;
487 i = 1;
488 }
489 val |= buf[pos++] << (idx++ * 8);
490 }
491
492 writel(val, qup->base + QUP_OUT_FIFO_BASE);
493 idx = 0;
494 val = 0;
495 len -= 4;
496 }
497
498 ret = qup_i2c_change_state(qup, QUP_RUN_STATE);
499
500 return ret;
501 }
502
503 static int qup_i2c_get_data_len(struct qup_i2c_dev *qup)
504 {
505 int data_len;
506
507 if (qup->blk.data_len > QUP_READ_LIMIT)
508 data_len = QUP_READ_LIMIT;
509 else
510 data_len = qup->blk.data_len;
511
512 return data_len;
513 }
514
515 static int qup_i2c_set_tags(u8 *tags, struct qup_i2c_dev *qup,
516 struct i2c_msg *msg, int is_dma)
517 {
518 u16 addr = i2c_8bit_addr_from_msg(msg);
519 int len = 0;
520 int data_len;
521
522 int last = (qup->blk.pos == (qup->blk.count - 1)) && (qup->is_last);
523
524 if (qup->blk.pos == 0) {
525 tags[len++] = QUP_TAG_V2_START;
526 tags[len++] = addr & 0xff;
527
528 if (msg->flags & I2C_M_TEN)
529 tags[len++] = addr >> 8;
530 }
531
532 /* Send _STOP commands for the last block */
533 if (last) {
534 if (msg->flags & I2C_M_RD)
535 tags[len++] = QUP_TAG_V2_DATARD_STOP;
536 else
537 tags[len++] = QUP_TAG_V2_DATAWR_STOP;
538 } else {
539 if (msg->flags & I2C_M_RD)
540 tags[len++] = QUP_TAG_V2_DATARD;
541 else
542 tags[len++] = QUP_TAG_V2_DATAWR;
543 }
544
545 data_len = qup_i2c_get_data_len(qup);
546
547 /* 0 implies 256 bytes */
548 if (data_len == QUP_READ_LIMIT)
549 tags[len++] = 0;
550 else
551 tags[len++] = data_len;
552
553 if ((msg->flags & I2C_M_RD) && last && is_dma) {
554 tags[len++] = QUP_BAM_INPUT_EOT;
555 tags[len++] = QUP_BAM_FLUSH_STOP;
556 }
557
558 return len;
559 }
560
561 static int qup_i2c_issue_xfer_v2(struct qup_i2c_dev *qup, struct i2c_msg *msg)
562 {
563 int data_len = 0, tag_len, index;
564 int ret;
565
566 tag_len = qup_i2c_set_tags(qup->blk.tags, qup, msg, 0);
567 index = msg->len - qup->blk.data_len;
568
569 /* only tags are written for read */
570 if (!(msg->flags & I2C_M_RD))
571 data_len = qup_i2c_get_data_len(qup);
572
573 ret = qup_i2c_send_data(qup, tag_len, qup->blk.tags,
574 data_len, &msg->buf[index]);
575 qup->blk.data_len -= data_len;
576
577 return ret;
578 }
579
580 static void qup_i2c_bam_cb(void *data)
581 {
582 struct qup_i2c_dev *qup = data;
583
584 complete(&qup->xfer);
585 }
586
587 static int qup_sg_set_buf(struct scatterlist *sg, void *buf,
588 struct qup_i2c_tag *tg, unsigned int buflen,
589 struct qup_i2c_dev *qup, int map, int dir)
590 {
591 int ret;
592
593 sg_set_buf(sg, buf, buflen);
594 ret = dma_map_sg(qup->dev, sg, 1, dir);
595 if (!ret)
596 return -EINVAL;
597
598 if (!map)
599 sg_dma_address(sg) = tg->addr + ((u8 *)buf - tg->start);
600
601 return 0;
602 }
603
604 static void qup_i2c_rel_dma(struct qup_i2c_dev *qup)
605 {
606 if (qup->btx.dma)
607 dma_release_channel(qup->btx.dma);
608 if (qup->brx.dma)
609 dma_release_channel(qup->brx.dma);
610 qup->btx.dma = NULL;
611 qup->brx.dma = NULL;
612 }
613
614 static int qup_i2c_req_dma(struct qup_i2c_dev *qup)
615 {
616 int err;
617
618 if (!qup->btx.dma) {
619 qup->btx.dma = dma_request_slave_channel_reason(qup->dev, "tx");
620 if (IS_ERR(qup->btx.dma)) {
621 err = PTR_ERR(qup->btx.dma);
622 qup->btx.dma = NULL;
623 dev_err(qup->dev, "\n tx channel not available");
624 return err;
625 }
626 }
627
628 if (!qup->brx.dma) {
629 qup->brx.dma = dma_request_slave_channel_reason(qup->dev, "rx");
630 if (IS_ERR(qup->brx.dma)) {
631 dev_err(qup->dev, "\n rx channel not available");
632 err = PTR_ERR(qup->brx.dma);
633 qup->brx.dma = NULL;
634 qup_i2c_rel_dma(qup);
635 return err;
636 }
637 }
638 return 0;
639 }
640
641 static int qup_i2c_bam_do_xfer(struct qup_i2c_dev *qup, struct i2c_msg *msg,
642 int num)
643 {
644 struct dma_async_tx_descriptor *txd, *rxd = NULL;
645 int ret = 0, idx = 0, limit = QUP_READ_LIMIT;
646 dma_cookie_t cookie_rx, cookie_tx;
647 u32 rx_nents = 0, tx_nents = 0, len, blocks, rem;
648 u32 i, tlen, tx_len, tx_buf = 0, rx_buf = 0, off = 0;
649 u8 *tags;
650
651 while (idx < num) {
652 blocks = (msg->len + limit) / limit;
653 rem = msg->len % limit;
654 tx_len = 0, len = 0, i = 0;
655
656 qup->is_last = (idx == (num - 1));
657
658 qup_i2c_set_blk_data(qup, msg);
659
660 if (msg->flags & I2C_M_RD) {
661 rx_nents += (blocks * 2) + 1;
662 tx_nents += 1;
663
664 while (qup->blk.pos < blocks) {
665 /* length set to '0' implies 256 bytes */
666 tlen = (i == (blocks - 1)) ? rem : 0;
667 tags = &qup->start_tag.start[off + len];
668 len += qup_i2c_set_tags(tags, qup, msg, 1);
669
670 /* scratch buf to read the start and len tags */
671 ret = qup_sg_set_buf(&qup->brx.sg[rx_buf++],
672 &qup->brx.tag.start[0],
673 &qup->brx.tag,
674 2, qup, 0, 0);
675
676 if (ret)
677 return ret;
678
679 ret = qup_sg_set_buf(&qup->brx.sg[rx_buf++],
680 &msg->buf[limit * i],
681 NULL, tlen, qup,
682 1, DMA_FROM_DEVICE);
683 if (ret)
684 return ret;
685
686 i++;
687 qup->blk.pos = i;
688 }
689 ret = qup_sg_set_buf(&qup->btx.sg[tx_buf++],
690 &qup->start_tag.start[off],
691 &qup->start_tag, len, qup, 0, 0);
692 if (ret)
693 return ret;
694
695 off += len;
696 /* scratch buf to read the BAM EOT and FLUSH tags */
697 ret = qup_sg_set_buf(&qup->brx.sg[rx_buf++],
698 &qup->brx.tag.start[0],
699 &qup->brx.tag, 2,
700 qup, 0, 0);
701 if (ret)
702 return ret;
703 } else {
704 tx_nents += (blocks * 2);
705
706 while (qup->blk.pos < blocks) {
707 tlen = (i == (blocks - 1)) ? rem : 0;
708 tags = &qup->start_tag.start[off + tx_len];
709 len = qup_i2c_set_tags(tags, qup, msg, 1);
710
711 ret = qup_sg_set_buf(&qup->btx.sg[tx_buf++],
712 tags,
713 &qup->start_tag, len,
714 qup, 0, 0);
715 if (ret)
716 return ret;
717
718 tx_len += len;
719 ret = qup_sg_set_buf(&qup->btx.sg[tx_buf++],
720 &msg->buf[limit * i],
721 NULL, tlen, qup, 1,
722 DMA_TO_DEVICE);
723 if (ret)
724 return ret;
725 i++;
726 qup->blk.pos = i;
727 }
728 off += tx_len;
729
730 if (idx == (num - 1)) {
731 len = 1;
732 if (rx_nents) {
733 qup->btx.tag.start[0] =
734 QUP_BAM_INPUT_EOT;
735 len++;
736 }
737 qup->btx.tag.start[len - 1] =
738 QUP_BAM_FLUSH_STOP;
739 ret = qup_sg_set_buf(&qup->btx.sg[tx_buf++],
740 &qup->btx.tag.start[0],
741 &qup->btx.tag, len,
742 qup, 0, 0);
743 if (ret)
744 return ret;
745 tx_nents += 1;
746 }
747 }
748 idx++;
749 msg++;
750 }
751
752 txd = dmaengine_prep_slave_sg(qup->btx.dma, qup->btx.sg, tx_nents,
753 DMA_MEM_TO_DEV,
754 DMA_PREP_INTERRUPT | DMA_PREP_FENCE);
755 if (!txd) {
756 dev_err(qup->dev, "failed to get tx desc\n");
757 ret = -EINVAL;
758 goto desc_err;
759 }
760
761 if (!rx_nents) {
762 txd->callback = qup_i2c_bam_cb;
763 txd->callback_param = qup;
764 }
765
766 cookie_tx = dmaengine_submit(txd);
767 if (dma_submit_error(cookie_tx)) {
768 ret = -EINVAL;
769 goto desc_err;
770 }
771
772 dma_async_issue_pending(qup->btx.dma);
773
774 if (rx_nents) {
775 rxd = dmaengine_prep_slave_sg(qup->brx.dma, qup->brx.sg,
776 rx_nents, DMA_DEV_TO_MEM,
777 DMA_PREP_INTERRUPT);
778 if (!rxd) {
779 dev_err(qup->dev, "failed to get rx desc\n");
780 ret = -EINVAL;
781
782 /* abort TX descriptors */
783 dmaengine_terminate_all(qup->btx.dma);
784 goto desc_err;
785 }
786
787 rxd->callback = qup_i2c_bam_cb;
788 rxd->callback_param = qup;
789 cookie_rx = dmaengine_submit(rxd);
790 if (dma_submit_error(cookie_rx)) {
791 ret = -EINVAL;
792 goto desc_err;
793 }
794
795 dma_async_issue_pending(qup->brx.dma);
796 }
797
798 if (!wait_for_completion_timeout(&qup->xfer, TOUT_MAX * HZ)) {
799 dev_err(qup->dev, "normal trans timed out\n");
800 ret = -ETIMEDOUT;
801 }
802
803 if (ret || qup->bus_err || qup->qup_err) {
804 if (qup->bus_err & QUP_I2C_NACK_FLAG) {
805 msg--;
806 dev_err(qup->dev, "NACK from %x\n", msg->addr);
807 ret = -EIO;
808
809 if (qup_i2c_change_state(qup, QUP_RUN_STATE)) {
810 dev_err(qup->dev, "change to run state timed out");
811 return ret;
812 }
813
814 if (rx_nents)
815 writel(QUP_BAM_INPUT_EOT,
816 qup->base + QUP_OUT_FIFO_BASE);
817
818 writel(QUP_BAM_FLUSH_STOP,
819 qup->base + QUP_OUT_FIFO_BASE);
820
821 qup_i2c_flush(qup);
822
823 /* wait for remaining interrupts to occur */
824 if (!wait_for_completion_timeout(&qup->xfer, HZ))
825 dev_err(qup->dev, "flush timed out\n");
826
827 qup_i2c_rel_dma(qup);
828 }
829 }
830
831 dma_unmap_sg(qup->dev, qup->btx.sg, tx_nents, DMA_TO_DEVICE);
832
833 if (rx_nents)
834 dma_unmap_sg(qup->dev, qup->brx.sg, rx_nents,
835 DMA_FROM_DEVICE);
836 desc_err:
837 return ret;
838 }
839
840 static int qup_i2c_bam_xfer(struct i2c_adapter *adap, struct i2c_msg *msg,
841 int num)
842 {
843 struct qup_i2c_dev *qup = i2c_get_adapdata(adap);
844 int ret = 0;
845
846 enable_irq(qup->irq);
847 ret = qup_i2c_req_dma(qup);
848
849 if (ret)
850 goto out;
851
852 qup->bus_err = 0;
853 qup->qup_err = 0;
854
855 writel(0, qup->base + QUP_MX_INPUT_CNT);
856 writel(0, qup->base + QUP_MX_OUTPUT_CNT);
857
858 /* set BAM mode */
859 writel(QUP_REPACK_EN | QUP_BAM_MODE, qup->base + QUP_IO_MODE);
860
861 /* mask fifo irqs */
862 writel((0x3 << 8), qup->base + QUP_OPERATIONAL_MASK);
863
864 /* set RUN STATE */
865 ret = qup_i2c_change_state(qup, QUP_RUN_STATE);
866 if (ret)
867 goto out;
868
869 writel(qup->clk_ctl, qup->base + QUP_I2C_CLK_CTL);
870
871 qup->msg = msg;
872 ret = qup_i2c_bam_do_xfer(qup, qup->msg, num);
873 out:
874 disable_irq(qup->irq);
875
876 qup->msg = NULL;
877 return ret;
878 }
879
880 static int qup_i2c_wait_for_complete(struct qup_i2c_dev *qup,
881 struct i2c_msg *msg)
882 {
883 unsigned long left;
884 int ret = 0;
885
886 left = wait_for_completion_timeout(&qup->xfer, HZ);
887 if (!left) {
888 writel(1, qup->base + QUP_SW_RESET);
889 ret = -ETIMEDOUT;
890 }
891
892 if (qup->bus_err || qup->qup_err) {
893 if (qup->bus_err & QUP_I2C_NACK_FLAG) {
894 dev_err(qup->dev, "NACK from %x\n", msg->addr);
895 ret = -EIO;
896 }
897 }
898
899 return ret;
900 }
901
902 static int qup_i2c_write_one_v2(struct qup_i2c_dev *qup, struct i2c_msg *msg)
903 {
904 int ret = 0;
905
906 qup->msg = msg;
907 qup->pos = 0;
908 enable_irq(qup->irq);
909 qup_i2c_set_blk_data(qup, msg);
910 qup_i2c_set_write_mode_v2(qup, msg);
911
912 ret = qup_i2c_change_state(qup, QUP_RUN_STATE);
913 if (ret)
914 goto err;
915
916 writel(qup->clk_ctl, qup->base + QUP_I2C_CLK_CTL);
917
918 do {
919 ret = qup_i2c_issue_xfer_v2(qup, msg);
920 if (ret)
921 goto err;
922
923 ret = qup_i2c_wait_for_complete(qup, msg);
924 if (ret)
925 goto err;
926
927 qup->blk.pos++;
928 } while (qup->blk.pos < qup->blk.count);
929
930 ret = qup_i2c_wait_ready(qup, QUP_OUT_NOT_EMPTY, RESET_BIT, ONE_BYTE);
931
932 err:
933 disable_irq(qup->irq);
934 qup->msg = NULL;
935
936 return ret;
937 }
938
939 static int qup_i2c_write_one(struct qup_i2c_dev *qup, struct i2c_msg *msg)
940 {
941 int ret;
942
943 qup->msg = msg;
944 qup->pos = 0;
945
946 enable_irq(qup->irq);
947
948 qup_i2c_set_write_mode(qup, msg);
949
950 ret = qup_i2c_change_state(qup, QUP_RUN_STATE);
951 if (ret)
952 goto err;
953
954 writel(qup->clk_ctl, qup->base + QUP_I2C_CLK_CTL);
955
956 do {
957 ret = qup_i2c_change_state(qup, QUP_PAUSE_STATE);
958 if (ret)
959 goto err;
960
961 ret = qup_i2c_issue_write(qup, msg);
962 if (ret)
963 goto err;
964
965 ret = qup_i2c_change_state(qup, QUP_RUN_STATE);
966 if (ret)
967 goto err;
968
969 ret = qup_i2c_wait_for_complete(qup, msg);
970 if (ret)
971 goto err;
972 } while (qup->pos < msg->len);
973
974 /* Wait for the outstanding data in the fifo to drain */
975 ret = qup_i2c_wait_ready(qup, QUP_OUT_NOT_EMPTY, RESET_BIT, ONE_BYTE);
976 err:
977 disable_irq(qup->irq);
978 qup->msg = NULL;
979
980 return ret;
981 }
982
983 static void qup_i2c_set_read_mode(struct qup_i2c_dev *qup, int len)
984 {
985 if (len < qup->in_fifo_sz) {
986 /* FIFO mode */
987 writel(QUP_REPACK_EN, qup->base + QUP_IO_MODE);
988 writel(len, qup->base + QUP_MX_READ_CNT);
989 } else {
990 /* BLOCK mode (transfer data on chunks) */
991 writel(QUP_INPUT_BLK_MODE | QUP_REPACK_EN,
992 qup->base + QUP_IO_MODE);
993 writel(len, qup->base + QUP_MX_INPUT_CNT);
994 }
995 }
996
997 static void qup_i2c_set_read_mode_v2(struct qup_i2c_dev *qup, int len)
998 {
999 int tx_len = qup->blk.tx_tag_len;
1000
1001 len += qup->blk.rx_tag_len;
1002 len |= qup->config_run;
1003 tx_len |= qup->config_run;
1004
1005 if (len < qup->in_fifo_sz) {
1006 /* FIFO mode */
1007 writel(QUP_REPACK_EN, qup->base + QUP_IO_MODE);
1008 writel(tx_len, qup->base + QUP_MX_WRITE_CNT);
1009 writel(len, qup->base + QUP_MX_READ_CNT);
1010 } else {
1011 /* BLOCK mode (transfer data on chunks) */
1012 writel(QUP_INPUT_BLK_MODE | QUP_REPACK_EN,
1013 qup->base + QUP_IO_MODE);
1014 writel(tx_len, qup->base + QUP_MX_OUTPUT_CNT);
1015 writel(len, qup->base + QUP_MX_INPUT_CNT);
1016 }
1017 }
1018
1019 static void qup_i2c_issue_read(struct qup_i2c_dev *qup, struct i2c_msg *msg)
1020 {
1021 u32 addr, len, val;
1022
1023 addr = (msg->addr << 1) | 1;
1024
1025 /* 0 is used to specify a length 256 (QUP_READ_LIMIT) */
1026 len = (msg->len == QUP_READ_LIMIT) ? 0 : msg->len;
1027
1028 val = ((QUP_TAG_REC | len) << QUP_MSW_SHIFT) | QUP_TAG_START | addr;
1029 writel(val, qup->base + QUP_OUT_FIFO_BASE);
1030 }
1031
1032
1033 static int qup_i2c_read_fifo(struct qup_i2c_dev *qup, struct i2c_msg *msg)
1034 {
1035 u32 val = 0;
1036 int idx;
1037 int ret = 0;
1038
1039 for (idx = 0; qup->pos < msg->len; idx++) {
1040 if ((idx & 1) == 0) {
1041 /* Check that FIFO have data */
1042 ret = qup_i2c_wait_ready(qup, QUP_IN_NOT_EMPTY,
1043 SET_BIT, 4 * ONE_BYTE);
1044 if (ret)
1045 return ret;
1046
1047 /* Reading 2 words at time */
1048 val = readl(qup->base + QUP_IN_FIFO_BASE);
1049
1050 msg->buf[qup->pos++] = val & 0xFF;
1051 } else {
1052 msg->buf[qup->pos++] = val >> QUP_MSW_SHIFT;
1053 }
1054 }
1055
1056 return ret;
1057 }
1058
1059 static int qup_i2c_read_fifo_v2(struct qup_i2c_dev *qup,
1060 struct i2c_msg *msg)
1061 {
1062 u32 val;
1063 int idx, pos = 0, ret = 0, total;
1064
1065 total = qup_i2c_get_data_len(qup);
1066
1067 /* 2 extra bytes for read tags */
1068 while (pos < (total + 2)) {
1069 /* Check that FIFO have data */
1070 ret = qup_i2c_wait_ready(qup, QUP_IN_NOT_EMPTY,
1071 SET_BIT, 4 * ONE_BYTE);
1072 if (ret) {
1073 dev_err(qup->dev, "timeout for fifo not empty");
1074 return ret;
1075 }
1076 val = readl(qup->base + QUP_IN_FIFO_BASE);
1077
1078 for (idx = 0; idx < 4; idx++, val >>= 8, pos++) {
1079 /* first 2 bytes are tag bytes */
1080 if (pos < 2)
1081 continue;
1082
1083 if (pos >= (total + 2))
1084 goto out;
1085
1086 msg->buf[qup->pos++] = val & 0xff;
1087 }
1088 }
1089
1090 out:
1091 qup->blk.data_len -= total;
1092
1093 return ret;
1094 }
1095
1096 static int qup_i2c_read_one_v2(struct qup_i2c_dev *qup, struct i2c_msg *msg)
1097 {
1098 int ret = 0;
1099
1100 qup->msg = msg;
1101 qup->pos = 0;
1102 enable_irq(qup->irq);
1103 qup_i2c_set_blk_data(qup, msg);
1104 qup_i2c_set_read_mode_v2(qup, msg->len);
1105
1106 ret = qup_i2c_change_state(qup, QUP_RUN_STATE);
1107 if (ret)
1108 goto err;
1109
1110 writel(qup->clk_ctl, qup->base + QUP_I2C_CLK_CTL);
1111
1112 do {
1113 ret = qup_i2c_issue_xfer_v2(qup, msg);
1114 if (ret)
1115 goto err;
1116
1117 ret = qup_i2c_wait_for_complete(qup, msg);
1118 if (ret)
1119 goto err;
1120
1121 ret = qup_i2c_read_fifo_v2(qup, msg);
1122 if (ret)
1123 goto err;
1124
1125 qup->blk.pos++;
1126 } while (qup->blk.pos < qup->blk.count);
1127
1128 err:
1129 disable_irq(qup->irq);
1130 qup->msg = NULL;
1131
1132 return ret;
1133 }
1134
1135 static int qup_i2c_read_one(struct qup_i2c_dev *qup, struct i2c_msg *msg)
1136 {
1137 int ret;
1138
1139 qup->msg = msg;
1140 qup->pos = 0;
1141
1142 enable_irq(qup->irq);
1143 qup_i2c_set_read_mode(qup, msg->len);
1144
1145 ret = qup_i2c_change_state(qup, QUP_RUN_STATE);
1146 if (ret)
1147 goto err;
1148
1149 writel(qup->clk_ctl, qup->base + QUP_I2C_CLK_CTL);
1150
1151 ret = qup_i2c_change_state(qup, QUP_PAUSE_STATE);
1152 if (ret)
1153 goto err;
1154
1155 qup_i2c_issue_read(qup, msg);
1156
1157 ret = qup_i2c_change_state(qup, QUP_RUN_STATE);
1158 if (ret)
1159 goto err;
1160
1161 do {
1162 ret = qup_i2c_wait_for_complete(qup, msg);
1163 if (ret)
1164 goto err;
1165
1166 ret = qup_i2c_read_fifo(qup, msg);
1167 if (ret)
1168 goto err;
1169 } while (qup->pos < msg->len);
1170
1171 err:
1172 disable_irq(qup->irq);
1173 qup->msg = NULL;
1174
1175 return ret;
1176 }
1177
1178 static int qup_i2c_xfer(struct i2c_adapter *adap,
1179 struct i2c_msg msgs[],
1180 int num)
1181 {
1182 struct qup_i2c_dev *qup = i2c_get_adapdata(adap);
1183 int ret, idx;
1184
1185 ret = pm_runtime_get_sync(qup->dev);
1186 if (ret < 0)
1187 goto out;
1188
1189 writel(1, qup->base + QUP_SW_RESET);
1190 ret = qup_i2c_poll_state(qup, QUP_RESET_STATE);
1191 if (ret)
1192 goto out;
1193
1194 /* Configure QUP as I2C mini core */
1195 writel(I2C_MINI_CORE | I2C_N_VAL, qup->base + QUP_CONFIG);
1196
1197 for (idx = 0; idx < num; idx++) {
1198 if (msgs[idx].len == 0) {
1199 ret = -EINVAL;
1200 goto out;
1201 }
1202
1203 if (qup_i2c_poll_state_i2c_master(qup)) {
1204 ret = -EIO;
1205 goto out;
1206 }
1207
1208 if (msgs[idx].flags & I2C_M_RD)
1209 ret = qup_i2c_read_one(qup, &msgs[idx]);
1210 else
1211 ret = qup_i2c_write_one(qup, &msgs[idx]);
1212
1213 if (ret)
1214 break;
1215
1216 ret = qup_i2c_change_state(qup, QUP_RESET_STATE);
1217 if (ret)
1218 break;
1219 }
1220
1221 if (ret == 0)
1222 ret = num;
1223 out:
1224
1225 pm_runtime_mark_last_busy(qup->dev);
1226 pm_runtime_put_autosuspend(qup->dev);
1227
1228 return ret;
1229 }
1230
1231 static int qup_i2c_xfer_v2(struct i2c_adapter *adap,
1232 struct i2c_msg msgs[],
1233 int num)
1234 {
1235 struct qup_i2c_dev *qup = i2c_get_adapdata(adap);
1236 int ret, len, idx = 0, use_dma = 0;
1237
1238 ret = pm_runtime_get_sync(qup->dev);
1239 if (ret < 0)
1240 goto out;
1241
1242 writel(1, qup->base + QUP_SW_RESET);
1243 ret = qup_i2c_poll_state(qup, QUP_RESET_STATE);
1244 if (ret)
1245 goto out;
1246
1247 /* Configure QUP as I2C mini core */
1248 writel(I2C_MINI_CORE | I2C_N_VAL_V2, qup->base + QUP_CONFIG);
1249 writel(QUP_V2_TAGS_EN, qup->base + QUP_I2C_MASTER_GEN);
1250
1251 if ((qup->is_dma)) {
1252 /* All i2c_msgs should be transferred using either dma or cpu */
1253 for (idx = 0; idx < num; idx++) {
1254 if (msgs[idx].len == 0) {
1255 ret = -EINVAL;
1256 goto out;
1257 }
1258
1259 len = (msgs[idx].len > qup->out_fifo_sz) ||
1260 (msgs[idx].len > qup->in_fifo_sz);
1261
1262 if ((!is_vmalloc_addr(msgs[idx].buf)) && len) {
1263 use_dma = 1;
1264 } else {
1265 use_dma = 0;
1266 break;
1267 }
1268 }
1269 }
1270
1271 do {
1272 if (msgs[idx].len == 0) {
1273 ret = -EINVAL;
1274 goto out;
1275 }
1276
1277 if (qup_i2c_poll_state_i2c_master(qup)) {
1278 ret = -EIO;
1279 goto out;
1280 }
1281
1282 qup->is_last = (idx == (num - 1));
1283 if (idx)
1284 qup->config_run = QUP_I2C_MX_CONFIG_DURING_RUN;
1285 else
1286 qup->config_run = 0;
1287
1288 reinit_completion(&qup->xfer);
1289
1290 if (use_dma) {
1291 ret = qup_i2c_bam_xfer(adap, &msgs[idx], num);
1292 } else {
1293 if (msgs[idx].flags & I2C_M_RD)
1294 ret = qup_i2c_read_one_v2(qup, &msgs[idx]);
1295 else
1296 ret = qup_i2c_write_one_v2(qup, &msgs[idx]);
1297 }
1298 } while ((idx++ < (num - 1)) && !use_dma && !ret);
1299
1300 if (!ret)
1301 ret = qup_i2c_change_state(qup, QUP_RESET_STATE);
1302
1303 if (ret == 0)
1304 ret = num;
1305 out:
1306 pm_runtime_mark_last_busy(qup->dev);
1307 pm_runtime_put_autosuspend(qup->dev);
1308
1309 return ret;
1310 }
1311
1312 static u32 qup_i2c_func(struct i2c_adapter *adap)
1313 {
1314 return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK);
1315 }
1316
1317 static const struct i2c_algorithm qup_i2c_algo = {
1318 .master_xfer = qup_i2c_xfer,
1319 .functionality = qup_i2c_func,
1320 };
1321
1322 static const struct i2c_algorithm qup_i2c_algo_v2 = {
1323 .master_xfer = qup_i2c_xfer_v2,
1324 .functionality = qup_i2c_func,
1325 };
1326
1327 /*
1328 * The QUP block will issue a NACK and STOP on the bus when reaching
1329 * the end of the read, the length of the read is specified as one byte
1330 * which limits the possible read to 256 (QUP_READ_LIMIT) bytes.
1331 */
1332 static struct i2c_adapter_quirks qup_i2c_quirks = {
1333 .max_read_len = QUP_READ_LIMIT,
1334 };
1335
1336 static void qup_i2c_enable_clocks(struct qup_i2c_dev *qup)
1337 {
1338 clk_prepare_enable(qup->clk);
1339 clk_prepare_enable(qup->pclk);
1340 }
1341
1342 static void qup_i2c_disable_clocks(struct qup_i2c_dev *qup)
1343 {
1344 u32 config;
1345
1346 qup_i2c_change_state(qup, QUP_RESET_STATE);
1347 clk_disable_unprepare(qup->clk);
1348 config = readl(qup->base + QUP_CONFIG);
1349 config |= QUP_CLOCK_AUTO_GATE;
1350 writel(config, qup->base + QUP_CONFIG);
1351 clk_disable_unprepare(qup->pclk);
1352 }
1353
1354 static int qup_i2c_probe(struct platform_device *pdev)
1355 {
1356 static const int blk_sizes[] = {4, 16, 32};
1357 struct device_node *node = pdev->dev.of_node;
1358 struct qup_i2c_dev *qup;
1359 unsigned long one_bit_t;
1360 struct resource *res;
1361 u32 io_mode, hw_ver, size;
1362 int ret, fs_div, hs_div;
1363 int src_clk_freq;
1364 u32 clk_freq = 100000;
1365 int blocks;
1366
1367 qup = devm_kzalloc(&pdev->dev, sizeof(*qup), GFP_KERNEL);
1368 if (!qup)
1369 return -ENOMEM;
1370
1371 qup->dev = &pdev->dev;
1372 init_completion(&qup->xfer);
1373 platform_set_drvdata(pdev, qup);
1374
1375 of_property_read_u32(node, "clock-frequency", &clk_freq);
1376
1377 if (of_device_is_compatible(pdev->dev.of_node, "qcom,i2c-qup-v1.1.1")) {
1378 qup->adap.algo = &qup_i2c_algo;
1379 qup->adap.quirks = &qup_i2c_quirks;
1380 } else {
1381 qup->adap.algo = &qup_i2c_algo_v2;
1382 ret = qup_i2c_req_dma(qup);
1383
1384 if (ret == -EPROBE_DEFER)
1385 goto fail_dma;
1386 else if (ret != 0)
1387 goto nodma;
1388
1389 blocks = (MX_BLOCKS << 1) + 1;
1390 qup->btx.sg = devm_kzalloc(&pdev->dev,
1391 sizeof(*qup->btx.sg) * blocks,
1392 GFP_KERNEL);
1393 if (!qup->btx.sg) {
1394 ret = -ENOMEM;
1395 goto fail_dma;
1396 }
1397 sg_init_table(qup->btx.sg, blocks);
1398
1399 qup->brx.sg = devm_kzalloc(&pdev->dev,
1400 sizeof(*qup->brx.sg) * blocks,
1401 GFP_KERNEL);
1402 if (!qup->brx.sg) {
1403 ret = -ENOMEM;
1404 goto fail_dma;
1405 }
1406 sg_init_table(qup->brx.sg, blocks);
1407
1408 /* 2 tag bytes for each block + 5 for start, stop tags */
1409 size = blocks * 2 + 5;
1410 qup->dpool = dma_pool_create("qup_i2c-dma-pool", &pdev->dev,
1411 size, 4, 0);
1412
1413 qup->start_tag.start = dma_pool_alloc(qup->dpool, GFP_KERNEL,
1414 &qup->start_tag.addr);
1415 if (!qup->start_tag.start) {
1416 ret = -ENOMEM;
1417 goto fail_dma;
1418 }
1419
1420 qup->brx.tag.start = dma_pool_alloc(qup->dpool,
1421 GFP_KERNEL,
1422 &qup->brx.tag.addr);
1423 if (!qup->brx.tag.start) {
1424 ret = -ENOMEM;
1425 goto fail_dma;
1426 }
1427
1428 qup->btx.tag.start = dma_pool_alloc(qup->dpool,
1429 GFP_KERNEL,
1430 &qup->btx.tag.addr);
1431 if (!qup->btx.tag.start) {
1432 ret = -ENOMEM;
1433 goto fail_dma;
1434 }
1435 qup->is_dma = true;
1436 }
1437
1438 nodma:
1439 /* We support frequencies up to FAST Mode (400KHz) */
1440 if (!clk_freq || clk_freq > 400000) {
1441 dev_err(qup->dev, "clock frequency not supported %d\n",
1442 clk_freq);
1443 return -EINVAL;
1444 }
1445
1446 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1447 qup->base = devm_ioremap_resource(qup->dev, res);
1448 if (IS_ERR(qup->base))
1449 return PTR_ERR(qup->base);
1450
1451 qup->irq = platform_get_irq(pdev, 0);
1452 if (qup->irq < 0) {
1453 dev_err(qup->dev, "No IRQ defined\n");
1454 return qup->irq;
1455 }
1456
1457 qup->clk = devm_clk_get(qup->dev, "core");
1458 if (IS_ERR(qup->clk)) {
1459 dev_err(qup->dev, "Could not get core clock\n");
1460 return PTR_ERR(qup->clk);
1461 }
1462
1463 qup->pclk = devm_clk_get(qup->dev, "iface");
1464 if (IS_ERR(qup->pclk)) {
1465 dev_err(qup->dev, "Could not get iface clock\n");
1466 return PTR_ERR(qup->pclk);
1467 }
1468
1469 qup_i2c_enable_clocks(qup);
1470
1471 /*
1472 * Bootloaders might leave a pending interrupt on certain QUP's,
1473 * so we reset the core before registering for interrupts.
1474 */
1475 writel(1, qup->base + QUP_SW_RESET);
1476 ret = qup_i2c_poll_state_valid(qup);
1477 if (ret)
1478 goto fail;
1479
1480 ret = devm_request_irq(qup->dev, qup->irq, qup_i2c_interrupt,
1481 IRQF_TRIGGER_HIGH, "i2c_qup", qup);
1482 if (ret) {
1483 dev_err(qup->dev, "Request %d IRQ failed\n", qup->irq);
1484 goto fail;
1485 }
1486 disable_irq(qup->irq);
1487
1488 hw_ver = readl(qup->base + QUP_HW_VERSION);
1489 dev_dbg(qup->dev, "Revision %x\n", hw_ver);
1490
1491 io_mode = readl(qup->base + QUP_IO_MODE);
1492
1493 /*
1494 * The block/fifo size w.r.t. 'actual data' is 1/2 due to 'tag'
1495 * associated with each byte written/received
1496 */
1497 size = QUP_OUTPUT_BLOCK_SIZE(io_mode);
1498 if (size >= ARRAY_SIZE(blk_sizes)) {
1499 ret = -EIO;
1500 goto fail;
1501 }
1502 qup->out_blk_sz = blk_sizes[size] / 2;
1503
1504 size = QUP_INPUT_BLOCK_SIZE(io_mode);
1505 if (size >= ARRAY_SIZE(blk_sizes)) {
1506 ret = -EIO;
1507 goto fail;
1508 }
1509 qup->in_blk_sz = blk_sizes[size] / 2;
1510
1511 size = QUP_OUTPUT_FIFO_SIZE(io_mode);
1512 qup->out_fifo_sz = qup->out_blk_sz * (2 << size);
1513
1514 size = QUP_INPUT_FIFO_SIZE(io_mode);
1515 qup->in_fifo_sz = qup->in_blk_sz * (2 << size);
1516
1517 src_clk_freq = clk_get_rate(qup->clk);
1518 fs_div = ((src_clk_freq / clk_freq) / 2) - 3;
1519 hs_div = 3;
1520 qup->clk_ctl = (hs_div << 8) | (fs_div & 0xff);
1521
1522 /*
1523 * Time it takes for a byte to be clocked out on the bus.
1524 * Each byte takes 9 clock cycles (8 bits + 1 ack).
1525 */
1526 one_bit_t = (USEC_PER_SEC / clk_freq) + 1;
1527 qup->one_byte_t = one_bit_t * 9;
1528
1529 dev_dbg(qup->dev, "IN:block:%d, fifo:%d, OUT:block:%d, fifo:%d\n",
1530 qup->in_blk_sz, qup->in_fifo_sz,
1531 qup->out_blk_sz, qup->out_fifo_sz);
1532
1533 i2c_set_adapdata(&qup->adap, qup);
1534 qup->adap.dev.parent = qup->dev;
1535 qup->adap.dev.of_node = pdev->dev.of_node;
1536 qup->is_last = true;
1537
1538 strlcpy(qup->adap.name, "QUP I2C adapter", sizeof(qup->adap.name));
1539
1540 pm_runtime_set_autosuspend_delay(qup->dev, MSEC_PER_SEC);
1541 pm_runtime_use_autosuspend(qup->dev);
1542 pm_runtime_set_active(qup->dev);
1543 pm_runtime_enable(qup->dev);
1544
1545 ret = i2c_add_adapter(&qup->adap);
1546 if (ret)
1547 goto fail_runtime;
1548
1549 return 0;
1550
1551 fail_runtime:
1552 pm_runtime_disable(qup->dev);
1553 pm_runtime_set_suspended(qup->dev);
1554 fail:
1555 qup_i2c_disable_clocks(qup);
1556 fail_dma:
1557 if (qup->btx.dma)
1558 dma_release_channel(qup->btx.dma);
1559 if (qup->brx.dma)
1560 dma_release_channel(qup->brx.dma);
1561 return ret;
1562 }
1563
1564 static int qup_i2c_remove(struct platform_device *pdev)
1565 {
1566 struct qup_i2c_dev *qup = platform_get_drvdata(pdev);
1567
1568 if (qup->is_dma) {
1569 dma_pool_free(qup->dpool, qup->start_tag.start,
1570 qup->start_tag.addr);
1571 dma_pool_free(qup->dpool, qup->brx.tag.start,
1572 qup->brx.tag.addr);
1573 dma_pool_free(qup->dpool, qup->btx.tag.start,
1574 qup->btx.tag.addr);
1575 dma_pool_destroy(qup->dpool);
1576 dma_release_channel(qup->btx.dma);
1577 dma_release_channel(qup->brx.dma);
1578 }
1579
1580 disable_irq(qup->irq);
1581 qup_i2c_disable_clocks(qup);
1582 i2c_del_adapter(&qup->adap);
1583 pm_runtime_disable(qup->dev);
1584 pm_runtime_set_suspended(qup->dev);
1585 return 0;
1586 }
1587
1588 #ifdef CONFIG_PM
1589 static int qup_i2c_pm_suspend_runtime(struct device *device)
1590 {
1591 struct qup_i2c_dev *qup = dev_get_drvdata(device);
1592
1593 dev_dbg(device, "pm_runtime: suspending...\n");
1594 qup_i2c_disable_clocks(qup);
1595 return 0;
1596 }
1597
1598 static int qup_i2c_pm_resume_runtime(struct device *device)
1599 {
1600 struct qup_i2c_dev *qup = dev_get_drvdata(device);
1601
1602 dev_dbg(device, "pm_runtime: resuming...\n");
1603 qup_i2c_enable_clocks(qup);
1604 return 0;
1605 }
1606 #endif
1607
1608 #ifdef CONFIG_PM_SLEEP
1609 static int qup_i2c_suspend(struct device *device)
1610 {
1611 qup_i2c_pm_suspend_runtime(device);
1612 return 0;
1613 }
1614
1615 static int qup_i2c_resume(struct device *device)
1616 {
1617 qup_i2c_pm_resume_runtime(device);
1618 pm_runtime_mark_last_busy(device);
1619 pm_request_autosuspend(device);
1620 return 0;
1621 }
1622 #endif
1623
1624 static const struct dev_pm_ops qup_i2c_qup_pm_ops = {
1625 SET_SYSTEM_SLEEP_PM_OPS(
1626 qup_i2c_suspend,
1627 qup_i2c_resume)
1628 SET_RUNTIME_PM_OPS(
1629 qup_i2c_pm_suspend_runtime,
1630 qup_i2c_pm_resume_runtime,
1631 NULL)
1632 };
1633
1634 static const struct of_device_id qup_i2c_dt_match[] = {
1635 { .compatible = "qcom,i2c-qup-v1.1.1" },
1636 { .compatible = "qcom,i2c-qup-v2.1.1" },
1637 { .compatible = "qcom,i2c-qup-v2.2.1" },
1638 {}
1639 };
1640 MODULE_DEVICE_TABLE(of, qup_i2c_dt_match);
1641
1642 static struct platform_driver qup_i2c_driver = {
1643 .probe = qup_i2c_probe,
1644 .remove = qup_i2c_remove,
1645 .driver = {
1646 .name = "i2c_qup",
1647 .pm = &qup_i2c_qup_pm_ops,
1648 .of_match_table = qup_i2c_dt_match,
1649 },
1650 };
1651
1652 module_platform_driver(qup_i2c_driver);
1653
1654 MODULE_LICENSE("GPL v2");
1655 MODULE_ALIAS("platform:i2c_qup");
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