1 /* linux/drivers/i2c/busses/i2c-s3c2410.c
3 * Copyright (C) 2004,2005,2009 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
6 * S3C2410 I2C Controller
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 #include <linux/kernel.h>
24 #include <linux/module.h>
26 #include <linux/i2c.h>
27 #include <linux/init.h>
28 #include <linux/time.h>
29 #include <linux/interrupt.h>
30 #include <linux/delay.h>
31 #include <linux/errno.h>
32 #include <linux/err.h>
33 #include <linux/platform_device.h>
34 #include <linux/pm_runtime.h>
35 #include <linux/clk.h>
36 #include <linux/cpufreq.h>
37 #include <linux/slab.h>
39 #include <linux/of_i2c.h>
40 #include <linux/of_gpio.h>
44 #include <plat/regs-iic.h>
47 /* Treat S3C2410 as baseline hardware, anything else is supported via quirks */
48 #define QUIRK_S3C2440 (1 << 0)
49 #define QUIRK_HDMIPHY (1 << 1)
50 #define QUIRK_NO_GPIO (1 << 2)
52 /* i2c controller state */
53 enum s3c24xx_i2c_state
{
63 wait_queue_head_t wait
;
65 unsigned int suspended
:1;
72 unsigned int tx_setup
;
75 enum s3c24xx_i2c_state state
;
76 unsigned long clkrate
;
81 struct resource
*ioarea
;
82 struct i2c_adapter adap
;
84 struct s3c2410_platform_i2c
*pdata
;
86 #ifdef CONFIG_CPU_FREQ
87 struct notifier_block freq_transition
;
91 static struct platform_device_id s3c24xx_driver_ids
[] = {
93 .name
= "s3c2410-i2c",
96 .name
= "s3c2440-i2c",
97 .driver_data
= QUIRK_S3C2440
,
99 .name
= "s3c2440-hdmiphy-i2c",
100 .driver_data
= QUIRK_S3C2440
| QUIRK_HDMIPHY
| QUIRK_NO_GPIO
,
103 MODULE_DEVICE_TABLE(platform
, s3c24xx_driver_ids
);
106 static const struct of_device_id s3c24xx_i2c_match
[] = {
107 { .compatible
= "samsung,s3c2410-i2c", .data
= (void *)0 },
108 { .compatible
= "samsung,s3c2440-i2c", .data
= (void *)QUIRK_S3C2440
},
109 { .compatible
= "samsung,s3c2440-hdmiphy-i2c",
110 .data
= (void *)(QUIRK_S3C2440
| QUIRK_HDMIPHY
| QUIRK_NO_GPIO
) },
113 MODULE_DEVICE_TABLE(of
, s3c24xx_i2c_match
);
116 /* s3c24xx_get_device_quirks
118 * Get controller type either from device tree or platform device variant.
121 static inline unsigned int s3c24xx_get_device_quirks(struct platform_device
*pdev
)
123 if (pdev
->dev
.of_node
) {
124 const struct of_device_id
*match
;
125 match
= of_match_node(&s3c24xx_i2c_match
, pdev
->dev
.of_node
);
126 return (unsigned int)match
->data
;
129 return platform_get_device_id(pdev
)->driver_data
;
132 /* s3c24xx_i2c_master_complete
134 * complete the message and wake up the caller, using the given return code,
135 * or zero to mean ok.
138 static inline void s3c24xx_i2c_master_complete(struct s3c24xx_i2c
*i2c
, int ret
)
140 dev_dbg(i2c
->dev
, "master_complete %d\n", ret
);
152 static inline void s3c24xx_i2c_disable_ack(struct s3c24xx_i2c
*i2c
)
156 tmp
= readl(i2c
->regs
+ S3C2410_IICCON
);
157 writel(tmp
& ~S3C2410_IICCON_ACKEN
, i2c
->regs
+ S3C2410_IICCON
);
160 static inline void s3c24xx_i2c_enable_ack(struct s3c24xx_i2c
*i2c
)
164 tmp
= readl(i2c
->regs
+ S3C2410_IICCON
);
165 writel(tmp
| S3C2410_IICCON_ACKEN
, i2c
->regs
+ S3C2410_IICCON
);
168 /* irq enable/disable functions */
170 static inline void s3c24xx_i2c_disable_irq(struct s3c24xx_i2c
*i2c
)
174 tmp
= readl(i2c
->regs
+ S3C2410_IICCON
);
175 writel(tmp
& ~S3C2410_IICCON_IRQEN
, i2c
->regs
+ S3C2410_IICCON
);
178 static inline void s3c24xx_i2c_enable_irq(struct s3c24xx_i2c
*i2c
)
182 tmp
= readl(i2c
->regs
+ S3C2410_IICCON
);
183 writel(tmp
| S3C2410_IICCON_IRQEN
, i2c
->regs
+ S3C2410_IICCON
);
187 /* s3c24xx_i2c_message_start
189 * put the start of a message onto the bus
192 static void s3c24xx_i2c_message_start(struct s3c24xx_i2c
*i2c
,
195 unsigned int addr
= (msg
->addr
& 0x7f) << 1;
197 unsigned long iiccon
;
200 stat
|= S3C2410_IICSTAT_TXRXEN
;
202 if (msg
->flags
& I2C_M_RD
) {
203 stat
|= S3C2410_IICSTAT_MASTER_RX
;
206 stat
|= S3C2410_IICSTAT_MASTER_TX
;
208 if (msg
->flags
& I2C_M_REV_DIR_ADDR
)
211 /* todo - check for wether ack wanted or not */
212 s3c24xx_i2c_enable_ack(i2c
);
214 iiccon
= readl(i2c
->regs
+ S3C2410_IICCON
);
215 writel(stat
, i2c
->regs
+ S3C2410_IICSTAT
);
217 dev_dbg(i2c
->dev
, "START: %08lx to IICSTAT, %02x to DS\n", stat
, addr
);
218 writeb(addr
, i2c
->regs
+ S3C2410_IICDS
);
220 /* delay here to ensure the data byte has gotten onto the bus
221 * before the transaction is started */
223 ndelay(i2c
->tx_setup
);
225 dev_dbg(i2c
->dev
, "iiccon, %08lx\n", iiccon
);
226 writel(iiccon
, i2c
->regs
+ S3C2410_IICCON
);
228 stat
|= S3C2410_IICSTAT_START
;
229 writel(stat
, i2c
->regs
+ S3C2410_IICSTAT
);
232 static inline void s3c24xx_i2c_stop(struct s3c24xx_i2c
*i2c
, int ret
)
234 unsigned long iicstat
= readl(i2c
->regs
+ S3C2410_IICSTAT
);
236 dev_dbg(i2c
->dev
, "STOP\n");
238 /* stop the transfer */
239 iicstat
&= ~S3C2410_IICSTAT_START
;
240 writel(iicstat
, i2c
->regs
+ S3C2410_IICSTAT
);
242 i2c
->state
= STATE_STOP
;
244 s3c24xx_i2c_master_complete(i2c
, ret
);
245 s3c24xx_i2c_disable_irq(i2c
);
248 /* helper functions to determine the current state in the set of
249 * messages we are sending */
253 * returns TRUE if the current message is the last in the set
256 static inline int is_lastmsg(struct s3c24xx_i2c
*i2c
)
258 return i2c
->msg_idx
>= (i2c
->msg_num
- 1);
263 * returns TRUE if we this is the last byte in the current message
266 static inline int is_msglast(struct s3c24xx_i2c
*i2c
)
268 return i2c
->msg_ptr
== i2c
->msg
->len
-1;
273 * returns TRUE if we reached the end of the current message
276 static inline int is_msgend(struct s3c24xx_i2c
*i2c
)
278 return i2c
->msg_ptr
>= i2c
->msg
->len
;
281 /* i2c_s3c_irq_nextbyte
283 * process an interrupt and work out what to do
286 static int i2c_s3c_irq_nextbyte(struct s3c24xx_i2c
*i2c
, unsigned long iicstat
)
292 switch (i2c
->state
) {
295 dev_err(i2c
->dev
, "%s: called in STATE_IDLE\n", __func__
);
299 dev_err(i2c
->dev
, "%s: called in STATE_STOP\n", __func__
);
300 s3c24xx_i2c_disable_irq(i2c
);
304 /* last thing we did was send a start condition on the
305 * bus, or started a new i2c message
308 if (iicstat
& S3C2410_IICSTAT_LASTBIT
&&
309 !(i2c
->msg
->flags
& I2C_M_IGNORE_NAK
)) {
310 /* ack was not received... */
312 dev_dbg(i2c
->dev
, "ack was not received\n");
313 s3c24xx_i2c_stop(i2c
, -ENXIO
);
317 if (i2c
->msg
->flags
& I2C_M_RD
)
318 i2c
->state
= STATE_READ
;
320 i2c
->state
= STATE_WRITE
;
322 /* terminate the transfer if there is nothing to do
323 * as this is used by the i2c probe to find devices. */
325 if (is_lastmsg(i2c
) && i2c
->msg
->len
== 0) {
326 s3c24xx_i2c_stop(i2c
, 0);
330 if (i2c
->state
== STATE_READ
)
333 /* fall through to the write state, as we will need to
334 * send a byte as well */
337 /* we are writing data to the device... check for the
338 * end of the message, and if so, work out what to do
341 if (!(i2c
->msg
->flags
& I2C_M_IGNORE_NAK
)) {
342 if (iicstat
& S3C2410_IICSTAT_LASTBIT
) {
343 dev_dbg(i2c
->dev
, "WRITE: No Ack\n");
345 s3c24xx_i2c_stop(i2c
, -ECONNREFUSED
);
352 if (!is_msgend(i2c
)) {
353 byte
= i2c
->msg
->buf
[i2c
->msg_ptr
++];
354 writeb(byte
, i2c
->regs
+ S3C2410_IICDS
);
356 /* delay after writing the byte to allow the
357 * data setup time on the bus, as writing the
358 * data to the register causes the first bit
359 * to appear on SDA, and SCL will change as
360 * soon as the interrupt is acknowledged */
362 ndelay(i2c
->tx_setup
);
364 } else if (!is_lastmsg(i2c
)) {
365 /* we need to go to the next i2c message */
367 dev_dbg(i2c
->dev
, "WRITE: Next Message\n");
373 /* check to see if we need to do another message */
374 if (i2c
->msg
->flags
& I2C_M_NOSTART
) {
376 if (i2c
->msg
->flags
& I2C_M_RD
) {
377 /* cannot do this, the controller
378 * forces us to send a new START
379 * when we change direction */
381 s3c24xx_i2c_stop(i2c
, -EINVAL
);
386 /* send the new start */
387 s3c24xx_i2c_message_start(i2c
, i2c
->msg
);
388 i2c
->state
= STATE_START
;
394 s3c24xx_i2c_stop(i2c
, 0);
399 /* we have a byte of data in the data register, do
400 * something with it, and then work out wether we are
401 * going to do any more read/write
404 byte
= readb(i2c
->regs
+ S3C2410_IICDS
);
405 i2c
->msg
->buf
[i2c
->msg_ptr
++] = byte
;
408 if (is_msglast(i2c
)) {
409 /* last byte of buffer */
412 s3c24xx_i2c_disable_ack(i2c
);
414 } else if (is_msgend(i2c
)) {
415 /* ok, we've read the entire buffer, see if there
416 * is anything else we need to do */
418 if (is_lastmsg(i2c
)) {
419 /* last message, send stop and complete */
420 dev_dbg(i2c
->dev
, "READ: Send Stop\n");
422 s3c24xx_i2c_stop(i2c
, 0);
424 /* go to the next transfer */
425 dev_dbg(i2c
->dev
, "READ: Next Transfer\n");
436 /* acknowlegde the IRQ and get back on with the work */
439 tmp
= readl(i2c
->regs
+ S3C2410_IICCON
);
440 tmp
&= ~S3C2410_IICCON_IRQPEND
;
441 writel(tmp
, i2c
->regs
+ S3C2410_IICCON
);
448 * top level IRQ servicing routine
451 static irqreturn_t
s3c24xx_i2c_irq(int irqno
, void *dev_id
)
453 struct s3c24xx_i2c
*i2c
= dev_id
;
454 unsigned long status
;
457 status
= readl(i2c
->regs
+ S3C2410_IICSTAT
);
459 if (status
& S3C2410_IICSTAT_ARBITR
) {
460 /* deal with arbitration loss */
461 dev_err(i2c
->dev
, "deal with arbitration loss\n");
464 if (i2c
->state
== STATE_IDLE
) {
465 dev_dbg(i2c
->dev
, "IRQ: error i2c->state == IDLE\n");
467 tmp
= readl(i2c
->regs
+ S3C2410_IICCON
);
468 tmp
&= ~S3C2410_IICCON_IRQPEND
;
469 writel(tmp
, i2c
->regs
+ S3C2410_IICCON
);
473 /* pretty much this leaves us with the fact that we've
474 * transmitted or received whatever byte we last sent */
476 i2c_s3c_irq_nextbyte(i2c
, status
);
483 /* s3c24xx_i2c_set_master
485 * get the i2c bus for a master transaction
488 static int s3c24xx_i2c_set_master(struct s3c24xx_i2c
*i2c
)
490 unsigned long iicstat
;
493 /* the timeout for HDMIPHY is reduced to 10 ms because
494 * the hangup is expected to happen, so waiting 400 ms
495 * causes only unnecessary system hangup
497 if (i2c
->quirks
& QUIRK_HDMIPHY
)
500 while (timeout
-- > 0) {
501 iicstat
= readl(i2c
->regs
+ S3C2410_IICSTAT
);
503 if (!(iicstat
& S3C2410_IICSTAT_BUSBUSY
))
509 /* hang-up of bus dedicated for HDMIPHY occurred, resetting */
510 if (i2c
->quirks
& QUIRK_HDMIPHY
) {
511 writel(0, i2c
->regs
+ S3C2410_IICCON
);
512 writel(0, i2c
->regs
+ S3C2410_IICSTAT
);
513 writel(0, i2c
->regs
+ S3C2410_IICDS
);
521 /* s3c24xx_i2c_doxfer
523 * this starts an i2c transfer
526 static int s3c24xx_i2c_doxfer(struct s3c24xx_i2c
*i2c
,
527 struct i2c_msg
*msgs
, int num
)
529 unsigned long iicstat
, timeout
;
536 ret
= s3c24xx_i2c_set_master(i2c
);
538 dev_err(i2c
->dev
, "cannot get bus (error %d)\n", ret
);
543 spin_lock_irq(&i2c
->lock
);
549 i2c
->state
= STATE_START
;
551 s3c24xx_i2c_enable_irq(i2c
);
552 s3c24xx_i2c_message_start(i2c
, msgs
);
553 spin_unlock_irq(&i2c
->lock
);
555 timeout
= wait_event_timeout(i2c
->wait
, i2c
->msg_num
== 0, HZ
* 5);
559 /* having these next two as dev_err() makes life very
560 * noisy when doing an i2cdetect */
563 dev_dbg(i2c
->dev
, "timeout\n");
565 dev_dbg(i2c
->dev
, "incomplete xfer (%d)\n", ret
);
567 /* ensure the stop has been through the bus */
569 dev_dbg(i2c
->dev
, "waiting for bus idle\n");
571 /* first, try busy waiting briefly */
574 iicstat
= readl(i2c
->regs
+ S3C2410_IICSTAT
);
575 } while ((iicstat
& S3C2410_IICSTAT_START
) && --spins
);
577 /* if that timed out sleep */
580 iicstat
= readl(i2c
->regs
+ S3C2410_IICSTAT
);
583 if (iicstat
& S3C2410_IICSTAT_START
)
584 dev_warn(i2c
->dev
, "timeout waiting for bus idle\n");
592 * first port of call from the i2c bus code when an message needs
593 * transferring across the i2c bus.
596 static int s3c24xx_i2c_xfer(struct i2c_adapter
*adap
,
597 struct i2c_msg
*msgs
, int num
)
599 struct s3c24xx_i2c
*i2c
= (struct s3c24xx_i2c
*)adap
->algo_data
;
603 pm_runtime_get_sync(&adap
->dev
);
604 clk_enable(i2c
->clk
);
606 for (retry
= 0; retry
< adap
->retries
; retry
++) {
608 ret
= s3c24xx_i2c_doxfer(i2c
, msgs
, num
);
610 if (ret
!= -EAGAIN
) {
611 clk_disable(i2c
->clk
);
612 pm_runtime_put_sync(&adap
->dev
);
616 dev_dbg(i2c
->dev
, "Retrying transmission (%d)\n", retry
);
621 clk_disable(i2c
->clk
);
622 pm_runtime_put_sync(&adap
->dev
);
626 /* declare our i2c functionality */
627 static u32
s3c24xx_i2c_func(struct i2c_adapter
*adap
)
629 return I2C_FUNC_I2C
| I2C_FUNC_SMBUS_EMUL
| I2C_FUNC_PROTOCOL_MANGLING
;
632 /* i2c bus registration info */
634 static const struct i2c_algorithm s3c24xx_i2c_algorithm
= {
635 .master_xfer
= s3c24xx_i2c_xfer
,
636 .functionality
= s3c24xx_i2c_func
,
639 /* s3c24xx_i2c_calcdivisor
641 * return the divisor settings for a given frequency
644 static int s3c24xx_i2c_calcdivisor(unsigned long clkin
, unsigned int wanted
,
645 unsigned int *div1
, unsigned int *divs
)
647 unsigned int calc_divs
= clkin
/ wanted
;
648 unsigned int calc_div1
;
650 if (calc_divs
> (16*16))
655 calc_divs
+= calc_div1
-1;
656 calc_divs
/= calc_div1
;
666 return clkin
/ (calc_divs
* calc_div1
);
669 /* s3c24xx_i2c_clockrate
671 * work out a divisor for the user requested frequency setting,
672 * either by the requested frequency, or scanning the acceptable
673 * range of frequencies until something is found
676 static int s3c24xx_i2c_clockrate(struct s3c24xx_i2c
*i2c
, unsigned int *got
)
678 struct s3c2410_platform_i2c
*pdata
= i2c
->pdata
;
679 unsigned long clkin
= clk_get_rate(i2c
->clk
);
680 unsigned int divs
, div1
;
681 unsigned long target_frequency
;
685 i2c
->clkrate
= clkin
;
686 clkin
/= 1000; /* clkin now in KHz */
688 dev_dbg(i2c
->dev
, "pdata desired frequency %lu\n", pdata
->frequency
);
690 target_frequency
= pdata
->frequency
? pdata
->frequency
: 100000;
692 target_frequency
/= 1000; /* Target frequency now in KHz */
694 freq
= s3c24xx_i2c_calcdivisor(clkin
, target_frequency
, &div1
, &divs
);
696 if (freq
> target_frequency
) {
698 "Unable to achieve desired frequency %luKHz." \
699 " Lowest achievable %dKHz\n", target_frequency
, freq
);
705 iiccon
= readl(i2c
->regs
+ S3C2410_IICCON
);
706 iiccon
&= ~(S3C2410_IICCON_SCALEMASK
| S3C2410_IICCON_TXDIV_512
);
710 iiccon
|= S3C2410_IICCON_TXDIV_512
;
712 writel(iiccon
, i2c
->regs
+ S3C2410_IICCON
);
714 if (i2c
->quirks
& QUIRK_S3C2440
) {
715 unsigned long sda_delay
;
717 if (pdata
->sda_delay
) {
718 sda_delay
= clkin
* pdata
->sda_delay
;
719 sda_delay
= DIV_ROUND_UP(sda_delay
, 1000000);
720 sda_delay
= DIV_ROUND_UP(sda_delay
, 5);
723 sda_delay
|= S3C2410_IICLC_FILTER_ON
;
727 dev_dbg(i2c
->dev
, "IICLC=%08lx\n", sda_delay
);
728 writel(sda_delay
, i2c
->regs
+ S3C2440_IICLC
);
734 #ifdef CONFIG_CPU_FREQ
736 #define freq_to_i2c(_n) container_of(_n, struct s3c24xx_i2c, freq_transition)
738 static int s3c24xx_i2c_cpufreq_transition(struct notifier_block
*nb
,
739 unsigned long val
, void *data
)
741 struct s3c24xx_i2c
*i2c
= freq_to_i2c(nb
);
747 delta_f
= clk_get_rate(i2c
->clk
) - i2c
->clkrate
;
749 /* if we're post-change and the input clock has slowed down
750 * or at pre-change and the clock is about to speed up, then
751 * adjust our clock rate. <0 is slow, >0 speedup.
754 if ((val
== CPUFREQ_POSTCHANGE
&& delta_f
< 0) ||
755 (val
== CPUFREQ_PRECHANGE
&& delta_f
> 0)) {
756 spin_lock_irqsave(&i2c
->lock
, flags
);
757 ret
= s3c24xx_i2c_clockrate(i2c
, &got
);
758 spin_unlock_irqrestore(&i2c
->lock
, flags
);
761 dev_err(i2c
->dev
, "cannot find frequency\n");
763 dev_info(i2c
->dev
, "setting freq %d\n", got
);
769 static inline int s3c24xx_i2c_register_cpufreq(struct s3c24xx_i2c
*i2c
)
771 i2c
->freq_transition
.notifier_call
= s3c24xx_i2c_cpufreq_transition
;
773 return cpufreq_register_notifier(&i2c
->freq_transition
,
774 CPUFREQ_TRANSITION_NOTIFIER
);
777 static inline void s3c24xx_i2c_deregister_cpufreq(struct s3c24xx_i2c
*i2c
)
779 cpufreq_unregister_notifier(&i2c
->freq_transition
,
780 CPUFREQ_TRANSITION_NOTIFIER
);
784 static inline int s3c24xx_i2c_register_cpufreq(struct s3c24xx_i2c
*i2c
)
789 static inline void s3c24xx_i2c_deregister_cpufreq(struct s3c24xx_i2c
*i2c
)
795 static int s3c24xx_i2c_parse_dt_gpio(struct s3c24xx_i2c
*i2c
)
799 if (i2c
->quirks
& QUIRK_NO_GPIO
)
802 for (idx
= 0; idx
< 2; idx
++) {
803 gpio
= of_get_gpio(i2c
->dev
->of_node
, idx
);
804 if (!gpio_is_valid(gpio
)) {
805 dev_err(i2c
->dev
, "invalid gpio[%d]: %d\n", idx
, gpio
);
809 ret
= gpio_request(gpio
, "i2c-bus");
811 dev_err(i2c
->dev
, "gpio [%d] request failed\n", gpio
);
819 gpio_free(i2c
->gpios
[idx
]);
823 static void s3c24xx_i2c_dt_gpio_free(struct s3c24xx_i2c
*i2c
)
827 if (i2c
->quirks
& QUIRK_NO_GPIO
)
830 for (idx
= 0; idx
< 2; idx
++)
831 gpio_free(i2c
->gpios
[idx
]);
834 static int s3c24xx_i2c_parse_dt_gpio(struct s3c24xx_i2c
*i2c
)
839 static void s3c24xx_i2c_dt_gpio_free(struct s3c24xx_i2c
*i2c
)
846 * initialise the controller, set the IO lines and frequency
849 static int s3c24xx_i2c_init(struct s3c24xx_i2c
*i2c
)
851 unsigned long iicon
= S3C2410_IICCON_IRQEN
| S3C2410_IICCON_ACKEN
;
852 struct s3c2410_platform_i2c
*pdata
;
855 /* get the plafrom data */
859 /* inititalise the gpio */
862 pdata
->cfg_gpio(to_platform_device(i2c
->dev
));
864 if (s3c24xx_i2c_parse_dt_gpio(i2c
))
867 /* write slave address */
869 writeb(pdata
->slave_addr
, i2c
->regs
+ S3C2410_IICADD
);
871 dev_info(i2c
->dev
, "slave address 0x%02x\n", pdata
->slave_addr
);
873 writel(iicon
, i2c
->regs
+ S3C2410_IICCON
);
875 /* we need to work out the divisors for the clock... */
877 if (s3c24xx_i2c_clockrate(i2c
, &freq
) != 0) {
878 writel(0, i2c
->regs
+ S3C2410_IICCON
);
879 dev_err(i2c
->dev
, "cannot meet bus frequency required\n");
883 /* todo - check that the i2c lines aren't being dragged anywhere */
885 dev_info(i2c
->dev
, "bus frequency set to %d KHz\n", freq
);
886 dev_dbg(i2c
->dev
, "S3C2410_IICCON=0x%02lx\n", iicon
);
892 /* s3c24xx_i2c_parse_dt
894 * Parse the device tree node and retreive the platform data.
898 s3c24xx_i2c_parse_dt(struct device_node
*np
, struct s3c24xx_i2c
*i2c
)
900 struct s3c2410_platform_i2c
*pdata
= i2c
->pdata
;
905 pdata
->bus_num
= -1; /* i2c bus number is dynamically assigned */
906 of_property_read_u32(np
, "samsung,i2c-sda-delay", &pdata
->sda_delay
);
907 of_property_read_u32(np
, "samsung,i2c-slave-addr", &pdata
->slave_addr
);
908 of_property_read_u32(np
, "samsung,i2c-max-bus-freq",
909 (u32
*)&pdata
->frequency
);
913 s3c24xx_i2c_parse_dt(struct device_node
*np
, struct s3c24xx_i2c
*i2c
)
921 * called by the bus driver when a suitable device is found
924 static int s3c24xx_i2c_probe(struct platform_device
*pdev
)
926 struct s3c24xx_i2c
*i2c
;
927 struct s3c2410_platform_i2c
*pdata
= NULL
;
928 struct resource
*res
;
931 if (!pdev
->dev
.of_node
) {
932 pdata
= pdev
->dev
.platform_data
;
934 dev_err(&pdev
->dev
, "no platform data\n");
939 i2c
= devm_kzalloc(&pdev
->dev
, sizeof(struct s3c24xx_i2c
), GFP_KERNEL
);
941 dev_err(&pdev
->dev
, "no memory for state\n");
945 i2c
->pdata
= devm_kzalloc(&pdev
->dev
, sizeof(*pdata
), GFP_KERNEL
);
951 i2c
->quirks
= s3c24xx_get_device_quirks(pdev
);
953 memcpy(i2c
->pdata
, pdata
, sizeof(*pdata
));
955 s3c24xx_i2c_parse_dt(pdev
->dev
.of_node
, i2c
);
957 strlcpy(i2c
->adap
.name
, "s3c2410-i2c", sizeof(i2c
->adap
.name
));
958 i2c
->adap
.owner
= THIS_MODULE
;
959 i2c
->adap
.algo
= &s3c24xx_i2c_algorithm
;
960 i2c
->adap
.retries
= 2;
961 i2c
->adap
.class = I2C_CLASS_HWMON
| I2C_CLASS_SPD
;
964 spin_lock_init(&i2c
->lock
);
965 init_waitqueue_head(&i2c
->wait
);
967 /* find the clock and enable it */
969 i2c
->dev
= &pdev
->dev
;
970 i2c
->clk
= clk_get(&pdev
->dev
, "i2c");
971 if (IS_ERR(i2c
->clk
)) {
972 dev_err(&pdev
->dev
, "cannot get clock\n");
977 dev_dbg(&pdev
->dev
, "clock source %p\n", i2c
->clk
);
979 clk_enable(i2c
->clk
);
981 /* map the registers */
983 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
985 dev_err(&pdev
->dev
, "cannot find IO resource\n");
990 i2c
->ioarea
= request_mem_region(res
->start
, resource_size(res
),
993 if (i2c
->ioarea
== NULL
) {
994 dev_err(&pdev
->dev
, "cannot request IO\n");
999 i2c
->regs
= ioremap(res
->start
, resource_size(res
));
1001 if (i2c
->regs
== NULL
) {
1002 dev_err(&pdev
->dev
, "cannot map IO\n");
1007 dev_dbg(&pdev
->dev
, "registers %p (%p, %p)\n",
1008 i2c
->regs
, i2c
->ioarea
, res
);
1010 /* setup info block for the i2c core */
1012 i2c
->adap
.algo_data
= i2c
;
1013 i2c
->adap
.dev
.parent
= &pdev
->dev
;
1015 /* initialise the i2c controller */
1017 ret
= s3c24xx_i2c_init(i2c
);
1021 /* find the IRQ for this unit (note, this relies on the init call to
1022 * ensure no current IRQs pending
1025 i2c
->irq
= ret
= platform_get_irq(pdev
, 0);
1027 dev_err(&pdev
->dev
, "cannot find IRQ\n");
1031 ret
= request_irq(i2c
->irq
, s3c24xx_i2c_irq
, 0,
1032 dev_name(&pdev
->dev
), i2c
);
1035 dev_err(&pdev
->dev
, "cannot claim IRQ %d\n", i2c
->irq
);
1039 ret
= s3c24xx_i2c_register_cpufreq(i2c
);
1041 dev_err(&pdev
->dev
, "failed to register cpufreq notifier\n");
1045 /* Note, previous versions of the driver used i2c_add_adapter()
1046 * to add the bus at any number. We now pass the bus number via
1047 * the platform data, so if unset it will now default to always
1051 i2c
->adap
.nr
= i2c
->pdata
->bus_num
;
1052 i2c
->adap
.dev
.of_node
= pdev
->dev
.of_node
;
1054 ret
= i2c_add_numbered_adapter(&i2c
->adap
);
1056 dev_err(&pdev
->dev
, "failed to add bus to i2c core\n");
1060 of_i2c_register_devices(&i2c
->adap
);
1061 platform_set_drvdata(pdev
, i2c
);
1063 pm_runtime_enable(&pdev
->dev
);
1064 pm_runtime_enable(&i2c
->adap
.dev
);
1066 dev_info(&pdev
->dev
, "%s: S3C I2C adapter\n", dev_name(&i2c
->adap
.dev
));
1067 clk_disable(i2c
->clk
);
1071 s3c24xx_i2c_deregister_cpufreq(i2c
);
1074 free_irq(i2c
->irq
, i2c
);
1080 release_resource(i2c
->ioarea
);
1084 clk_disable(i2c
->clk
);
1091 /* s3c24xx_i2c_remove
1093 * called when device is removed from the bus
1096 static int s3c24xx_i2c_remove(struct platform_device
*pdev
)
1098 struct s3c24xx_i2c
*i2c
= platform_get_drvdata(pdev
);
1100 pm_runtime_disable(&i2c
->adap
.dev
);
1101 pm_runtime_disable(&pdev
->dev
);
1103 s3c24xx_i2c_deregister_cpufreq(i2c
);
1105 i2c_del_adapter(&i2c
->adap
);
1106 free_irq(i2c
->irq
, i2c
);
1108 clk_disable(i2c
->clk
);
1113 release_resource(i2c
->ioarea
);
1114 s3c24xx_i2c_dt_gpio_free(i2c
);
1121 static int s3c24xx_i2c_suspend_noirq(struct device
*dev
)
1123 struct platform_device
*pdev
= to_platform_device(dev
);
1124 struct s3c24xx_i2c
*i2c
= platform_get_drvdata(pdev
);
1131 static int s3c24xx_i2c_resume(struct device
*dev
)
1133 struct platform_device
*pdev
= to_platform_device(dev
);
1134 struct s3c24xx_i2c
*i2c
= platform_get_drvdata(pdev
);
1137 clk_enable(i2c
->clk
);
1138 s3c24xx_i2c_init(i2c
);
1139 clk_disable(i2c
->clk
);
1144 static const struct dev_pm_ops s3c24xx_i2c_dev_pm_ops
= {
1145 .suspend_noirq
= s3c24xx_i2c_suspend_noirq
,
1146 .resume
= s3c24xx_i2c_resume
,
1149 #define S3C24XX_DEV_PM_OPS (&s3c24xx_i2c_dev_pm_ops)
1151 #define S3C24XX_DEV_PM_OPS NULL
1154 /* device driver for platform bus bits */
1156 static struct platform_driver s3c24xx_i2c_driver
= {
1157 .probe
= s3c24xx_i2c_probe
,
1158 .remove
= s3c24xx_i2c_remove
,
1159 .id_table
= s3c24xx_driver_ids
,
1161 .owner
= THIS_MODULE
,
1163 .pm
= S3C24XX_DEV_PM_OPS
,
1164 .of_match_table
= of_match_ptr(s3c24xx_i2c_match
),
1168 static int __init
i2c_adap_s3c_init(void)
1170 return platform_driver_register(&s3c24xx_i2c_driver
);
1172 subsys_initcall(i2c_adap_s3c_init
);
1174 static void __exit
i2c_adap_s3c_exit(void)
1176 platform_driver_unregister(&s3c24xx_i2c_driver
);
1178 module_exit(i2c_adap_s3c_exit
);
1180 MODULE_DESCRIPTION("S3C24XX I2C Bus driver");
1181 MODULE_AUTHOR("Ben Dooks, <ben@simtec.co.uk>");
1182 MODULE_LICENSE("GPL");