drivers/i2c/busses/i2c-sh_mobile.c

   1 /*
   2  * SuperH Mobile I2C Controller
   3  *
   4  * Copyright (C) 2008 Magnus Damm
   5  *
   6  * Portions of the code based on out-of-tree driver i2c-sh7343.c
   7  * Copyright (c) 2006 Carlos Munoz <carlos@kenati.com>
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License as published by
  11  * the Free Software Foundation; either version 2 of the License
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  21  */
  22
  23 #include <linux/kernel.h>
  24 #include <linux/module.h>
  25 #include <linux/init.h>
  26 #include <linux/delay.h>
  27 #include <linux/platform_device.h>
  28 #include <linux/interrupt.h>
  29 #include <linux/i2c.h>
  30 #include <linux/err.h>
  31 #include <linux/pm_runtime.h>
  32 #include <linux/clk.h>
  33 #include <linux/io.h>
  34 #include <linux/slab.h>
  35
  36 /* Transmit operation:                                                      */
  37 /*                                                                          */
  38 /* 0 byte transmit                                                          */
  39 /* BUS:     S     A8     ACK   P                                            */
  40 /* IRQ:       DTE   WAIT                                                    */
  41 /* ICIC:                                                                    */
  42 /* ICCR: 0x94 0x90                                                          */
  43 /* ICDR:      A8                                                            */
  44 /*                                                                          */
  45 /* 1 byte transmit                                                          */
  46 /* BUS:     S     A8     ACK   D8(1)   ACK   P                              */
  47 /* IRQ:       DTE   WAIT         WAIT                                       */
  48 /* ICIC:      -DTE                                                          */
  49 /* ICCR: 0x94       0x90                                                    */
  50 /* ICDR:      A8    D8(1)                                                   */
  51 /*                                                                          */
  52 /* 2 byte transmit                                                          */
  53 /* BUS:     S     A8     ACK   D8(1)   ACK   D8(2)   ACK   P                */
  54 /* IRQ:       DTE   WAIT         WAIT          WAIT                         */
  55 /* ICIC:      -DTE                                                          */
  56 /* ICCR: 0x94                    0x90                                       */
  57 /* ICDR:      A8    D8(1)        D8(2)                                      */
  58 /*                                                                          */
  59 /* 3 bytes or more, +---------+ gets repeated                               */
  60 /*                                                                          */
  61 /*                                                                          */
  62 /* Receive operation:                                                       */
  63 /*                                                                          */
  64 /* 0 byte receive - not supported since slave may hold SDA low              */
  65 /*                                                                          */
  66 /* 1 byte receive       [TX] | [RX]                                         */
  67 /* BUS:     S     A8     ACK | D8(1)   ACK   P                              */
  68 /* IRQ:       DTE   WAIT     |   WAIT     DTE                               */
  69 /* ICIC:      -DTE           |   +DTE                                       */
  70 /* ICCR: 0x94       0x81     |   0xc0                                       */
  71 /* ICDR:      A8             |            D8(1)                             */
  72 /*                                                                          */
  73 /* 2 byte receive        [TX]| [RX]                                         */
  74 /* BUS:     S     A8     ACK | D8(1)   ACK   D8(2)   ACK   P                */
  75 /* IRQ:       DTE   WAIT     |   WAIT          WAIT     DTE                 */
  76 /* ICIC:      -DTE           |                 +DTE                         */
  77 /* ICCR: 0x94       0x81     |                 0xc0                         */
  78 /* ICDR:      A8             |                 D8(1)    D8(2)               */
  79 /*                                                                          */
  80 /* 3 byte receive       [TX] | [RX]                                         */
  81 /* BUS:     S     A8     ACK | D8(1)   ACK   D8(2)   ACK   D8(3)   ACK    P */
  82 /* IRQ:       DTE   WAIT     |   WAIT          WAIT         WAIT      DTE   */
  83 /* ICIC:      -DTE           |                              +DTE            */
  84 /* ICCR: 0x94       0x81     |                              0xc0            */
  85 /* ICDR:      A8             |                 D8(1)        D8(2)     D8(3) */
  86 /*                                                                          */
  87 /* 4 bytes or more, this part is repeated    +---------+                    */
  88 /*                                                                          */
  89 /*                                                                          */
  90 /* Interrupt order and BUSY flag                                            */
  91 /*     ___                                                 _                */
  92 /* SDA ___\___XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXAAAAAAAAA___/                 */
  93 /* SCL      \_/1\_/2\_/3\_/4\_/5\_/6\_/7\_/8\___/9\_____/                   */
  94 /*                                                                          */
  95 /*        S   D7  D6  D5  D4  D3  D2  D1  D0              P                 */
  96 /*                                           ___                            */
  97 /* WAIT IRQ ________________________________/   \___________                */
  98 /* TACK IRQ ____________________________________/   \_______                */
  99 /* DTE  IRQ __________________________________________/   \_                */
 100 /* AL   IRQ XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX                */
 101 /*         _______________________________________________                  */
 102 /* BUSY __/                                               \_                */
 103 /*                                                                          */
 104
 105 enum sh_mobile_i2c_op {
 106         OP_START = 0,
 107         OP_TX_FIRST,
 108         OP_TX,
 109         OP_TX_STOP,
 110         OP_TX_TO_RX,
 111         OP_RX,
 112         OP_RX_STOP,
 113         OP_RX_STOP_DATA,
 114 };
 115
 116 struct sh_mobile_i2c_data {
 117         struct device *dev;
 118         void __iomem *reg;
 119         struct i2c_adapter adap;
 120
 121         struct clk *clk;
 122         u_int8_t iccl;
 123         u_int8_t icch;
 124
 125         spinlock_t lock;
 126         wait_queue_head_t wait;
 127         struct i2c_msg *msg;
 128         int pos;
 129         int sr;
 130 };
 131
 132 #define NORMAL_SPEED            100000 /* FAST_SPEED 400000 */
 133
 134 /* Register offsets */
 135 #define ICDR(pd)                (pd->reg + 0x00)
 136 #define ICCR(pd)                (pd->reg + 0x04)
 137 #define ICSR(pd)                (pd->reg + 0x08)
 138 #define ICIC(pd)                (pd->reg + 0x0c)
 139 #define ICCL(pd)                (pd->reg + 0x10)
 140 #define ICCH(pd)                (pd->reg + 0x14)
 141
 142 /* Register bits */
 143 #define ICCR_ICE                0x80
 144 #define ICCR_RACK               0x40
 145 #define ICCR_TRS                0x10
 146 #define ICCR_BBSY               0x04
 147 #define ICCR_SCP                0x01
 148
 149 #define ICSR_SCLM               0x80
 150 #define ICSR_SDAM               0x40
 151 #define SW_DONE                 0x20
 152 #define ICSR_BUSY               0x10
 153 #define ICSR_AL                 0x08
 154 #define ICSR_TACK               0x04
 155 #define ICSR_WAIT               0x02
 156 #define ICSR_DTE                0x01
 157
 158 #define ICIC_ALE                0x08
 159 #define ICIC_TACKE              0x04
 160 #define ICIC_WAITE              0x02
 161 #define ICIC_DTEE               0x01
 162
 163 static void activate_ch(struct sh_mobile_i2c_data *pd)
 164 {
 165         unsigned long i2c_clk;
 166         u_int32_t num;
 167         u_int32_t denom;
 168         u_int32_t tmp;
 169
 170         /* Wake up device and enable clock */
 171         pm_runtime_get_sync(pd->dev);
 172         clk_enable(pd->clk);
 173
 174         /* Get clock rate after clock is enabled */
 175         i2c_clk = clk_get_rate(pd->clk);
 176
 177         /* Calculate the value for iccl. From the data sheet:
 178          * iccl = (p clock / transfer rate) * (L / (L + H))
 179          * where L and H are the SCL low/high ratio (5/4 in this case).
 180          * We also round off the result.
 181          */
 182         num = i2c_clk * 5;
 183         denom = NORMAL_SPEED * 9;
 184         tmp = num * 10 / denom;
 185         if (tmp % 10 >= 5)
 186                 pd->iccl = (u_int8_t)((num/denom) + 1);
 187         else
 188                 pd->iccl = (u_int8_t)(num/denom);
 189
 190         /* Calculate the value for icch. From the data sheet:
 191            icch = (p clock / transfer rate) * (H / (L + H)) */
 192         num = i2c_clk * 4;
 193         tmp = num * 10 / denom;
 194         if (tmp % 10 >= 5)
 195                 pd->icch = (u_int8_t)((num/denom) + 1);
 196         else
 197                 pd->icch = (u_int8_t)(num/denom);
 198
 199         /* Enable channel and configure rx ack */
 200         iowrite8(ioread8(ICCR(pd)) | ICCR_ICE, ICCR(pd));
 201
 202         /* Mask all interrupts */
 203         iowrite8(0, ICIC(pd));
 204
 205         /* Set the clock */
 206         iowrite8(pd->iccl, ICCL(pd));
 207         iowrite8(pd->icch, ICCH(pd));
 208 }
 209
 210 static void deactivate_ch(struct sh_mobile_i2c_data *pd)
 211 {
 212         /* Clear/disable interrupts */
 213         iowrite8(0, ICSR(pd));
 214         iowrite8(0, ICIC(pd));
 215
 216         /* Disable channel */
 217         iowrite8(ioread8(ICCR(pd)) & ~ICCR_ICE, ICCR(pd));
 218
 219         /* Disable clock and mark device as idle */
 220         clk_disable(pd->clk);
 221         pm_runtime_put_sync(pd->dev);
 222 }
 223
 224 static unsigned char i2c_op(struct sh_mobile_i2c_data *pd,
 225                             enum sh_mobile_i2c_op op, unsigned char data)
 226 {
 227         unsigned char ret = 0;
 228         unsigned long flags;
 229
 230         dev_dbg(pd->dev, "op %d, data in 0x%02x\n", op, data);
 231
 232         spin_lock_irqsave(&pd->lock, flags);
 233
 234         switch (op) {
 235         case OP_START: /* issue start and trigger DTE interrupt */
 236                 iowrite8(0x94, ICCR(pd));
 237                 break;
 238         case OP_TX_FIRST: /* disable DTE interrupt and write data */
 239                 iowrite8(ICIC_WAITE | ICIC_ALE | ICIC_TACKE, ICIC(pd));
 240                 iowrite8(data, ICDR(pd));
 241                 break;
 242         case OP_TX: /* write data */
 243                 iowrite8(data, ICDR(pd));
 244                 break;
 245         case OP_TX_STOP: /* write data and issue a stop afterwards */
 246                 iowrite8(data, ICDR(pd));
 247                 iowrite8(0x90, ICCR(pd));
 248                 break;
 249         case OP_TX_TO_RX: /* select read mode */
 250                 iowrite8(0x81, ICCR(pd));
 251                 break;
 252         case OP_RX: /* just read data */
 253                 ret = ioread8(ICDR(pd));
 254                 break;
 255         case OP_RX_STOP: /* enable DTE interrupt, issue stop */
 256                 iowrite8(ICIC_DTEE | ICIC_WAITE | ICIC_ALE | ICIC_TACKE,
 257                          ICIC(pd));
 258                 iowrite8(0xc0, ICCR(pd));
 259                 break;
 260         case OP_RX_STOP_DATA: /* enable DTE interrupt, read data, issue stop */
 261                 iowrite8(ICIC_DTEE | ICIC_WAITE | ICIC_ALE | ICIC_TACKE,
 262                          ICIC(pd));
 263                 ret = ioread8(ICDR(pd));
 264                 iowrite8(0xc0, ICCR(pd));
 265                 break;
 266         }
 267
 268         spin_unlock_irqrestore(&pd->lock, flags);
 269
 270         dev_dbg(pd->dev, "op %d, data out 0x%02x\n", op, ret);
 271         return ret;
 272 }
 273
 274 static int sh_mobile_i2c_is_first_byte(struct sh_mobile_i2c_data *pd)
 275 {
 276         if (pd->pos == -1)
 277                 return 1;
 278
 279         return 0;
 280 }
 281
 282 static int sh_mobile_i2c_is_last_byte(struct sh_mobile_i2c_data *pd)
 283 {
 284         if (pd->pos == (pd->msg->len - 1))
 285                 return 1;
 286
 287         return 0;
 288 }
 289
 290 static void sh_mobile_i2c_get_data(struct sh_mobile_i2c_data *pd,
 291                                    unsigned char *buf)
 292 {
 293         switch (pd->pos) {
 294         case -1:
 295                 *buf = (pd->msg->addr & 0x7f) << 1;
 296                 *buf |= (pd->msg->flags & I2C_M_RD) ? 1 : 0;
 297                 break;
 298         default:
 299                 *buf = pd->msg->buf[pd->pos];
 300         }
 301 }
 302
 303 static int sh_mobile_i2c_isr_tx(struct sh_mobile_i2c_data *pd)
 304 {
 305         unsigned char data;
 306
 307         if (pd->pos == pd->msg->len)
 308                 return 1;
 309
 310         sh_mobile_i2c_get_data(pd, &data);
 311
 312         if (sh_mobile_i2c_is_last_byte(pd))
 313                 i2c_op(pd, OP_TX_STOP, data);
 314         else if (sh_mobile_i2c_is_first_byte(pd))
 315                 i2c_op(pd, OP_TX_FIRST, data);
 316         else
 317                 i2c_op(pd, OP_TX, data);
 318
 319         pd->pos++;
 320         return 0;
 321 }
 322
 323 static int sh_mobile_i2c_isr_rx(struct sh_mobile_i2c_data *pd)
 324 {
 325         unsigned char data;
 326         int real_pos;
 327
 328         do {
 329                 if (pd->pos <= -1) {
 330                         sh_mobile_i2c_get_data(pd, &data);
 331
 332                         if (sh_mobile_i2c_is_first_byte(pd))
 333                                 i2c_op(pd, OP_TX_FIRST, data);
 334                         else
 335                                 i2c_op(pd, OP_TX, data);
 336                         break;
 337                 }
 338
 339                 if (pd->pos == 0) {
 340                         i2c_op(pd, OP_TX_TO_RX, 0);
 341                         break;
 342                 }
 343
 344                 real_pos = pd->pos - 2;
 345
 346                 if (pd->pos == pd->msg->len) {
 347                         if (real_pos < 0) {
 348                                 i2c_op(pd, OP_RX_STOP, 0);
 349                                 break;
 350                         }
 351                         data = i2c_op(pd, OP_RX_STOP_DATA, 0);
 352                 } else
 353                         data = i2c_op(pd, OP_RX, 0);
 354
 355                 if (real_pos >= 0)
 356                         pd->msg->buf[real_pos] = data;
 357         } while (0);
 358
 359         pd->pos++;
 360         return pd->pos == (pd->msg->len + 2);
 361 }
 362
 363 static irqreturn_t sh_mobile_i2c_isr(int irq, void *dev_id)
 364 {
 365         struct platform_device *dev = dev_id;
 366         struct sh_mobile_i2c_data *pd = platform_get_drvdata(dev);
 367         unsigned char sr;
 368         int wakeup;
 369
 370         sr = ioread8(ICSR(pd));
 371         pd->sr |= sr; /* remember state */
 372
 373         dev_dbg(pd->dev, "i2c_isr 0x%02x 0x%02x %s %d %d!\n", sr, pd->sr,
 374                (pd->msg->flags & I2C_M_RD) ? "read" : "write",
 375                pd->pos, pd->msg->len);
 376
 377         if (sr & (ICSR_AL | ICSR_TACK)) {
 378                 /* don't interrupt transaction - continue to issue stop */
 379                 iowrite8(sr & ~(ICSR_AL | ICSR_TACK), ICSR(pd));
 380                 wakeup = 0;
 381         } else if (pd->msg->flags & I2C_M_RD)
 382                 wakeup = sh_mobile_i2c_isr_rx(pd);
 383         else
 384                 wakeup = sh_mobile_i2c_isr_tx(pd);
 385
 386         if (sr & ICSR_WAIT) /* TODO: add delay here to support slow acks */
 387                 iowrite8(sr & ~ICSR_WAIT, ICSR(pd));
 388
 389         if (wakeup) {
 390                 pd->sr |= SW_DONE;
 391                 wake_up(&pd->wait);
 392         }
 393
 394         return IRQ_HANDLED;
 395 }
 396
 397 static int start_ch(struct sh_mobile_i2c_data *pd, struct i2c_msg *usr_msg)
 398 {
 399         if (usr_msg->len == 0 && (usr_msg->flags & I2C_M_RD)) {
 400                 dev_err(pd->dev, "Unsupported zero length i2c read\n");
 401                 return -EIO;
 402         }
 403
 404         /* Initialize channel registers */
 405         iowrite8(ioread8(ICCR(pd)) & ~ICCR_ICE, ICCR(pd));
 406
 407         /* Enable channel and configure rx ack */
 408         iowrite8(ioread8(ICCR(pd)) | ICCR_ICE, ICCR(pd));
 409
 410         /* Set the clock */
 411         iowrite8(pd->iccl, ICCL(pd));
 412         iowrite8(pd->icch, ICCH(pd));
 413
 414         pd->msg = usr_msg;
 415         pd->pos = -1;
 416         pd->sr = 0;
 417
 418         /* Enable all interrupts to begin with */
 419         iowrite8(ICIC_WAITE | ICIC_ALE | ICIC_TACKE | ICIC_DTEE, ICIC(pd));
 420         return 0;
 421 }
 422
 423 static int sh_mobile_i2c_xfer(struct i2c_adapter *adapter,
 424                               struct i2c_msg *msgs,
 425                               int num)
 426 {
 427         struct sh_mobile_i2c_data *pd = i2c_get_adapdata(adapter);
 428         struct i2c_msg  *msg;
 429         int err = 0;
 430         u_int8_t val;
 431         int i, k, retry_count;
 432
 433         activate_ch(pd);
 434
 435         /* Process all messages */
 436         for (i = 0; i < num; i++) {
 437                 msg = &msgs[i];
 438
 439                 err = start_ch(pd, msg);
 440                 if (err)
 441                         break;
 442
 443                 i2c_op(pd, OP_START, 0);
 444
 445                 /* The interrupt handler takes care of the rest... */
 446                 k = wait_event_timeout(pd->wait,
 447                                        pd->sr & (ICSR_TACK | SW_DONE),
 448                                        5 * HZ);
 449                 if (!k)
 450                         dev_err(pd->dev, "Transfer request timed out\n");
 451
 452                 retry_count = 1000;
 453 again:
 454                 val = ioread8(ICSR(pd));
 455
 456                 dev_dbg(pd->dev, "val 0x%02x pd->sr 0x%02x\n", val, pd->sr);
 457
 458                 /* the interrupt handler may wake us up before the
 459                  * transfer is finished, so poll the hardware
 460                  * until we're done.
 461                  */
 462                 if (val & ICSR_BUSY) {
 463                         udelay(10);
 464                         if (retry_count--)
 465                                 goto again;
 466
 467                         err = -EIO;
 468                         dev_err(pd->dev, "Polling timed out\n");
 469                         break;
 470                 }
 471
 472                 /* handle missing acknowledge and arbitration lost */
 473                 if ((val | pd->sr) & (ICSR_TACK | ICSR_AL)) {
 474                         err = -EIO;
 475                         break;
 476                 }
 477         }
 478
 479         deactivate_ch(pd);
 480
 481         if (!err)
 482                 err = num;
 483         return err;
 484 }
 485
 486 static u32 sh_mobile_i2c_func(struct i2c_adapter *adapter)
 487 {
 488         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
 489 }
 490
 491 static struct i2c_algorithm sh_mobile_i2c_algorithm = {
 492         .functionality  = sh_mobile_i2c_func,
 493         .master_xfer    = sh_mobile_i2c_xfer,
 494 };
 495
 496 static int sh_mobile_i2c_hook_irqs(struct platform_device *dev, int hook)
 497 {
 498         struct resource *res;
 499         int ret = -ENXIO;
 500         int q, m;
 501         int k = 0;
 502         int n = 0;
 503
 504         while ((res = platform_get_resource(dev, IORESOURCE_IRQ, k))) {
 505                 for (n = res->start; hook && n <= res->end; n++) {
 506                         if (request_irq(n, sh_mobile_i2c_isr, IRQF_DISABLED,
 507                                         dev_name(&dev->dev), dev))
 508                                 goto rollback;
 509                 }
 510                 k++;
 511         }
 512
 513         if (hook)
 514                 return k > 0 ? 0 : -ENOENT;
 515
 516         k--;
 517         ret = 0;
 518
 519  rollback:
 520         for (q = k; k >= 0; k--) {
 521                 for (m = n; m >= res->start; m--)
 522                         free_irq(m, dev);
 523
 524                 res = platform_get_resource(dev, IORESOURCE_IRQ, k - 1);
 525                 m = res->end;
 526         }
 527
 528         return ret;
 529 }
 530
 531 static int sh_mobile_i2c_probe(struct platform_device *dev)
 532 {
 533         struct sh_mobile_i2c_data *pd;
 534         struct i2c_adapter *adap;
 535         struct resource *res;
 536         char clk_name[8];
 537         int size;
 538         int ret;
 539
 540         pd = kzalloc(sizeof(struct sh_mobile_i2c_data), GFP_KERNEL);
 541         if (pd == NULL) {
 542                 dev_err(&dev->dev, "cannot allocate private data\n");
 543                 return -ENOMEM;
 544         }
 545
 546         snprintf(clk_name, sizeof(clk_name), "i2c%d", dev->id);
 547         pd->clk = clk_get(&dev->dev, clk_name);
 548         if (IS_ERR(pd->clk)) {
 549                 dev_err(&dev->dev, "cannot get clock \"%s\"\n", clk_name);
 550                 ret = PTR_ERR(pd->clk);
 551                 goto err;
 552         }
 553
 554         ret = sh_mobile_i2c_hook_irqs(dev, 1);
 555         if (ret) {
 556                 dev_err(&dev->dev, "cannot request IRQ\n");
 557                 goto err_clk;
 558         }
 559
 560         pd->dev = &dev->dev;
 561         platform_set_drvdata(dev, pd);
 562
 563         res = platform_get_resource(dev, IORESOURCE_MEM, 0);
 564         if (res == NULL) {
 565                 dev_err(&dev->dev, "cannot find IO resource\n");
 566                 ret = -ENOENT;
 567                 goto err_irq;
 568         }
 569
 570         size = resource_size(res);
 571
 572         pd->reg = ioremap(res->start, size);
 573         if (pd->reg == NULL) {
 574                 dev_err(&dev->dev, "cannot map IO\n");
 575                 ret = -ENXIO;
 576                 goto err_irq;
 577         }
 578
 579         /* Enable Runtime PM for this device.
 580          *
 581          * Also tell the Runtime PM core to ignore children
 582          * for this device since it is valid for us to suspend
 583          * this I2C master driver even though the slave devices
 584          * on the I2C bus may not be suspended.
 585          *
 586          * The state of the I2C hardware bus is unaffected by
 587          * the Runtime PM state.
 588          */
 589         pm_suspend_ignore_children(&dev->dev, true);
 590         pm_runtime_enable(&dev->dev);
 591
 592         /* setup the private data */
 593         adap = &pd->adap;
 594         i2c_set_adapdata(adap, pd);
 595
 596         adap->owner = THIS_MODULE;
 597         adap->algo = &sh_mobile_i2c_algorithm;
 598         adap->dev.parent = &dev->dev;
 599         adap->retries = 5;
 600         adap->nr = dev->id;
 601
 602         strlcpy(adap->name, dev->name, sizeof(adap->name));
 603
 604         spin_lock_init(&pd->lock);
 605         init_waitqueue_head(&pd->wait);
 606
 607         ret = i2c_add_numbered_adapter(adap);
 608         if (ret < 0) {
 609                 dev_err(&dev->dev, "cannot add numbered adapter\n");
 610                 goto err_all;
 611         }
 612
 613         return 0;
 614
 615  err_all:
 616         iounmap(pd->reg);
 617  err_irq:
 618         sh_mobile_i2c_hook_irqs(dev, 0);
 619  err_clk:
 620         clk_put(pd->clk);
 621  err:
 622         kfree(pd);
 623         return ret;
 624 }
 625
 626 static int sh_mobile_i2c_remove(struct platform_device *dev)
 627 {
 628         struct sh_mobile_i2c_data *pd = platform_get_drvdata(dev);
 629
 630         i2c_del_adapter(&pd->adap);
 631         iounmap(pd->reg);
 632         sh_mobile_i2c_hook_irqs(dev, 0);
 633         clk_put(pd->clk);
 634         pm_runtime_disable(&dev->dev);
 635         kfree(pd);
 636         return 0;
 637 }
 638
 639 static int sh_mobile_i2c_runtime_nop(struct device *dev)
 640 {
 641         /* Runtime PM callback shared between ->runtime_suspend()
 642          * and ->runtime_resume(). Simply returns success.
 643          *
 644          * This driver re-initializes all registers after
 645          * pm_runtime_get_sync() anyway so there is no need
 646          * to save and restore registers here.
 647          */
 648         return 0;
 649 }
 650
 651 static const struct dev_pm_ops sh_mobile_i2c_dev_pm_ops = {
 652         .runtime_suspend = sh_mobile_i2c_runtime_nop,
 653         .runtime_resume = sh_mobile_i2c_runtime_nop,
 654 };
 655
 656 static struct platform_driver sh_mobile_i2c_driver = {
 657         .driver         = {
 658                 .name           = "i2c-sh_mobile",
 659                 .owner          = THIS_MODULE,
 660                 .pm             = &sh_mobile_i2c_dev_pm_ops,
 661         },
 662         .probe          = sh_mobile_i2c_probe,
 663         .remove         = sh_mobile_i2c_remove,
 664 };
 665
 666 static int __init sh_mobile_i2c_adap_init(void)
 667 {
 668         return platform_driver_register(&sh_mobile_i2c_driver);
 669 }
 670
 671 static void __exit sh_mobile_i2c_adap_exit(void)
 672 {
 673         platform_driver_unregister(&sh_mobile_i2c_driver);
 674 }
 675
 676 subsys_initcall(sh_mobile_i2c_adap_init);
 677 module_exit(sh_mobile_i2c_adap_exit);
 678
 679 MODULE_DESCRIPTION("SuperH Mobile I2C Bus Controller driver");
 680 MODULE_AUTHOR("Magnus Damm");
 681 MODULE_LICENSE("GPL v2");