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[mirror_ubuntu-focal-kernel.git] / drivers / i2c / busses / i2c-stm32f7.c
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Driver for STMicroelectronics STM32F7 I2C controller
4 *
5 * This I2C controller is described in the STM32F75xxx and STM32F74xxx Soc
6 * reference manual.
7 * Please see below a link to the documentation:
8 * http://www.st.com/resource/en/reference_manual/dm00124865.pdf
9 *
10 * Copyright (C) M'boumba Cedric Madianga 2017
11 * Copyright (C) STMicroelectronics 2017
12 * Author: M'boumba Cedric Madianga <cedric.madianga@gmail.com>
13 *
14 * This driver is based on i2c-stm32f4.c
15 *
16 */
17 #include <linux/clk.h>
18 #include <linux/delay.h>
19 #include <linux/err.h>
20 #include <linux/i2c.h>
21 #include <linux/interrupt.h>
22 #include <linux/io.h>
23 #include <linux/iopoll.h>
24 #include <linux/mfd/syscon.h>
25 #include <linux/module.h>
26 #include <linux/of.h>
27 #include <linux/of_address.h>
28 #include <linux/of_platform.h>
29 #include <linux/platform_device.h>
30 #include <linux/pinctrl/consumer.h>
31 #include <linux/pm_runtime.h>
32 #include <linux/regmap.h>
33 #include <linux/reset.h>
34 #include <linux/slab.h>
35
36 #include "i2c-stm32.h"
37
38 /* STM32F7 I2C registers */
39 #define STM32F7_I2C_CR1 0x00
40 #define STM32F7_I2C_CR2 0x04
41 #define STM32F7_I2C_OAR1 0x08
42 #define STM32F7_I2C_OAR2 0x0C
43 #define STM32F7_I2C_PECR 0x20
44 #define STM32F7_I2C_TIMINGR 0x10
45 #define STM32F7_I2C_ISR 0x18
46 #define STM32F7_I2C_ICR 0x1C
47 #define STM32F7_I2C_RXDR 0x24
48 #define STM32F7_I2C_TXDR 0x28
49
50 /* STM32F7 I2C control 1 */
51 #define STM32F7_I2C_CR1_PECEN BIT(23)
52 #define STM32F7_I2C_CR1_SBC BIT(16)
53 #define STM32F7_I2C_CR1_RXDMAEN BIT(15)
54 #define STM32F7_I2C_CR1_TXDMAEN BIT(14)
55 #define STM32F7_I2C_CR1_ANFOFF BIT(12)
56 #define STM32F7_I2C_CR1_DNF_MASK GENMASK(11, 8)
57 #define STM32F7_I2C_CR1_DNF(n) (((n) & 0xf) << 8)
58 #define STM32F7_I2C_CR1_ERRIE BIT(7)
59 #define STM32F7_I2C_CR1_TCIE BIT(6)
60 #define STM32F7_I2C_CR1_STOPIE BIT(5)
61 #define STM32F7_I2C_CR1_NACKIE BIT(4)
62 #define STM32F7_I2C_CR1_ADDRIE BIT(3)
63 #define STM32F7_I2C_CR1_RXIE BIT(2)
64 #define STM32F7_I2C_CR1_TXIE BIT(1)
65 #define STM32F7_I2C_CR1_PE BIT(0)
66 #define STM32F7_I2C_ALL_IRQ_MASK (STM32F7_I2C_CR1_ERRIE \
67 | STM32F7_I2C_CR1_TCIE \
68 | STM32F7_I2C_CR1_STOPIE \
69 | STM32F7_I2C_CR1_NACKIE \
70 | STM32F7_I2C_CR1_RXIE \
71 | STM32F7_I2C_CR1_TXIE)
72 #define STM32F7_I2C_XFER_IRQ_MASK (STM32F7_I2C_CR1_TCIE \
73 | STM32F7_I2C_CR1_STOPIE \
74 | STM32F7_I2C_CR1_NACKIE \
75 | STM32F7_I2C_CR1_RXIE \
76 | STM32F7_I2C_CR1_TXIE)
77
78 /* STM32F7 I2C control 2 */
79 #define STM32F7_I2C_CR2_PECBYTE BIT(26)
80 #define STM32F7_I2C_CR2_RELOAD BIT(24)
81 #define STM32F7_I2C_CR2_NBYTES_MASK GENMASK(23, 16)
82 #define STM32F7_I2C_CR2_NBYTES(n) (((n) & 0xff) << 16)
83 #define STM32F7_I2C_CR2_NACK BIT(15)
84 #define STM32F7_I2C_CR2_STOP BIT(14)
85 #define STM32F7_I2C_CR2_START BIT(13)
86 #define STM32F7_I2C_CR2_HEAD10R BIT(12)
87 #define STM32F7_I2C_CR2_ADD10 BIT(11)
88 #define STM32F7_I2C_CR2_RD_WRN BIT(10)
89 #define STM32F7_I2C_CR2_SADD10_MASK GENMASK(9, 0)
90 #define STM32F7_I2C_CR2_SADD10(n) (((n) & \
91 STM32F7_I2C_CR2_SADD10_MASK))
92 #define STM32F7_I2C_CR2_SADD7_MASK GENMASK(7, 1)
93 #define STM32F7_I2C_CR2_SADD7(n) (((n) & 0x7f) << 1)
94
95 /* STM32F7 I2C Own Address 1 */
96 #define STM32F7_I2C_OAR1_OA1EN BIT(15)
97 #define STM32F7_I2C_OAR1_OA1MODE BIT(10)
98 #define STM32F7_I2C_OAR1_OA1_10_MASK GENMASK(9, 0)
99 #define STM32F7_I2C_OAR1_OA1_10(n) (((n) & \
100 STM32F7_I2C_OAR1_OA1_10_MASK))
101 #define STM32F7_I2C_OAR1_OA1_7_MASK GENMASK(7, 1)
102 #define STM32F7_I2C_OAR1_OA1_7(n) (((n) & 0x7f) << 1)
103 #define STM32F7_I2C_OAR1_MASK (STM32F7_I2C_OAR1_OA1_7_MASK \
104 | STM32F7_I2C_OAR1_OA1_10_MASK \
105 | STM32F7_I2C_OAR1_OA1EN \
106 | STM32F7_I2C_OAR1_OA1MODE)
107
108 /* STM32F7 I2C Own Address 2 */
109 #define STM32F7_I2C_OAR2_OA2EN BIT(15)
110 #define STM32F7_I2C_OAR2_OA2MSK_MASK GENMASK(10, 8)
111 #define STM32F7_I2C_OAR2_OA2MSK(n) (((n) & 0x7) << 8)
112 #define STM32F7_I2C_OAR2_OA2_7_MASK GENMASK(7, 1)
113 #define STM32F7_I2C_OAR2_OA2_7(n) (((n) & 0x7f) << 1)
114 #define STM32F7_I2C_OAR2_MASK (STM32F7_I2C_OAR2_OA2MSK_MASK \
115 | STM32F7_I2C_OAR2_OA2_7_MASK \
116 | STM32F7_I2C_OAR2_OA2EN)
117
118 /* STM32F7 I2C Interrupt Status */
119 #define STM32F7_I2C_ISR_ADDCODE_MASK GENMASK(23, 17)
120 #define STM32F7_I2C_ISR_ADDCODE_GET(n) \
121 (((n) & STM32F7_I2C_ISR_ADDCODE_MASK) >> 17)
122 #define STM32F7_I2C_ISR_DIR BIT(16)
123 #define STM32F7_I2C_ISR_BUSY BIT(15)
124 #define STM32F7_I2C_ISR_PECERR BIT(11)
125 #define STM32F7_I2C_ISR_ARLO BIT(9)
126 #define STM32F7_I2C_ISR_BERR BIT(8)
127 #define STM32F7_I2C_ISR_TCR BIT(7)
128 #define STM32F7_I2C_ISR_TC BIT(6)
129 #define STM32F7_I2C_ISR_STOPF BIT(5)
130 #define STM32F7_I2C_ISR_NACKF BIT(4)
131 #define STM32F7_I2C_ISR_ADDR BIT(3)
132 #define STM32F7_I2C_ISR_RXNE BIT(2)
133 #define STM32F7_I2C_ISR_TXIS BIT(1)
134 #define STM32F7_I2C_ISR_TXE BIT(0)
135
136 /* STM32F7 I2C Interrupt Clear */
137 #define STM32F7_I2C_ICR_PECCF BIT(11)
138 #define STM32F7_I2C_ICR_ARLOCF BIT(9)
139 #define STM32F7_I2C_ICR_BERRCF BIT(8)
140 #define STM32F7_I2C_ICR_STOPCF BIT(5)
141 #define STM32F7_I2C_ICR_NACKCF BIT(4)
142 #define STM32F7_I2C_ICR_ADDRCF BIT(3)
143
144 /* STM32F7 I2C Timing */
145 #define STM32F7_I2C_TIMINGR_PRESC(n) (((n) & 0xf) << 28)
146 #define STM32F7_I2C_TIMINGR_SCLDEL(n) (((n) & 0xf) << 20)
147 #define STM32F7_I2C_TIMINGR_SDADEL(n) (((n) & 0xf) << 16)
148 #define STM32F7_I2C_TIMINGR_SCLH(n) (((n) & 0xff) << 8)
149 #define STM32F7_I2C_TIMINGR_SCLL(n) ((n) & 0xff)
150
151 #define STM32F7_I2C_MAX_LEN 0xff
152 #define STM32F7_I2C_DMA_LEN_MIN 0x16
153 #define STM32F7_I2C_MAX_SLAVE 0x2
154
155 #define STM32F7_I2C_DNF_DEFAULT 0
156 #define STM32F7_I2C_DNF_MAX 15
157
158 #define STM32F7_I2C_ANALOG_FILTER_ENABLE 1
159 #define STM32F7_I2C_ANALOG_FILTER_DELAY_MIN 50 /* ns */
160 #define STM32F7_I2C_ANALOG_FILTER_DELAY_MAX 260 /* ns */
161
162 #define STM32F7_I2C_RISE_TIME_DEFAULT 25 /* ns */
163 #define STM32F7_I2C_FALL_TIME_DEFAULT 10 /* ns */
164
165 #define STM32F7_PRESC_MAX BIT(4)
166 #define STM32F7_SCLDEL_MAX BIT(4)
167 #define STM32F7_SDADEL_MAX BIT(4)
168 #define STM32F7_SCLH_MAX BIT(8)
169 #define STM32F7_SCLL_MAX BIT(8)
170
171 #define STM32F7_AUTOSUSPEND_DELAY (HZ / 100)
172
173 /**
174 * struct stm32f7_i2c_spec - private i2c specification timing
175 * @rate: I2C bus speed (Hz)
176 * @rate_min: 80% of I2C bus speed (Hz)
177 * @rate_max: 100% of I2C bus speed (Hz)
178 * @fall_max: Max fall time of both SDA and SCL signals (ns)
179 * @rise_max: Max rise time of both SDA and SCL signals (ns)
180 * @hddat_min: Min data hold time (ns)
181 * @vddat_max: Max data valid time (ns)
182 * @sudat_min: Min data setup time (ns)
183 * @l_min: Min low period of the SCL clock (ns)
184 * @h_min: Min high period of the SCL clock (ns)
185 */
186 struct stm32f7_i2c_spec {
187 u32 rate;
188 u32 rate_min;
189 u32 rate_max;
190 u32 fall_max;
191 u32 rise_max;
192 u32 hddat_min;
193 u32 vddat_max;
194 u32 sudat_min;
195 u32 l_min;
196 u32 h_min;
197 };
198
199 /**
200 * struct stm32f7_i2c_setup - private I2C timing setup parameters
201 * @speed: I2C speed mode (standard, Fast Plus)
202 * @speed_freq: I2C speed frequency (Hz)
203 * @clock_src: I2C clock source frequency (Hz)
204 * @rise_time: Rise time (ns)
205 * @fall_time: Fall time (ns)
206 * @dnf: Digital filter coefficient (0-16)
207 * @analog_filter: Analog filter delay (On/Off)
208 */
209 struct stm32f7_i2c_setup {
210 enum stm32_i2c_speed speed;
211 u32 speed_freq;
212 u32 clock_src;
213 u32 rise_time;
214 u32 fall_time;
215 u8 dnf;
216 bool analog_filter;
217 };
218
219 /**
220 * struct stm32f7_i2c_timings - private I2C output parameters
221 * @node: List entry
222 * @presc: Prescaler value
223 * @scldel: Data setup time
224 * @sdadel: Data hold time
225 * @sclh: SCL high period (master mode)
226 * @scll: SCL low period (master mode)
227 */
228 struct stm32f7_i2c_timings {
229 struct list_head node;
230 u8 presc;
231 u8 scldel;
232 u8 sdadel;
233 u8 sclh;
234 u8 scll;
235 };
236
237 /**
238 * struct stm32f7_i2c_msg - client specific data
239 * @addr: 8-bit or 10-bit slave addr, including r/w bit
240 * @count: number of bytes to be transferred
241 * @buf: data buffer
242 * @result: result of the transfer
243 * @stop: last I2C msg to be sent, i.e. STOP to be generated
244 * @smbus: boolean to know if the I2C IP is used in SMBus mode
245 * @size: type of SMBus protocol
246 * @read_write: direction of SMBus protocol
247 * SMBus block read and SMBus block write - block read process call protocols
248 * @smbus_buf: buffer to be used for SMBus protocol transfer. It will
249 * contain a maximum of 32 bytes of data + byte command + byte count + PEC
250 * This buffer has to be 32-bit aligned to be compliant with memory address
251 * register in DMA mode.
252 */
253 struct stm32f7_i2c_msg {
254 u16 addr;
255 u32 count;
256 u8 *buf;
257 int result;
258 bool stop;
259 bool smbus;
260 int size;
261 char read_write;
262 u8 smbus_buf[I2C_SMBUS_BLOCK_MAX + 3] __aligned(4);
263 };
264
265 /**
266 * struct stm32f7_i2c_dev - private data of the controller
267 * @adap: I2C adapter for this controller
268 * @dev: device for this controller
269 * @base: virtual memory area
270 * @complete: completion of I2C message
271 * @clk: hw i2c clock
272 * @speed: I2C clock frequency of the controller. Standard, Fast or Fast+
273 * @msg: Pointer to data to be written
274 * @msg_num: number of I2C messages to be executed
275 * @msg_id: message identifiant
276 * @f7_msg: customized i2c msg for driver usage
277 * @setup: I2C timing input setup
278 * @timing: I2C computed timings
279 * @slave: list of slave devices registered on the I2C bus
280 * @slave_running: slave device currently used
281 * @slave_dir: transfer direction for the current slave device
282 * @master_mode: boolean to know in which mode the I2C is running (master or
283 * slave)
284 * @dma: dma data
285 * @use_dma: boolean to know if dma is used in the current transfer
286 * @regmap: holds SYSCFG phandle for Fast Mode Plus bits
287 */
288 struct stm32f7_i2c_dev {
289 struct i2c_adapter adap;
290 struct device *dev;
291 void __iomem *base;
292 struct completion complete;
293 struct clk *clk;
294 int speed;
295 struct i2c_msg *msg;
296 unsigned int msg_num;
297 unsigned int msg_id;
298 struct stm32f7_i2c_msg f7_msg;
299 struct stm32f7_i2c_setup setup;
300 struct stm32f7_i2c_timings timing;
301 struct i2c_client *slave[STM32F7_I2C_MAX_SLAVE];
302 struct i2c_client *slave_running;
303 u32 slave_dir;
304 bool master_mode;
305 struct stm32_i2c_dma *dma;
306 bool use_dma;
307 struct regmap *regmap;
308 };
309
310 /*
311 * All these values are coming from I2C Specification, Version 6.0, 4th of
312 * April 2014.
313 *
314 * Table10. Characteristics of the SDA and SCL bus lines for Standard, Fast,
315 * and Fast-mode Plus I2C-bus devices
316 */
317 static struct stm32f7_i2c_spec i2c_specs[] = {
318 [STM32_I2C_SPEED_STANDARD] = {
319 .rate = 100000,
320 .rate_min = 80000,
321 .rate_max = 100000,
322 .fall_max = 300,
323 .rise_max = 1000,
324 .hddat_min = 0,
325 .vddat_max = 3450,
326 .sudat_min = 250,
327 .l_min = 4700,
328 .h_min = 4000,
329 },
330 [STM32_I2C_SPEED_FAST] = {
331 .rate = 400000,
332 .rate_min = 320000,
333 .rate_max = 400000,
334 .fall_max = 300,
335 .rise_max = 300,
336 .hddat_min = 0,
337 .vddat_max = 900,
338 .sudat_min = 100,
339 .l_min = 1300,
340 .h_min = 600,
341 },
342 [STM32_I2C_SPEED_FAST_PLUS] = {
343 .rate = 1000000,
344 .rate_min = 800000,
345 .rate_max = 1000000,
346 .fall_max = 100,
347 .rise_max = 120,
348 .hddat_min = 0,
349 .vddat_max = 450,
350 .sudat_min = 50,
351 .l_min = 500,
352 .h_min = 260,
353 },
354 };
355
356 static const struct stm32f7_i2c_setup stm32f7_setup = {
357 .rise_time = STM32F7_I2C_RISE_TIME_DEFAULT,
358 .fall_time = STM32F7_I2C_FALL_TIME_DEFAULT,
359 .dnf = STM32F7_I2C_DNF_DEFAULT,
360 .analog_filter = STM32F7_I2C_ANALOG_FILTER_ENABLE,
361 };
362
363 static inline void stm32f7_i2c_set_bits(void __iomem *reg, u32 mask)
364 {
365 writel_relaxed(readl_relaxed(reg) | mask, reg);
366 }
367
368 static inline void stm32f7_i2c_clr_bits(void __iomem *reg, u32 mask)
369 {
370 writel_relaxed(readl_relaxed(reg) & ~mask, reg);
371 }
372
373 static void stm32f7_i2c_disable_irq(struct stm32f7_i2c_dev *i2c_dev, u32 mask)
374 {
375 stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1, mask);
376 }
377
378 static int stm32f7_i2c_compute_timing(struct stm32f7_i2c_dev *i2c_dev,
379 struct stm32f7_i2c_setup *setup,
380 struct stm32f7_i2c_timings *output)
381 {
382 u32 p_prev = STM32F7_PRESC_MAX;
383 u32 i2cclk = DIV_ROUND_CLOSEST(NSEC_PER_SEC,
384 setup->clock_src);
385 u32 i2cbus = DIV_ROUND_CLOSEST(NSEC_PER_SEC,
386 setup->speed_freq);
387 u32 clk_error_prev = i2cbus;
388 u32 tsync;
389 u32 af_delay_min, af_delay_max;
390 u32 dnf_delay;
391 u32 clk_min, clk_max;
392 int sdadel_min, sdadel_max;
393 int scldel_min;
394 struct stm32f7_i2c_timings *v, *_v, *s;
395 struct list_head solutions;
396 u16 p, l, a, h;
397 int ret = 0;
398
399 if (setup->speed >= STM32_I2C_SPEED_END) {
400 dev_err(i2c_dev->dev, "speed out of bound {%d/%d}\n",
401 setup->speed, STM32_I2C_SPEED_END - 1);
402 return -EINVAL;
403 }
404
405 if ((setup->rise_time > i2c_specs[setup->speed].rise_max) ||
406 (setup->fall_time > i2c_specs[setup->speed].fall_max)) {
407 dev_err(i2c_dev->dev,
408 "timings out of bound Rise{%d>%d}/Fall{%d>%d}\n",
409 setup->rise_time, i2c_specs[setup->speed].rise_max,
410 setup->fall_time, i2c_specs[setup->speed].fall_max);
411 return -EINVAL;
412 }
413
414 if (setup->dnf > STM32F7_I2C_DNF_MAX) {
415 dev_err(i2c_dev->dev,
416 "DNF out of bound %d/%d\n",
417 setup->dnf, STM32F7_I2C_DNF_MAX);
418 return -EINVAL;
419 }
420
421 if (setup->speed_freq > i2c_specs[setup->speed].rate) {
422 dev_err(i2c_dev->dev, "ERROR: Freq {%d/%d}\n",
423 setup->speed_freq, i2c_specs[setup->speed].rate);
424 return -EINVAL;
425 }
426
427 /* Analog and Digital Filters */
428 af_delay_min =
429 (setup->analog_filter ?
430 STM32F7_I2C_ANALOG_FILTER_DELAY_MIN : 0);
431 af_delay_max =
432 (setup->analog_filter ?
433 STM32F7_I2C_ANALOG_FILTER_DELAY_MAX : 0);
434 dnf_delay = setup->dnf * i2cclk;
435
436 sdadel_min = i2c_specs[setup->speed].hddat_min + setup->fall_time -
437 af_delay_min - (setup->dnf + 3) * i2cclk;
438
439 sdadel_max = i2c_specs[setup->speed].vddat_max - setup->rise_time -
440 af_delay_max - (setup->dnf + 4) * i2cclk;
441
442 scldel_min = setup->rise_time + i2c_specs[setup->speed].sudat_min;
443
444 if (sdadel_min < 0)
445 sdadel_min = 0;
446 if (sdadel_max < 0)
447 sdadel_max = 0;
448
449 dev_dbg(i2c_dev->dev, "SDADEL(min/max): %i/%i, SCLDEL(Min): %i\n",
450 sdadel_min, sdadel_max, scldel_min);
451
452 INIT_LIST_HEAD(&solutions);
453 /* Compute possible values for PRESC, SCLDEL and SDADEL */
454 for (p = 0; p < STM32F7_PRESC_MAX; p++) {
455 for (l = 0; l < STM32F7_SCLDEL_MAX; l++) {
456 u32 scldel = (l + 1) * (p + 1) * i2cclk;
457
458 if (scldel < scldel_min)
459 continue;
460
461 for (a = 0; a < STM32F7_SDADEL_MAX; a++) {
462 u32 sdadel = (a * (p + 1) + 1) * i2cclk;
463
464 if (((sdadel >= sdadel_min) &&
465 (sdadel <= sdadel_max)) &&
466 (p != p_prev)) {
467 v = kmalloc(sizeof(*v), GFP_KERNEL);
468 if (!v) {
469 ret = -ENOMEM;
470 goto exit;
471 }
472
473 v->presc = p;
474 v->scldel = l;
475 v->sdadel = a;
476 p_prev = p;
477
478 list_add_tail(&v->node,
479 &solutions);
480 break;
481 }
482 }
483
484 if (p_prev == p)
485 break;
486 }
487 }
488
489 if (list_empty(&solutions)) {
490 dev_err(i2c_dev->dev, "no Prescaler solution\n");
491 ret = -EPERM;
492 goto exit;
493 }
494
495 tsync = af_delay_min + dnf_delay + (2 * i2cclk);
496 s = NULL;
497 clk_max = NSEC_PER_SEC / i2c_specs[setup->speed].rate_min;
498 clk_min = NSEC_PER_SEC / i2c_specs[setup->speed].rate_max;
499
500 /*
501 * Among Prescaler possibilities discovered above figures out SCL Low
502 * and High Period. Provided:
503 * - SCL Low Period has to be higher than SCL Clock Low Period
504 * defined by I2C Specification. I2C Clock has to be lower than
505 * (SCL Low Period - Analog/Digital filters) / 4.
506 * - SCL High Period has to be lower than SCL Clock High Period
507 * defined by I2C Specification
508 * - I2C Clock has to be lower than SCL High Period
509 */
510 list_for_each_entry(v, &solutions, node) {
511 u32 prescaler = (v->presc + 1) * i2cclk;
512
513 for (l = 0; l < STM32F7_SCLL_MAX; l++) {
514 u32 tscl_l = (l + 1) * prescaler + tsync;
515
516 if ((tscl_l < i2c_specs[setup->speed].l_min) ||
517 (i2cclk >=
518 ((tscl_l - af_delay_min - dnf_delay) / 4))) {
519 continue;
520 }
521
522 for (h = 0; h < STM32F7_SCLH_MAX; h++) {
523 u32 tscl_h = (h + 1) * prescaler + tsync;
524 u32 tscl = tscl_l + tscl_h +
525 setup->rise_time + setup->fall_time;
526
527 if ((tscl >= clk_min) && (tscl <= clk_max) &&
528 (tscl_h >= i2c_specs[setup->speed].h_min) &&
529 (i2cclk < tscl_h)) {
530 int clk_error = tscl - i2cbus;
531
532 if (clk_error < 0)
533 clk_error = -clk_error;
534
535 if (clk_error < clk_error_prev) {
536 clk_error_prev = clk_error;
537 v->scll = l;
538 v->sclh = h;
539 s = v;
540 }
541 }
542 }
543 }
544 }
545
546 if (!s) {
547 dev_err(i2c_dev->dev, "no solution at all\n");
548 ret = -EPERM;
549 goto exit;
550 }
551
552 output->presc = s->presc;
553 output->scldel = s->scldel;
554 output->sdadel = s->sdadel;
555 output->scll = s->scll;
556 output->sclh = s->sclh;
557
558 dev_dbg(i2c_dev->dev,
559 "Presc: %i, scldel: %i, sdadel: %i, scll: %i, sclh: %i\n",
560 output->presc,
561 output->scldel, output->sdadel,
562 output->scll, output->sclh);
563
564 exit:
565 /* Release list and memory */
566 list_for_each_entry_safe(v, _v, &solutions, node) {
567 list_del(&v->node);
568 kfree(v);
569 }
570
571 return ret;
572 }
573
574 static int stm32f7_i2c_setup_timing(struct stm32f7_i2c_dev *i2c_dev,
575 struct stm32f7_i2c_setup *setup)
576 {
577 int ret = 0;
578
579 setup->speed = i2c_dev->speed;
580 setup->speed_freq = i2c_specs[setup->speed].rate;
581 setup->clock_src = clk_get_rate(i2c_dev->clk);
582
583 if (!setup->clock_src) {
584 dev_err(i2c_dev->dev, "clock rate is 0\n");
585 return -EINVAL;
586 }
587
588 do {
589 ret = stm32f7_i2c_compute_timing(i2c_dev, setup,
590 &i2c_dev->timing);
591 if (ret) {
592 dev_err(i2c_dev->dev,
593 "failed to compute I2C timings.\n");
594 if (i2c_dev->speed > STM32_I2C_SPEED_STANDARD) {
595 i2c_dev->speed--;
596 setup->speed = i2c_dev->speed;
597 setup->speed_freq =
598 i2c_specs[setup->speed].rate;
599 dev_warn(i2c_dev->dev,
600 "downgrade I2C Speed Freq to (%i)\n",
601 i2c_specs[setup->speed].rate);
602 } else {
603 break;
604 }
605 }
606 } while (ret);
607
608 if (ret) {
609 dev_err(i2c_dev->dev, "Impossible to compute I2C timings.\n");
610 return ret;
611 }
612
613 dev_dbg(i2c_dev->dev, "I2C Speed(%i), Freq(%i), Clk Source(%i)\n",
614 setup->speed, setup->speed_freq, setup->clock_src);
615 dev_dbg(i2c_dev->dev, "I2C Rise(%i) and Fall(%i) Time\n",
616 setup->rise_time, setup->fall_time);
617 dev_dbg(i2c_dev->dev, "I2C Analog Filter(%s), DNF(%i)\n",
618 (setup->analog_filter ? "On" : "Off"), setup->dnf);
619
620 return 0;
621 }
622
623 static void stm32f7_i2c_disable_dma_req(struct stm32f7_i2c_dev *i2c_dev)
624 {
625 void __iomem *base = i2c_dev->base;
626 u32 mask = STM32F7_I2C_CR1_RXDMAEN | STM32F7_I2C_CR1_TXDMAEN;
627
628 stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR1, mask);
629 }
630
631 static void stm32f7_i2c_dma_callback(void *arg)
632 {
633 struct stm32f7_i2c_dev *i2c_dev = (struct stm32f7_i2c_dev *)arg;
634 struct stm32_i2c_dma *dma = i2c_dev->dma;
635 struct device *dev = dma->chan_using->device->dev;
636
637 stm32f7_i2c_disable_dma_req(i2c_dev);
638 dma_unmap_single(dev, dma->dma_buf, dma->dma_len, dma->dma_data_dir);
639 complete(&dma->dma_complete);
640 }
641
642 static void stm32f7_i2c_hw_config(struct stm32f7_i2c_dev *i2c_dev)
643 {
644 struct stm32f7_i2c_timings *t = &i2c_dev->timing;
645 u32 timing = 0;
646
647 /* Timing settings */
648 timing |= STM32F7_I2C_TIMINGR_PRESC(t->presc);
649 timing |= STM32F7_I2C_TIMINGR_SCLDEL(t->scldel);
650 timing |= STM32F7_I2C_TIMINGR_SDADEL(t->sdadel);
651 timing |= STM32F7_I2C_TIMINGR_SCLH(t->sclh);
652 timing |= STM32F7_I2C_TIMINGR_SCLL(t->scll);
653 writel_relaxed(timing, i2c_dev->base + STM32F7_I2C_TIMINGR);
654
655 /* Enable I2C */
656 if (i2c_dev->setup.analog_filter)
657 stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1,
658 STM32F7_I2C_CR1_ANFOFF);
659 else
660 stm32f7_i2c_set_bits(i2c_dev->base + STM32F7_I2C_CR1,
661 STM32F7_I2C_CR1_ANFOFF);
662
663 /* Program the Digital Filter */
664 stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1,
665 STM32F7_I2C_CR1_DNF_MASK);
666 stm32f7_i2c_set_bits(i2c_dev->base + STM32F7_I2C_CR1,
667 STM32F7_I2C_CR1_DNF(i2c_dev->setup.dnf));
668
669 stm32f7_i2c_set_bits(i2c_dev->base + STM32F7_I2C_CR1,
670 STM32F7_I2C_CR1_PE);
671 }
672
673 static void stm32f7_i2c_write_tx_data(struct stm32f7_i2c_dev *i2c_dev)
674 {
675 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
676 void __iomem *base = i2c_dev->base;
677
678 if (f7_msg->count) {
679 writeb_relaxed(*f7_msg->buf++, base + STM32F7_I2C_TXDR);
680 f7_msg->count--;
681 }
682 }
683
684 static void stm32f7_i2c_read_rx_data(struct stm32f7_i2c_dev *i2c_dev)
685 {
686 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
687 void __iomem *base = i2c_dev->base;
688
689 if (f7_msg->count) {
690 *f7_msg->buf++ = readb_relaxed(base + STM32F7_I2C_RXDR);
691 f7_msg->count--;
692 } else {
693 /* Flush RX buffer has no data is expected */
694 readb_relaxed(base + STM32F7_I2C_RXDR);
695 }
696 }
697
698 static void stm32f7_i2c_reload(struct stm32f7_i2c_dev *i2c_dev)
699 {
700 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
701 u32 cr2;
702
703 if (i2c_dev->use_dma)
704 f7_msg->count -= STM32F7_I2C_MAX_LEN;
705
706 cr2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR2);
707
708 cr2 &= ~STM32F7_I2C_CR2_NBYTES_MASK;
709 if (f7_msg->count > STM32F7_I2C_MAX_LEN) {
710 cr2 |= STM32F7_I2C_CR2_NBYTES(STM32F7_I2C_MAX_LEN);
711 } else {
712 cr2 &= ~STM32F7_I2C_CR2_RELOAD;
713 cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count);
714 }
715
716 writel_relaxed(cr2, i2c_dev->base + STM32F7_I2C_CR2);
717 }
718
719 static void stm32f7_i2c_smbus_reload(struct stm32f7_i2c_dev *i2c_dev)
720 {
721 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
722 u32 cr2;
723 u8 *val;
724
725 /*
726 * For I2C_SMBUS_BLOCK_DATA && I2C_SMBUS_BLOCK_PROC_CALL, the first
727 * data received inform us how many data will follow.
728 */
729 stm32f7_i2c_read_rx_data(i2c_dev);
730
731 /*
732 * Update NBYTES with the value read to continue the transfer
733 */
734 val = f7_msg->buf - sizeof(u8);
735 f7_msg->count = *val;
736 cr2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR2);
737 cr2 &= ~(STM32F7_I2C_CR2_NBYTES_MASK | STM32F7_I2C_CR2_RELOAD);
738 cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count);
739 writel_relaxed(cr2, i2c_dev->base + STM32F7_I2C_CR2);
740 }
741
742 static int stm32f7_i2c_release_bus(struct i2c_adapter *i2c_adap)
743 {
744 struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(i2c_adap);
745
746 dev_info(i2c_dev->dev, "Trying to recover bus\n");
747
748 stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1,
749 STM32F7_I2C_CR1_PE);
750
751 stm32f7_i2c_hw_config(i2c_dev);
752
753 return 0;
754 }
755
756 static int stm32f7_i2c_wait_free_bus(struct stm32f7_i2c_dev *i2c_dev)
757 {
758 u32 status;
759 int ret;
760
761 ret = readl_relaxed_poll_timeout(i2c_dev->base + STM32F7_I2C_ISR,
762 status,
763 !(status & STM32F7_I2C_ISR_BUSY),
764 10, 1000);
765 if (!ret)
766 return 0;
767
768 dev_info(i2c_dev->dev, "bus busy\n");
769
770 ret = stm32f7_i2c_release_bus(&i2c_dev->adap);
771 if (ret) {
772 dev_err(i2c_dev->dev, "Failed to recover the bus (%d)\n", ret);
773 return ret;
774 }
775
776 return -EBUSY;
777 }
778
779 static void stm32f7_i2c_xfer_msg(struct stm32f7_i2c_dev *i2c_dev,
780 struct i2c_msg *msg)
781 {
782 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
783 void __iomem *base = i2c_dev->base;
784 u32 cr1, cr2;
785 int ret;
786
787 f7_msg->addr = msg->addr;
788 f7_msg->buf = msg->buf;
789 f7_msg->count = msg->len;
790 f7_msg->result = 0;
791 f7_msg->stop = (i2c_dev->msg_id >= i2c_dev->msg_num - 1);
792
793 reinit_completion(&i2c_dev->complete);
794
795 cr1 = readl_relaxed(base + STM32F7_I2C_CR1);
796 cr2 = readl_relaxed(base + STM32F7_I2C_CR2);
797
798 /* Set transfer direction */
799 cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
800 if (msg->flags & I2C_M_RD)
801 cr2 |= STM32F7_I2C_CR2_RD_WRN;
802
803 /* Set slave address */
804 cr2 &= ~(STM32F7_I2C_CR2_HEAD10R | STM32F7_I2C_CR2_ADD10);
805 if (msg->flags & I2C_M_TEN) {
806 cr2 &= ~STM32F7_I2C_CR2_SADD10_MASK;
807 cr2 |= STM32F7_I2C_CR2_SADD10(f7_msg->addr);
808 cr2 |= STM32F7_I2C_CR2_ADD10;
809 } else {
810 cr2 &= ~STM32F7_I2C_CR2_SADD7_MASK;
811 cr2 |= STM32F7_I2C_CR2_SADD7(f7_msg->addr);
812 }
813
814 /* Set nb bytes to transfer and reload if needed */
815 cr2 &= ~(STM32F7_I2C_CR2_NBYTES_MASK | STM32F7_I2C_CR2_RELOAD);
816 if (f7_msg->count > STM32F7_I2C_MAX_LEN) {
817 cr2 |= STM32F7_I2C_CR2_NBYTES(STM32F7_I2C_MAX_LEN);
818 cr2 |= STM32F7_I2C_CR2_RELOAD;
819 } else {
820 cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count);
821 }
822
823 /* Enable NACK, STOP, error and transfer complete interrupts */
824 cr1 |= STM32F7_I2C_CR1_ERRIE | STM32F7_I2C_CR1_TCIE |
825 STM32F7_I2C_CR1_STOPIE | STM32F7_I2C_CR1_NACKIE;
826
827 /* Clear DMA req and TX/RX interrupt */
828 cr1 &= ~(STM32F7_I2C_CR1_RXIE | STM32F7_I2C_CR1_TXIE |
829 STM32F7_I2C_CR1_RXDMAEN | STM32F7_I2C_CR1_TXDMAEN);
830
831 /* Configure DMA or enable RX/TX interrupt */
832 i2c_dev->use_dma = false;
833 if (i2c_dev->dma && f7_msg->count >= STM32F7_I2C_DMA_LEN_MIN) {
834 ret = stm32_i2c_prep_dma_xfer(i2c_dev->dev, i2c_dev->dma,
835 msg->flags & I2C_M_RD,
836 f7_msg->count, f7_msg->buf,
837 stm32f7_i2c_dma_callback,
838 i2c_dev);
839 if (!ret)
840 i2c_dev->use_dma = true;
841 else
842 dev_warn(i2c_dev->dev, "can't use DMA\n");
843 }
844
845 if (!i2c_dev->use_dma) {
846 if (msg->flags & I2C_M_RD)
847 cr1 |= STM32F7_I2C_CR1_RXIE;
848 else
849 cr1 |= STM32F7_I2C_CR1_TXIE;
850 } else {
851 if (msg->flags & I2C_M_RD)
852 cr1 |= STM32F7_I2C_CR1_RXDMAEN;
853 else
854 cr1 |= STM32F7_I2C_CR1_TXDMAEN;
855 }
856
857 /* Configure Start/Repeated Start */
858 cr2 |= STM32F7_I2C_CR2_START;
859
860 i2c_dev->master_mode = true;
861
862 /* Write configurations registers */
863 writel_relaxed(cr1, base + STM32F7_I2C_CR1);
864 writel_relaxed(cr2, base + STM32F7_I2C_CR2);
865 }
866
867 static int stm32f7_i2c_smbus_xfer_msg(struct stm32f7_i2c_dev *i2c_dev,
868 unsigned short flags, u8 command,
869 union i2c_smbus_data *data)
870 {
871 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
872 struct device *dev = i2c_dev->dev;
873 void __iomem *base = i2c_dev->base;
874 u32 cr1, cr2;
875 int i, ret;
876
877 f7_msg->result = 0;
878 reinit_completion(&i2c_dev->complete);
879
880 cr2 = readl_relaxed(base + STM32F7_I2C_CR2);
881 cr1 = readl_relaxed(base + STM32F7_I2C_CR1);
882
883 /* Set transfer direction */
884 cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
885 if (f7_msg->read_write)
886 cr2 |= STM32F7_I2C_CR2_RD_WRN;
887
888 /* Set slave address */
889 cr2 &= ~(STM32F7_I2C_CR2_ADD10 | STM32F7_I2C_CR2_SADD7_MASK);
890 cr2 |= STM32F7_I2C_CR2_SADD7(f7_msg->addr);
891
892 f7_msg->smbus_buf[0] = command;
893 switch (f7_msg->size) {
894 case I2C_SMBUS_QUICK:
895 f7_msg->stop = true;
896 f7_msg->count = 0;
897 break;
898 case I2C_SMBUS_BYTE:
899 f7_msg->stop = true;
900 f7_msg->count = 1;
901 break;
902 case I2C_SMBUS_BYTE_DATA:
903 if (f7_msg->read_write) {
904 f7_msg->stop = false;
905 f7_msg->count = 1;
906 cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
907 } else {
908 f7_msg->stop = true;
909 f7_msg->count = 2;
910 f7_msg->smbus_buf[1] = data->byte;
911 }
912 break;
913 case I2C_SMBUS_WORD_DATA:
914 if (f7_msg->read_write) {
915 f7_msg->stop = false;
916 f7_msg->count = 1;
917 cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
918 } else {
919 f7_msg->stop = true;
920 f7_msg->count = 3;
921 f7_msg->smbus_buf[1] = data->word & 0xff;
922 f7_msg->smbus_buf[2] = data->word >> 8;
923 }
924 break;
925 case I2C_SMBUS_BLOCK_DATA:
926 if (f7_msg->read_write) {
927 f7_msg->stop = false;
928 f7_msg->count = 1;
929 cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
930 } else {
931 f7_msg->stop = true;
932 if (data->block[0] > I2C_SMBUS_BLOCK_MAX ||
933 !data->block[0]) {
934 dev_err(dev, "Invalid block write size %d\n",
935 data->block[0]);
936 return -EINVAL;
937 }
938 f7_msg->count = data->block[0] + 2;
939 for (i = 1; i < f7_msg->count; i++)
940 f7_msg->smbus_buf[i] = data->block[i - 1];
941 }
942 break;
943 case I2C_SMBUS_PROC_CALL:
944 f7_msg->stop = false;
945 f7_msg->count = 3;
946 f7_msg->smbus_buf[1] = data->word & 0xff;
947 f7_msg->smbus_buf[2] = data->word >> 8;
948 cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
949 f7_msg->read_write = I2C_SMBUS_READ;
950 break;
951 case I2C_SMBUS_BLOCK_PROC_CALL:
952 f7_msg->stop = false;
953 if (data->block[0] > I2C_SMBUS_BLOCK_MAX - 1) {
954 dev_err(dev, "Invalid block write size %d\n",
955 data->block[0]);
956 return -EINVAL;
957 }
958 f7_msg->count = data->block[0] + 2;
959 for (i = 1; i < f7_msg->count; i++)
960 f7_msg->smbus_buf[i] = data->block[i - 1];
961 cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
962 f7_msg->read_write = I2C_SMBUS_READ;
963 break;
964 case I2C_SMBUS_I2C_BLOCK_DATA:
965 /* Rely on emulated i2c transfer (through master_xfer) */
966 return -EOPNOTSUPP;
967 default:
968 dev_err(dev, "Unsupported smbus protocol %d\n", f7_msg->size);
969 return -EOPNOTSUPP;
970 }
971
972 f7_msg->buf = f7_msg->smbus_buf;
973
974 /* Configure PEC */
975 if ((flags & I2C_CLIENT_PEC) && f7_msg->size != I2C_SMBUS_QUICK) {
976 cr1 |= STM32F7_I2C_CR1_PECEN;
977 cr2 |= STM32F7_I2C_CR2_PECBYTE;
978 if (!f7_msg->read_write)
979 f7_msg->count++;
980 } else {
981 cr1 &= ~STM32F7_I2C_CR1_PECEN;
982 cr2 &= ~STM32F7_I2C_CR2_PECBYTE;
983 }
984
985 /* Set number of bytes to be transferred */
986 cr2 &= ~(STM32F7_I2C_CR2_NBYTES_MASK | STM32F7_I2C_CR2_RELOAD);
987 cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count);
988
989 /* Enable NACK, STOP, error and transfer complete interrupts */
990 cr1 |= STM32F7_I2C_CR1_ERRIE | STM32F7_I2C_CR1_TCIE |
991 STM32F7_I2C_CR1_STOPIE | STM32F7_I2C_CR1_NACKIE;
992
993 /* Clear DMA req and TX/RX interrupt */
994 cr1 &= ~(STM32F7_I2C_CR1_RXIE | STM32F7_I2C_CR1_TXIE |
995 STM32F7_I2C_CR1_RXDMAEN | STM32F7_I2C_CR1_TXDMAEN);
996
997 /* Configure DMA or enable RX/TX interrupt */
998 i2c_dev->use_dma = false;
999 if (i2c_dev->dma && f7_msg->count >= STM32F7_I2C_DMA_LEN_MIN) {
1000 ret = stm32_i2c_prep_dma_xfer(i2c_dev->dev, i2c_dev->dma,
1001 cr2 & STM32F7_I2C_CR2_RD_WRN,
1002 f7_msg->count, f7_msg->buf,
1003 stm32f7_i2c_dma_callback,
1004 i2c_dev);
1005 if (!ret)
1006 i2c_dev->use_dma = true;
1007 else
1008 dev_warn(i2c_dev->dev, "can't use DMA\n");
1009 }
1010
1011 if (!i2c_dev->use_dma) {
1012 if (cr2 & STM32F7_I2C_CR2_RD_WRN)
1013 cr1 |= STM32F7_I2C_CR1_RXIE;
1014 else
1015 cr1 |= STM32F7_I2C_CR1_TXIE;
1016 } else {
1017 if (cr2 & STM32F7_I2C_CR2_RD_WRN)
1018 cr1 |= STM32F7_I2C_CR1_RXDMAEN;
1019 else
1020 cr1 |= STM32F7_I2C_CR1_TXDMAEN;
1021 }
1022
1023 /* Set Start bit */
1024 cr2 |= STM32F7_I2C_CR2_START;
1025
1026 i2c_dev->master_mode = true;
1027
1028 /* Write configurations registers */
1029 writel_relaxed(cr1, base + STM32F7_I2C_CR1);
1030 writel_relaxed(cr2, base + STM32F7_I2C_CR2);
1031
1032 return 0;
1033 }
1034
1035 static void stm32f7_i2c_smbus_rep_start(struct stm32f7_i2c_dev *i2c_dev)
1036 {
1037 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
1038 void __iomem *base = i2c_dev->base;
1039 u32 cr1, cr2;
1040 int ret;
1041
1042 cr2 = readl_relaxed(base + STM32F7_I2C_CR2);
1043 cr1 = readl_relaxed(base + STM32F7_I2C_CR1);
1044
1045 /* Set transfer direction */
1046 cr2 |= STM32F7_I2C_CR2_RD_WRN;
1047
1048 switch (f7_msg->size) {
1049 case I2C_SMBUS_BYTE_DATA:
1050 f7_msg->count = 1;
1051 break;
1052 case I2C_SMBUS_WORD_DATA:
1053 case I2C_SMBUS_PROC_CALL:
1054 f7_msg->count = 2;
1055 break;
1056 case I2C_SMBUS_BLOCK_DATA:
1057 case I2C_SMBUS_BLOCK_PROC_CALL:
1058 f7_msg->count = 1;
1059 cr2 |= STM32F7_I2C_CR2_RELOAD;
1060 break;
1061 }
1062
1063 f7_msg->buf = f7_msg->smbus_buf;
1064 f7_msg->stop = true;
1065
1066 /* Add one byte for PEC if needed */
1067 if (cr1 & STM32F7_I2C_CR1_PECEN)
1068 f7_msg->count++;
1069
1070 /* Set number of bytes to be transferred */
1071 cr2 &= ~(STM32F7_I2C_CR2_NBYTES_MASK);
1072 cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count);
1073
1074 /*
1075 * Configure RX/TX interrupt:
1076 */
1077 cr1 &= ~(STM32F7_I2C_CR1_RXIE | STM32F7_I2C_CR1_TXIE);
1078 cr1 |= STM32F7_I2C_CR1_RXIE;
1079
1080 /*
1081 * Configure DMA or enable RX/TX interrupt:
1082 * For I2C_SMBUS_BLOCK_DATA and I2C_SMBUS_BLOCK_PROC_CALL we don't use
1083 * dma as we don't know in advance how many data will be received
1084 */
1085 cr1 &= ~(STM32F7_I2C_CR1_RXIE | STM32F7_I2C_CR1_TXIE |
1086 STM32F7_I2C_CR1_RXDMAEN | STM32F7_I2C_CR1_TXDMAEN);
1087
1088 i2c_dev->use_dma = false;
1089 if (i2c_dev->dma && f7_msg->count >= STM32F7_I2C_DMA_LEN_MIN &&
1090 f7_msg->size != I2C_SMBUS_BLOCK_DATA &&
1091 f7_msg->size != I2C_SMBUS_BLOCK_PROC_CALL) {
1092 ret = stm32_i2c_prep_dma_xfer(i2c_dev->dev, i2c_dev->dma,
1093 cr2 & STM32F7_I2C_CR2_RD_WRN,
1094 f7_msg->count, f7_msg->buf,
1095 stm32f7_i2c_dma_callback,
1096 i2c_dev);
1097
1098 if (!ret)
1099 i2c_dev->use_dma = true;
1100 else
1101 dev_warn(i2c_dev->dev, "can't use DMA\n");
1102 }
1103
1104 if (!i2c_dev->use_dma)
1105 cr1 |= STM32F7_I2C_CR1_RXIE;
1106 else
1107 cr1 |= STM32F7_I2C_CR1_RXDMAEN;
1108
1109 /* Configure Repeated Start */
1110 cr2 |= STM32F7_I2C_CR2_START;
1111
1112 /* Write configurations registers */
1113 writel_relaxed(cr1, base + STM32F7_I2C_CR1);
1114 writel_relaxed(cr2, base + STM32F7_I2C_CR2);
1115 }
1116
1117 static int stm32f7_i2c_smbus_check_pec(struct stm32f7_i2c_dev *i2c_dev)
1118 {
1119 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
1120 u8 count, internal_pec, received_pec;
1121
1122 internal_pec = readl_relaxed(i2c_dev->base + STM32F7_I2C_PECR);
1123
1124 switch (f7_msg->size) {
1125 case I2C_SMBUS_BYTE:
1126 case I2C_SMBUS_BYTE_DATA:
1127 received_pec = f7_msg->smbus_buf[1];
1128 break;
1129 case I2C_SMBUS_WORD_DATA:
1130 case I2C_SMBUS_PROC_CALL:
1131 received_pec = f7_msg->smbus_buf[2];
1132 break;
1133 case I2C_SMBUS_BLOCK_DATA:
1134 case I2C_SMBUS_BLOCK_PROC_CALL:
1135 count = f7_msg->smbus_buf[0];
1136 received_pec = f7_msg->smbus_buf[count];
1137 break;
1138 default:
1139 dev_err(i2c_dev->dev, "Unsupported smbus protocol for PEC\n");
1140 return -EINVAL;
1141 }
1142
1143 if (internal_pec != received_pec) {
1144 dev_err(i2c_dev->dev, "Bad PEC 0x%02x vs. 0x%02x\n",
1145 internal_pec, received_pec);
1146 return -EBADMSG;
1147 }
1148
1149 return 0;
1150 }
1151
1152 static bool stm32f7_i2c_is_addr_match(struct i2c_client *slave, u32 addcode)
1153 {
1154 u32 addr;
1155
1156 if (!slave)
1157 return false;
1158
1159 if (slave->flags & I2C_CLIENT_TEN) {
1160 /*
1161 * For 10-bit addr, addcode = 11110XY with
1162 * X = Bit 9 of slave address
1163 * Y = Bit 8 of slave address
1164 */
1165 addr = slave->addr >> 8;
1166 addr |= 0x78;
1167 if (addr == addcode)
1168 return true;
1169 } else {
1170 addr = slave->addr & 0x7f;
1171 if (addr == addcode)
1172 return true;
1173 }
1174
1175 return false;
1176 }
1177
1178 static void stm32f7_i2c_slave_start(struct stm32f7_i2c_dev *i2c_dev)
1179 {
1180 struct i2c_client *slave = i2c_dev->slave_running;
1181 void __iomem *base = i2c_dev->base;
1182 u32 mask;
1183 u8 value = 0;
1184
1185 if (i2c_dev->slave_dir) {
1186 /* Notify i2c slave that new read transfer is starting */
1187 i2c_slave_event(slave, I2C_SLAVE_READ_REQUESTED, &value);
1188
1189 /*
1190 * Disable slave TX config in case of I2C combined message
1191 * (I2C Write followed by I2C Read)
1192 */
1193 mask = STM32F7_I2C_CR2_RELOAD;
1194 stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR2, mask);
1195 mask = STM32F7_I2C_CR1_SBC | STM32F7_I2C_CR1_RXIE |
1196 STM32F7_I2C_CR1_TCIE;
1197 stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR1, mask);
1198
1199 /* Enable TX empty, STOP, NACK interrupts */
1200 mask = STM32F7_I2C_CR1_STOPIE | STM32F7_I2C_CR1_NACKIE |
1201 STM32F7_I2C_CR1_TXIE;
1202 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, mask);
1203
1204 /* Write 1st data byte */
1205 writel_relaxed(value, base + STM32F7_I2C_TXDR);
1206 } else {
1207 /* Notify i2c slave that new write transfer is starting */
1208 i2c_slave_event(slave, I2C_SLAVE_WRITE_REQUESTED, &value);
1209
1210 /* Set reload mode to be able to ACK/NACK each received byte */
1211 mask = STM32F7_I2C_CR2_RELOAD;
1212 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR2, mask);
1213
1214 /*
1215 * Set STOP, NACK, RX empty and transfer complete interrupts.*
1216 * Set Slave Byte Control to be able to ACK/NACK each data
1217 * byte received
1218 */
1219 mask = STM32F7_I2C_CR1_STOPIE | STM32F7_I2C_CR1_NACKIE |
1220 STM32F7_I2C_CR1_SBC | STM32F7_I2C_CR1_RXIE |
1221 STM32F7_I2C_CR1_TCIE;
1222 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, mask);
1223 }
1224 }
1225
1226 static void stm32f7_i2c_slave_addr(struct stm32f7_i2c_dev *i2c_dev)
1227 {
1228 void __iomem *base = i2c_dev->base;
1229 u32 isr, addcode, dir, mask;
1230 int i;
1231
1232 isr = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR);
1233 addcode = STM32F7_I2C_ISR_ADDCODE_GET(isr);
1234 dir = isr & STM32F7_I2C_ISR_DIR;
1235
1236 for (i = 0; i < STM32F7_I2C_MAX_SLAVE; i++) {
1237 if (stm32f7_i2c_is_addr_match(i2c_dev->slave[i], addcode)) {
1238 i2c_dev->slave_running = i2c_dev->slave[i];
1239 i2c_dev->slave_dir = dir;
1240
1241 /* Start I2C slave processing */
1242 stm32f7_i2c_slave_start(i2c_dev);
1243
1244 /* Clear ADDR flag */
1245 mask = STM32F7_I2C_ICR_ADDRCF;
1246 writel_relaxed(mask, base + STM32F7_I2C_ICR);
1247 break;
1248 }
1249 }
1250 }
1251
1252 static int stm32f7_i2c_get_slave_id(struct stm32f7_i2c_dev *i2c_dev,
1253 struct i2c_client *slave, int *id)
1254 {
1255 int i;
1256
1257 for (i = 0; i < STM32F7_I2C_MAX_SLAVE; i++) {
1258 if (i2c_dev->slave[i] == slave) {
1259 *id = i;
1260 return 0;
1261 }
1262 }
1263
1264 dev_err(i2c_dev->dev, "Slave 0x%x not registered\n", slave->addr);
1265
1266 return -ENODEV;
1267 }
1268
1269 static int stm32f7_i2c_get_free_slave_id(struct stm32f7_i2c_dev *i2c_dev,
1270 struct i2c_client *slave, int *id)
1271 {
1272 struct device *dev = i2c_dev->dev;
1273 int i;
1274
1275 /*
1276 * slave[0] supports 7-bit and 10-bit slave address
1277 * slave[1] supports 7-bit slave address only
1278 */
1279 for (i = STM32F7_I2C_MAX_SLAVE - 1; i >= 0; i--) {
1280 if (i == 1 && (slave->flags & I2C_CLIENT_TEN))
1281 continue;
1282 if (!i2c_dev->slave[i]) {
1283 *id = i;
1284 return 0;
1285 }
1286 }
1287
1288 dev_err(dev, "Slave 0x%x could not be registered\n", slave->addr);
1289
1290 return -EINVAL;
1291 }
1292
1293 static bool stm32f7_i2c_is_slave_registered(struct stm32f7_i2c_dev *i2c_dev)
1294 {
1295 int i;
1296
1297 for (i = 0; i < STM32F7_I2C_MAX_SLAVE; i++) {
1298 if (i2c_dev->slave[i])
1299 return true;
1300 }
1301
1302 return false;
1303 }
1304
1305 static bool stm32f7_i2c_is_slave_busy(struct stm32f7_i2c_dev *i2c_dev)
1306 {
1307 int i, busy;
1308
1309 busy = 0;
1310 for (i = 0; i < STM32F7_I2C_MAX_SLAVE; i++) {
1311 if (i2c_dev->slave[i])
1312 busy++;
1313 }
1314
1315 return i == busy;
1316 }
1317
1318 static irqreturn_t stm32f7_i2c_slave_isr_event(struct stm32f7_i2c_dev *i2c_dev)
1319 {
1320 void __iomem *base = i2c_dev->base;
1321 u32 cr2, status, mask;
1322 u8 val;
1323 int ret;
1324
1325 status = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR);
1326
1327 /* Slave transmitter mode */
1328 if (status & STM32F7_I2C_ISR_TXIS) {
1329 i2c_slave_event(i2c_dev->slave_running,
1330 I2C_SLAVE_READ_PROCESSED,
1331 &val);
1332
1333 /* Write data byte */
1334 writel_relaxed(val, base + STM32F7_I2C_TXDR);
1335 }
1336
1337 /* Transfer Complete Reload for Slave receiver mode */
1338 if (status & STM32F7_I2C_ISR_TCR || status & STM32F7_I2C_ISR_RXNE) {
1339 /*
1340 * Read data byte then set NBYTES to receive next byte or NACK
1341 * the current received byte
1342 */
1343 val = readb_relaxed(i2c_dev->base + STM32F7_I2C_RXDR);
1344 ret = i2c_slave_event(i2c_dev->slave_running,
1345 I2C_SLAVE_WRITE_RECEIVED,
1346 &val);
1347 if (!ret) {
1348 cr2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR2);
1349 cr2 |= STM32F7_I2C_CR2_NBYTES(1);
1350 writel_relaxed(cr2, i2c_dev->base + STM32F7_I2C_CR2);
1351 } else {
1352 mask = STM32F7_I2C_CR2_NACK;
1353 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR2, mask);
1354 }
1355 }
1356
1357 /* NACK received */
1358 if (status & STM32F7_I2C_ISR_NACKF) {
1359 dev_dbg(i2c_dev->dev, "<%s>: Receive NACK\n", __func__);
1360 writel_relaxed(STM32F7_I2C_ICR_NACKCF, base + STM32F7_I2C_ICR);
1361 }
1362
1363 /* STOP received */
1364 if (status & STM32F7_I2C_ISR_STOPF) {
1365 /* Disable interrupts */
1366 stm32f7_i2c_disable_irq(i2c_dev, STM32F7_I2C_XFER_IRQ_MASK);
1367
1368 if (i2c_dev->slave_dir) {
1369 /*
1370 * Flush TX buffer in order to not used the byte in
1371 * TXDR for the next transfer
1372 */
1373 mask = STM32F7_I2C_ISR_TXE;
1374 stm32f7_i2c_set_bits(base + STM32F7_I2C_ISR, mask);
1375 }
1376
1377 /* Clear STOP flag */
1378 writel_relaxed(STM32F7_I2C_ICR_STOPCF, base + STM32F7_I2C_ICR);
1379
1380 /* Notify i2c slave that a STOP flag has been detected */
1381 i2c_slave_event(i2c_dev->slave_running, I2C_SLAVE_STOP, &val);
1382
1383 i2c_dev->slave_running = NULL;
1384 }
1385
1386 /* Address match received */
1387 if (status & STM32F7_I2C_ISR_ADDR)
1388 stm32f7_i2c_slave_addr(i2c_dev);
1389
1390 return IRQ_HANDLED;
1391 }
1392
1393 static irqreturn_t stm32f7_i2c_isr_event(int irq, void *data)
1394 {
1395 struct stm32f7_i2c_dev *i2c_dev = data;
1396 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
1397 struct stm32_i2c_dma *dma = i2c_dev->dma;
1398 void __iomem *base = i2c_dev->base;
1399 u32 status, mask;
1400 int ret = IRQ_HANDLED;
1401
1402 /* Check if the interrupt if for a slave device */
1403 if (!i2c_dev->master_mode) {
1404 ret = stm32f7_i2c_slave_isr_event(i2c_dev);
1405 return ret;
1406 }
1407
1408 status = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR);
1409
1410 /* Tx empty */
1411 if (status & STM32F7_I2C_ISR_TXIS)
1412 stm32f7_i2c_write_tx_data(i2c_dev);
1413
1414 /* RX not empty */
1415 if (status & STM32F7_I2C_ISR_RXNE)
1416 stm32f7_i2c_read_rx_data(i2c_dev);
1417
1418 /* NACK received */
1419 if (status & STM32F7_I2C_ISR_NACKF) {
1420 dev_dbg(i2c_dev->dev, "<%s>: Receive NACK\n", __func__);
1421 writel_relaxed(STM32F7_I2C_ICR_NACKCF, base + STM32F7_I2C_ICR);
1422 if (i2c_dev->use_dma) {
1423 stm32f7_i2c_disable_dma_req(i2c_dev);
1424 dmaengine_terminate_all(dma->chan_using);
1425 }
1426 f7_msg->result = -ENXIO;
1427 }
1428
1429 /* STOP detection flag */
1430 if (status & STM32F7_I2C_ISR_STOPF) {
1431 /* Disable interrupts */
1432 if (stm32f7_i2c_is_slave_registered(i2c_dev))
1433 mask = STM32F7_I2C_XFER_IRQ_MASK;
1434 else
1435 mask = STM32F7_I2C_ALL_IRQ_MASK;
1436 stm32f7_i2c_disable_irq(i2c_dev, mask);
1437
1438 /* Clear STOP flag */
1439 writel_relaxed(STM32F7_I2C_ICR_STOPCF, base + STM32F7_I2C_ICR);
1440
1441 if (i2c_dev->use_dma && !f7_msg->result) {
1442 ret = IRQ_WAKE_THREAD;
1443 } else {
1444 i2c_dev->master_mode = false;
1445 complete(&i2c_dev->complete);
1446 }
1447 }
1448
1449 /* Transfer complete */
1450 if (status & STM32F7_I2C_ISR_TC) {
1451 if (f7_msg->stop) {
1452 mask = STM32F7_I2C_CR2_STOP;
1453 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR2, mask);
1454 } else if (i2c_dev->use_dma && !f7_msg->result) {
1455 ret = IRQ_WAKE_THREAD;
1456 } else if (f7_msg->smbus) {
1457 stm32f7_i2c_smbus_rep_start(i2c_dev);
1458 } else {
1459 i2c_dev->msg_id++;
1460 i2c_dev->msg++;
1461 stm32f7_i2c_xfer_msg(i2c_dev, i2c_dev->msg);
1462 }
1463 }
1464
1465 if (status & STM32F7_I2C_ISR_TCR) {
1466 if (f7_msg->smbus)
1467 stm32f7_i2c_smbus_reload(i2c_dev);
1468 else
1469 stm32f7_i2c_reload(i2c_dev);
1470 }
1471
1472 return ret;
1473 }
1474
1475 static irqreturn_t stm32f7_i2c_isr_event_thread(int irq, void *data)
1476 {
1477 struct stm32f7_i2c_dev *i2c_dev = data;
1478 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
1479 struct stm32_i2c_dma *dma = i2c_dev->dma;
1480 u32 status;
1481 int ret;
1482
1483 /*
1484 * Wait for dma transfer completion before sending next message or
1485 * notity the end of xfer to the client
1486 */
1487 ret = wait_for_completion_timeout(&i2c_dev->dma->dma_complete, HZ);
1488 if (!ret) {
1489 dev_dbg(i2c_dev->dev, "<%s>: Timed out\n", __func__);
1490 stm32f7_i2c_disable_dma_req(i2c_dev);
1491 dmaengine_terminate_all(dma->chan_using);
1492 f7_msg->result = -ETIMEDOUT;
1493 }
1494
1495 status = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR);
1496
1497 if (status & STM32F7_I2C_ISR_TC) {
1498 if (f7_msg->smbus) {
1499 stm32f7_i2c_smbus_rep_start(i2c_dev);
1500 } else {
1501 i2c_dev->msg_id++;
1502 i2c_dev->msg++;
1503 stm32f7_i2c_xfer_msg(i2c_dev, i2c_dev->msg);
1504 }
1505 } else {
1506 i2c_dev->master_mode = false;
1507 complete(&i2c_dev->complete);
1508 }
1509
1510 return IRQ_HANDLED;
1511 }
1512
1513 static irqreturn_t stm32f7_i2c_isr_error(int irq, void *data)
1514 {
1515 struct stm32f7_i2c_dev *i2c_dev = data;
1516 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
1517 void __iomem *base = i2c_dev->base;
1518 struct device *dev = i2c_dev->dev;
1519 struct stm32_i2c_dma *dma = i2c_dev->dma;
1520 u32 status;
1521
1522 status = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR);
1523
1524 /* Bus error */
1525 if (status & STM32F7_I2C_ISR_BERR) {
1526 dev_err(dev, "<%s>: Bus error\n", __func__);
1527 writel_relaxed(STM32F7_I2C_ICR_BERRCF, base + STM32F7_I2C_ICR);
1528 stm32f7_i2c_release_bus(&i2c_dev->adap);
1529 f7_msg->result = -EIO;
1530 }
1531
1532 /* Arbitration loss */
1533 if (status & STM32F7_I2C_ISR_ARLO) {
1534 dev_dbg(dev, "<%s>: Arbitration loss\n", __func__);
1535 writel_relaxed(STM32F7_I2C_ICR_ARLOCF, base + STM32F7_I2C_ICR);
1536 f7_msg->result = -EAGAIN;
1537 }
1538
1539 if (status & STM32F7_I2C_ISR_PECERR) {
1540 dev_err(dev, "<%s>: PEC error in reception\n", __func__);
1541 writel_relaxed(STM32F7_I2C_ICR_PECCF, base + STM32F7_I2C_ICR);
1542 f7_msg->result = -EINVAL;
1543 }
1544
1545 if (!i2c_dev->slave_running) {
1546 u32 mask;
1547 /* Disable interrupts */
1548 if (stm32f7_i2c_is_slave_registered(i2c_dev))
1549 mask = STM32F7_I2C_XFER_IRQ_MASK;
1550 else
1551 mask = STM32F7_I2C_ALL_IRQ_MASK;
1552 stm32f7_i2c_disable_irq(i2c_dev, mask);
1553 }
1554
1555 /* Disable dma */
1556 if (i2c_dev->use_dma) {
1557 stm32f7_i2c_disable_dma_req(i2c_dev);
1558 dmaengine_terminate_all(dma->chan_using);
1559 }
1560
1561 i2c_dev->master_mode = false;
1562 complete(&i2c_dev->complete);
1563
1564 return IRQ_HANDLED;
1565 }
1566
1567 static int stm32f7_i2c_xfer(struct i2c_adapter *i2c_adap,
1568 struct i2c_msg msgs[], int num)
1569 {
1570 struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(i2c_adap);
1571 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
1572 struct stm32_i2c_dma *dma = i2c_dev->dma;
1573 unsigned long time_left;
1574 int ret;
1575
1576 i2c_dev->msg = msgs;
1577 i2c_dev->msg_num = num;
1578 i2c_dev->msg_id = 0;
1579 f7_msg->smbus = false;
1580
1581 ret = pm_runtime_get_sync(i2c_dev->dev);
1582 if (ret < 0)
1583 return ret;
1584
1585 ret = stm32f7_i2c_wait_free_bus(i2c_dev);
1586 if (ret)
1587 goto pm_free;
1588
1589 stm32f7_i2c_xfer_msg(i2c_dev, msgs);
1590
1591 time_left = wait_for_completion_timeout(&i2c_dev->complete,
1592 i2c_dev->adap.timeout);
1593 ret = f7_msg->result;
1594 if (ret) {
1595 /*
1596 * It is possible that some unsent data have already been
1597 * written into TXDR. To avoid sending old data in a
1598 * further transfer, flush TXDR in case of any error
1599 */
1600 writel_relaxed(STM32F7_I2C_ISR_TXE,
1601 i2c_dev->base + STM32F7_I2C_ISR);
1602 goto pm_free;
1603 }
1604
1605 if (!time_left) {
1606 dev_dbg(i2c_dev->dev, "Access to slave 0x%x timed out\n",
1607 i2c_dev->msg->addr);
1608 if (i2c_dev->use_dma)
1609 dmaengine_terminate_all(dma->chan_using);
1610 stm32f7_i2c_wait_free_bus(i2c_dev);
1611 ret = -ETIMEDOUT;
1612 }
1613
1614 pm_free:
1615 pm_runtime_mark_last_busy(i2c_dev->dev);
1616 pm_runtime_put_autosuspend(i2c_dev->dev);
1617
1618 return (ret < 0) ? ret : num;
1619 }
1620
1621 static int stm32f7_i2c_smbus_xfer(struct i2c_adapter *adapter, u16 addr,
1622 unsigned short flags, char read_write,
1623 u8 command, int size,
1624 union i2c_smbus_data *data)
1625 {
1626 struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(adapter);
1627 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
1628 struct stm32_i2c_dma *dma = i2c_dev->dma;
1629 struct device *dev = i2c_dev->dev;
1630 unsigned long timeout;
1631 int i, ret;
1632
1633 f7_msg->addr = addr;
1634 f7_msg->size = size;
1635 f7_msg->read_write = read_write;
1636 f7_msg->smbus = true;
1637
1638 ret = pm_runtime_get_sync(dev);
1639 if (ret < 0)
1640 return ret;
1641
1642 ret = stm32f7_i2c_wait_free_bus(i2c_dev);
1643 if (ret)
1644 goto pm_free;
1645
1646 ret = stm32f7_i2c_smbus_xfer_msg(i2c_dev, flags, command, data);
1647 if (ret)
1648 goto pm_free;
1649
1650 timeout = wait_for_completion_timeout(&i2c_dev->complete,
1651 i2c_dev->adap.timeout);
1652 ret = f7_msg->result;
1653 if (ret) {
1654 /*
1655 * It is possible that some unsent data have already been
1656 * written into TXDR. To avoid sending old data in a
1657 * further transfer, flush TXDR in case of any error
1658 */
1659 writel_relaxed(STM32F7_I2C_ISR_TXE,
1660 i2c_dev->base + STM32F7_I2C_ISR);
1661 goto pm_free;
1662 }
1663
1664 if (!timeout) {
1665 dev_dbg(dev, "Access to slave 0x%x timed out\n", f7_msg->addr);
1666 if (i2c_dev->use_dma)
1667 dmaengine_terminate_all(dma->chan_using);
1668 stm32f7_i2c_wait_free_bus(i2c_dev);
1669 ret = -ETIMEDOUT;
1670 goto pm_free;
1671 }
1672
1673 /* Check PEC */
1674 if ((flags & I2C_CLIENT_PEC) && size != I2C_SMBUS_QUICK && read_write) {
1675 ret = stm32f7_i2c_smbus_check_pec(i2c_dev);
1676 if (ret)
1677 goto pm_free;
1678 }
1679
1680 if (read_write && size != I2C_SMBUS_QUICK) {
1681 switch (size) {
1682 case I2C_SMBUS_BYTE:
1683 case I2C_SMBUS_BYTE_DATA:
1684 data->byte = f7_msg->smbus_buf[0];
1685 break;
1686 case I2C_SMBUS_WORD_DATA:
1687 case I2C_SMBUS_PROC_CALL:
1688 data->word = f7_msg->smbus_buf[0] |
1689 (f7_msg->smbus_buf[1] << 8);
1690 break;
1691 case I2C_SMBUS_BLOCK_DATA:
1692 case I2C_SMBUS_BLOCK_PROC_CALL:
1693 for (i = 0; i <= f7_msg->smbus_buf[0]; i++)
1694 data->block[i] = f7_msg->smbus_buf[i];
1695 break;
1696 default:
1697 dev_err(dev, "Unsupported smbus transaction\n");
1698 ret = -EINVAL;
1699 }
1700 }
1701
1702 pm_free:
1703 pm_runtime_mark_last_busy(dev);
1704 pm_runtime_put_autosuspend(dev);
1705 return ret;
1706 }
1707
1708 static int stm32f7_i2c_reg_slave(struct i2c_client *slave)
1709 {
1710 struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(slave->adapter);
1711 void __iomem *base = i2c_dev->base;
1712 struct device *dev = i2c_dev->dev;
1713 u32 oar1, oar2, mask;
1714 int id, ret;
1715
1716 if (slave->flags & I2C_CLIENT_PEC) {
1717 dev_err(dev, "SMBus PEC not supported in slave mode\n");
1718 return -EINVAL;
1719 }
1720
1721 if (stm32f7_i2c_is_slave_busy(i2c_dev)) {
1722 dev_err(dev, "Too much slave registered\n");
1723 return -EBUSY;
1724 }
1725
1726 ret = stm32f7_i2c_get_free_slave_id(i2c_dev, slave, &id);
1727 if (ret)
1728 return ret;
1729
1730 ret = pm_runtime_get_sync(dev);
1731 if (ret < 0)
1732 return ret;
1733
1734 if (id == 0) {
1735 /* Configure Own Address 1 */
1736 oar1 = readl_relaxed(i2c_dev->base + STM32F7_I2C_OAR1);
1737 oar1 &= ~STM32F7_I2C_OAR1_MASK;
1738 if (slave->flags & I2C_CLIENT_TEN) {
1739 oar1 |= STM32F7_I2C_OAR1_OA1_10(slave->addr);
1740 oar1 |= STM32F7_I2C_OAR1_OA1MODE;
1741 } else {
1742 oar1 |= STM32F7_I2C_OAR1_OA1_7(slave->addr);
1743 }
1744 oar1 |= STM32F7_I2C_OAR1_OA1EN;
1745 i2c_dev->slave[id] = slave;
1746 writel_relaxed(oar1, i2c_dev->base + STM32F7_I2C_OAR1);
1747 } else if (id == 1) {
1748 /* Configure Own Address 2 */
1749 oar2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_OAR2);
1750 oar2 &= ~STM32F7_I2C_OAR2_MASK;
1751 if (slave->flags & I2C_CLIENT_TEN) {
1752 ret = -EOPNOTSUPP;
1753 goto pm_free;
1754 }
1755
1756 oar2 |= STM32F7_I2C_OAR2_OA2_7(slave->addr);
1757 oar2 |= STM32F7_I2C_OAR2_OA2EN;
1758 i2c_dev->slave[id] = slave;
1759 writel_relaxed(oar2, i2c_dev->base + STM32F7_I2C_OAR2);
1760 } else {
1761 ret = -ENODEV;
1762 goto pm_free;
1763 }
1764
1765 /* Enable ACK */
1766 stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR2, STM32F7_I2C_CR2_NACK);
1767
1768 /* Enable Address match interrupt, error interrupt and enable I2C */
1769 mask = STM32F7_I2C_CR1_ADDRIE | STM32F7_I2C_CR1_ERRIE |
1770 STM32F7_I2C_CR1_PE;
1771 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, mask);
1772
1773 ret = 0;
1774 pm_free:
1775 pm_runtime_mark_last_busy(dev);
1776 pm_runtime_put_autosuspend(dev);
1777
1778 return ret;
1779 }
1780
1781 static int stm32f7_i2c_unreg_slave(struct i2c_client *slave)
1782 {
1783 struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(slave->adapter);
1784 void __iomem *base = i2c_dev->base;
1785 u32 mask;
1786 int id, ret;
1787
1788 ret = stm32f7_i2c_get_slave_id(i2c_dev, slave, &id);
1789 if (ret)
1790 return ret;
1791
1792 WARN_ON(!i2c_dev->slave[id]);
1793
1794 ret = pm_runtime_get_sync(i2c_dev->dev);
1795 if (ret < 0)
1796 return ret;
1797
1798 if (id == 0) {
1799 mask = STM32F7_I2C_OAR1_OA1EN;
1800 stm32f7_i2c_clr_bits(base + STM32F7_I2C_OAR1, mask);
1801 } else {
1802 mask = STM32F7_I2C_OAR2_OA2EN;
1803 stm32f7_i2c_clr_bits(base + STM32F7_I2C_OAR2, mask);
1804 }
1805
1806 i2c_dev->slave[id] = NULL;
1807
1808 if (!(stm32f7_i2c_is_slave_registered(i2c_dev)))
1809 stm32f7_i2c_disable_irq(i2c_dev, STM32F7_I2C_ALL_IRQ_MASK);
1810
1811 pm_runtime_mark_last_busy(i2c_dev->dev);
1812 pm_runtime_put_autosuspend(i2c_dev->dev);
1813
1814 return 0;
1815 }
1816
1817 static int stm32f7_i2c_setup_fm_plus_bits(struct platform_device *pdev,
1818 struct stm32f7_i2c_dev *i2c_dev)
1819 {
1820 struct device_node *np = pdev->dev.of_node;
1821 int ret;
1822 u32 reg, mask;
1823
1824 i2c_dev->regmap = syscon_regmap_lookup_by_phandle(np, "st,syscfg-fmp");
1825 if (IS_ERR(i2c_dev->regmap)) {
1826 /* Optional */
1827 return 0;
1828 }
1829
1830 ret = of_property_read_u32_index(np, "st,syscfg-fmp", 1, &reg);
1831 if (ret)
1832 return ret;
1833
1834 ret = of_property_read_u32_index(np, "st,syscfg-fmp", 2, &mask);
1835 if (ret)
1836 return ret;
1837
1838 return regmap_update_bits(i2c_dev->regmap, reg, mask, mask);
1839 }
1840
1841 static u32 stm32f7_i2c_func(struct i2c_adapter *adap)
1842 {
1843 return I2C_FUNC_I2C | I2C_FUNC_10BIT_ADDR | I2C_FUNC_SLAVE |
1844 I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
1845 I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
1846 I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_BLOCK_PROC_CALL |
1847 I2C_FUNC_SMBUS_PROC_CALL | I2C_FUNC_SMBUS_PEC |
1848 I2C_FUNC_SMBUS_I2C_BLOCK;
1849 }
1850
1851 static const struct i2c_algorithm stm32f7_i2c_algo = {
1852 .master_xfer = stm32f7_i2c_xfer,
1853 .smbus_xfer = stm32f7_i2c_smbus_xfer,
1854 .functionality = stm32f7_i2c_func,
1855 .reg_slave = stm32f7_i2c_reg_slave,
1856 .unreg_slave = stm32f7_i2c_unreg_slave,
1857 };
1858
1859 static int stm32f7_i2c_probe(struct platform_device *pdev)
1860 {
1861 struct stm32f7_i2c_dev *i2c_dev;
1862 const struct stm32f7_i2c_setup *setup;
1863 struct resource *res;
1864 u32 clk_rate, rise_time, fall_time;
1865 struct i2c_adapter *adap;
1866 struct reset_control *rst;
1867 dma_addr_t phy_addr;
1868 int irq_error, irq_event, ret;
1869
1870 i2c_dev = devm_kzalloc(&pdev->dev, sizeof(*i2c_dev), GFP_KERNEL);
1871 if (!i2c_dev)
1872 return -ENOMEM;
1873
1874 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1875 i2c_dev->base = devm_ioremap_resource(&pdev->dev, res);
1876 if (IS_ERR(i2c_dev->base))
1877 return PTR_ERR(i2c_dev->base);
1878 phy_addr = (dma_addr_t)res->start;
1879
1880 irq_event = platform_get_irq(pdev, 0);
1881 if (irq_event <= 0) {
1882 if (irq_event != -EPROBE_DEFER)
1883 dev_err(&pdev->dev, "Failed to get IRQ event: %d\n",
1884 irq_event);
1885 return irq_event ? : -ENOENT;
1886 }
1887
1888 irq_error = platform_get_irq(pdev, 1);
1889 if (irq_error <= 0) {
1890 if (irq_error != -EPROBE_DEFER)
1891 dev_err(&pdev->dev, "Failed to get IRQ error: %d\n",
1892 irq_error);
1893 return irq_error ? : -ENOENT;
1894 }
1895
1896 i2c_dev->clk = devm_clk_get(&pdev->dev, NULL);
1897 if (IS_ERR(i2c_dev->clk)) {
1898 dev_err(&pdev->dev, "Error: Missing controller clock\n");
1899 return PTR_ERR(i2c_dev->clk);
1900 }
1901
1902 ret = clk_prepare_enable(i2c_dev->clk);
1903 if (ret) {
1904 dev_err(&pdev->dev, "Failed to prepare_enable clock\n");
1905 return ret;
1906 }
1907
1908 i2c_dev->speed = STM32_I2C_SPEED_STANDARD;
1909 ret = device_property_read_u32(&pdev->dev, "clock-frequency",
1910 &clk_rate);
1911 if (!ret && clk_rate >= 1000000) {
1912 i2c_dev->speed = STM32_I2C_SPEED_FAST_PLUS;
1913 ret = stm32f7_i2c_setup_fm_plus_bits(pdev, i2c_dev);
1914 if (ret)
1915 goto clk_free;
1916 } else if (!ret && clk_rate >= 400000) {
1917 i2c_dev->speed = STM32_I2C_SPEED_FAST;
1918 } else if (!ret && clk_rate >= 100000) {
1919 i2c_dev->speed = STM32_I2C_SPEED_STANDARD;
1920 }
1921
1922 rst = devm_reset_control_get(&pdev->dev, NULL);
1923 if (IS_ERR(rst)) {
1924 dev_err(&pdev->dev, "Error: Missing controller reset\n");
1925 ret = PTR_ERR(rst);
1926 goto clk_free;
1927 }
1928 reset_control_assert(rst);
1929 udelay(2);
1930 reset_control_deassert(rst);
1931
1932 i2c_dev->dev = &pdev->dev;
1933
1934 ret = devm_request_threaded_irq(&pdev->dev, irq_event,
1935 stm32f7_i2c_isr_event,
1936 stm32f7_i2c_isr_event_thread,
1937 IRQF_ONESHOT,
1938 pdev->name, i2c_dev);
1939 if (ret) {
1940 dev_err(&pdev->dev, "Failed to request irq event %i\n",
1941 irq_event);
1942 goto clk_free;
1943 }
1944
1945 ret = devm_request_irq(&pdev->dev, irq_error, stm32f7_i2c_isr_error, 0,
1946 pdev->name, i2c_dev);
1947 if (ret) {
1948 dev_err(&pdev->dev, "Failed to request irq error %i\n",
1949 irq_error);
1950 goto clk_free;
1951 }
1952
1953 setup = of_device_get_match_data(&pdev->dev);
1954 if (!setup) {
1955 dev_err(&pdev->dev, "Can't get device data\n");
1956 ret = -ENODEV;
1957 goto clk_free;
1958 }
1959 i2c_dev->setup = *setup;
1960
1961 ret = device_property_read_u32(i2c_dev->dev, "i2c-scl-rising-time-ns",
1962 &rise_time);
1963 if (!ret)
1964 i2c_dev->setup.rise_time = rise_time;
1965
1966 ret = device_property_read_u32(i2c_dev->dev, "i2c-scl-falling-time-ns",
1967 &fall_time);
1968 if (!ret)
1969 i2c_dev->setup.fall_time = fall_time;
1970
1971 ret = stm32f7_i2c_setup_timing(i2c_dev, &i2c_dev->setup);
1972 if (ret)
1973 goto clk_free;
1974
1975 adap = &i2c_dev->adap;
1976 i2c_set_adapdata(adap, i2c_dev);
1977 snprintf(adap->name, sizeof(adap->name), "STM32F7 I2C(%pa)",
1978 &res->start);
1979 adap->owner = THIS_MODULE;
1980 adap->timeout = 2 * HZ;
1981 adap->retries = 3;
1982 adap->algo = &stm32f7_i2c_algo;
1983 adap->dev.parent = &pdev->dev;
1984 adap->dev.of_node = pdev->dev.of_node;
1985
1986 init_completion(&i2c_dev->complete);
1987
1988 /* Init DMA config if supported */
1989 i2c_dev->dma = stm32_i2c_dma_request(i2c_dev->dev, phy_addr,
1990 STM32F7_I2C_TXDR,
1991 STM32F7_I2C_RXDR);
1992 if (PTR_ERR(i2c_dev->dma) == -ENODEV)
1993 i2c_dev->dma = NULL;
1994 else if (IS_ERR(i2c_dev->dma)) {
1995 ret = PTR_ERR(i2c_dev->dma);
1996 if (ret != -EPROBE_DEFER)
1997 dev_err(&pdev->dev,
1998 "Failed to request dma error %i\n", ret);
1999 goto clk_free;
2000 }
2001
2002 platform_set_drvdata(pdev, i2c_dev);
2003
2004 pm_runtime_set_autosuspend_delay(i2c_dev->dev,
2005 STM32F7_AUTOSUSPEND_DELAY);
2006 pm_runtime_use_autosuspend(i2c_dev->dev);
2007 pm_runtime_set_active(i2c_dev->dev);
2008 pm_runtime_enable(i2c_dev->dev);
2009
2010 pm_runtime_get_noresume(&pdev->dev);
2011
2012 stm32f7_i2c_hw_config(i2c_dev);
2013
2014 ret = i2c_add_adapter(adap);
2015 if (ret)
2016 goto pm_disable;
2017
2018 dev_info(i2c_dev->dev, "STM32F7 I2C-%d bus adapter\n", adap->nr);
2019
2020 pm_runtime_mark_last_busy(i2c_dev->dev);
2021 pm_runtime_put_autosuspend(i2c_dev->dev);
2022
2023 return 0;
2024
2025 pm_disable:
2026 pm_runtime_put_noidle(i2c_dev->dev);
2027 pm_runtime_disable(i2c_dev->dev);
2028 pm_runtime_set_suspended(i2c_dev->dev);
2029 pm_runtime_dont_use_autosuspend(i2c_dev->dev);
2030
2031 if (i2c_dev->dma) {
2032 stm32_i2c_dma_free(i2c_dev->dma);
2033 i2c_dev->dma = NULL;
2034 }
2035
2036 clk_free:
2037 clk_disable_unprepare(i2c_dev->clk);
2038
2039 return ret;
2040 }
2041
2042 static int stm32f7_i2c_remove(struct platform_device *pdev)
2043 {
2044 struct stm32f7_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
2045
2046 i2c_del_adapter(&i2c_dev->adap);
2047 pm_runtime_get_sync(i2c_dev->dev);
2048
2049 pm_runtime_put_noidle(i2c_dev->dev);
2050 pm_runtime_disable(i2c_dev->dev);
2051 pm_runtime_set_suspended(i2c_dev->dev);
2052 pm_runtime_dont_use_autosuspend(i2c_dev->dev);
2053
2054 if (i2c_dev->dma) {
2055 stm32_i2c_dma_free(i2c_dev->dma);
2056 i2c_dev->dma = NULL;
2057 }
2058
2059 clk_disable_unprepare(i2c_dev->clk);
2060
2061 return 0;
2062 }
2063
2064 #ifdef CONFIG_PM
2065 static int stm32f7_i2c_runtime_suspend(struct device *dev)
2066 {
2067 struct stm32f7_i2c_dev *i2c_dev = dev_get_drvdata(dev);
2068
2069 if (!stm32f7_i2c_is_slave_registered(i2c_dev))
2070 clk_disable_unprepare(i2c_dev->clk);
2071
2072 return 0;
2073 }
2074
2075 static int stm32f7_i2c_runtime_resume(struct device *dev)
2076 {
2077 struct stm32f7_i2c_dev *i2c_dev = dev_get_drvdata(dev);
2078 int ret;
2079
2080 if (!stm32f7_i2c_is_slave_registered(i2c_dev)) {
2081 ret = clk_prepare_enable(i2c_dev->clk);
2082 if (ret) {
2083 dev_err(dev, "failed to prepare_enable clock\n");
2084 return ret;
2085 }
2086 }
2087
2088 return 0;
2089 }
2090 #endif
2091
2092 static const struct dev_pm_ops stm32f7_i2c_pm_ops = {
2093 SET_RUNTIME_PM_OPS(stm32f7_i2c_runtime_suspend,
2094 stm32f7_i2c_runtime_resume, NULL)
2095 };
2096
2097 static const struct of_device_id stm32f7_i2c_match[] = {
2098 { .compatible = "st,stm32f7-i2c", .data = &stm32f7_setup},
2099 {},
2100 };
2101 MODULE_DEVICE_TABLE(of, stm32f7_i2c_match);
2102
2103 static struct platform_driver stm32f7_i2c_driver = {
2104 .driver = {
2105 .name = "stm32f7-i2c",
2106 .of_match_table = stm32f7_i2c_match,
2107 .pm = &stm32f7_i2c_pm_ops,
2108 },
2109 .probe = stm32f7_i2c_probe,
2110 .remove = stm32f7_i2c_remove,
2111 };
2112
2113 module_platform_driver(stm32f7_i2c_driver);
2114
2115 MODULE_AUTHOR("M'boumba Cedric Madianga <cedric.madianga@gmail.com>");
2116 MODULE_DESCRIPTION("STMicroelectronics STM32F7 I2C driver");
2117 MODULE_LICENSE("GPL v2");
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