1 // SPDX-License-Identifier: GPL-2.0
3 * drivers/i2c/busses/i2c-tegra.c
5 * Copyright (C) 2010 Google, Inc.
6 * Author: Colin Cross <ccross@android.com>
9 #include <linux/bitfield.h>
10 #include <linux/clk.h>
11 #include <linux/delay.h>
12 #include <linux/dmaengine.h>
13 #include <linux/dma-mapping.h>
14 #include <linux/err.h>
15 #include <linux/i2c.h>
16 #include <linux/init.h>
17 #include <linux/interrupt.h>
19 #include <linux/iopoll.h>
20 #include <linux/irq.h>
21 #include <linux/kernel.h>
22 #include <linux/ktime.h>
23 #include <linux/module.h>
24 #include <linux/of_device.h>
25 #include <linux/pinctrl/consumer.h>
26 #include <linux/platform_device.h>
27 #include <linux/pm_runtime.h>
28 #include <linux/reset.h>
30 #define BYTES_PER_FIFO_WORD 4
32 #define I2C_CNFG 0x000
33 #define I2C_CNFG_DEBOUNCE_CNT GENMASK(14, 12)
34 #define I2C_CNFG_PACKET_MODE_EN BIT(10)
35 #define I2C_CNFG_NEW_MASTER_FSM BIT(11)
36 #define I2C_CNFG_MULTI_MASTER_MODE BIT(17)
37 #define I2C_STATUS 0x01c
38 #define I2C_SL_CNFG 0x020
39 #define I2C_SL_CNFG_NACK BIT(1)
40 #define I2C_SL_CNFG_NEWSL BIT(2)
41 #define I2C_SL_ADDR1 0x02c
42 #define I2C_SL_ADDR2 0x030
43 #define I2C_TLOW_SEXT 0x034
44 #define I2C_TX_FIFO 0x050
45 #define I2C_RX_FIFO 0x054
46 #define I2C_PACKET_TRANSFER_STATUS 0x058
47 #define I2C_FIFO_CONTROL 0x05c
48 #define I2C_FIFO_CONTROL_TX_FLUSH BIT(1)
49 #define I2C_FIFO_CONTROL_RX_FLUSH BIT(0)
50 #define I2C_FIFO_CONTROL_TX_TRIG(x) (((x) - 1) << 5)
51 #define I2C_FIFO_CONTROL_RX_TRIG(x) (((x) - 1) << 2)
52 #define I2C_FIFO_STATUS 0x060
53 #define I2C_FIFO_STATUS_TX GENMASK(7, 4)
54 #define I2C_FIFO_STATUS_RX GENMASK(3, 0)
55 #define I2C_INT_MASK 0x064
56 #define I2C_INT_STATUS 0x068
57 #define I2C_INT_BUS_CLR_DONE BIT(11)
58 #define I2C_INT_PACKET_XFER_COMPLETE BIT(7)
59 #define I2C_INT_NO_ACK BIT(3)
60 #define I2C_INT_ARBITRATION_LOST BIT(2)
61 #define I2C_INT_TX_FIFO_DATA_REQ BIT(1)
62 #define I2C_INT_RX_FIFO_DATA_REQ BIT(0)
63 #define I2C_CLK_DIVISOR 0x06c
64 #define I2C_CLK_DIVISOR_STD_FAST_MODE GENMASK(31, 16)
65 #define I2C_CLK_DIVISOR_HSMODE GENMASK(15, 0)
67 #define DVC_CTRL_REG1 0x000
68 #define DVC_CTRL_REG1_INTR_EN BIT(10)
69 #define DVC_CTRL_REG3 0x008
70 #define DVC_CTRL_REG3_SW_PROG BIT(26)
71 #define DVC_CTRL_REG3_I2C_DONE_INTR_EN BIT(30)
72 #define DVC_STATUS 0x00c
73 #define DVC_STATUS_I2C_DONE_INTR BIT(30)
75 #define I2C_ERR_NONE 0x00
76 #define I2C_ERR_NO_ACK BIT(0)
77 #define I2C_ERR_ARBITRATION_LOST BIT(1)
78 #define I2C_ERR_UNKNOWN_INTERRUPT BIT(2)
79 #define I2C_ERR_RX_BUFFER_OVERFLOW BIT(3)
81 #define PACKET_HEADER0_HEADER_SIZE GENMASK(29, 28)
82 #define PACKET_HEADER0_PACKET_ID GENMASK(23, 16)
83 #define PACKET_HEADER0_CONT_ID GENMASK(15, 12)
84 #define PACKET_HEADER0_PROTOCOL GENMASK(7, 4)
85 #define PACKET_HEADER0_PROTOCOL_I2C 1
87 #define I2C_HEADER_CONT_ON_NAK BIT(21)
88 #define I2C_HEADER_READ BIT(19)
89 #define I2C_HEADER_10BIT_ADDR BIT(18)
90 #define I2C_HEADER_IE_ENABLE BIT(17)
91 #define I2C_HEADER_REPEAT_START BIT(16)
92 #define I2C_HEADER_CONTINUE_XFER BIT(15)
93 #define I2C_HEADER_SLAVE_ADDR_SHIFT 1
95 #define I2C_BUS_CLEAR_CNFG 0x084
96 #define I2C_BC_SCLK_THRESHOLD GENMASK(23, 16)
97 #define I2C_BC_STOP_COND BIT(2)
98 #define I2C_BC_TERMINATE BIT(1)
99 #define I2C_BC_ENABLE BIT(0)
100 #define I2C_BUS_CLEAR_STATUS 0x088
101 #define I2C_BC_STATUS BIT(0)
103 #define I2C_CONFIG_LOAD 0x08c
104 #define I2C_MSTR_CONFIG_LOAD BIT(0)
106 #define I2C_CLKEN_OVERRIDE 0x090
107 #define I2C_MST_CORE_CLKEN_OVR BIT(0)
109 #define I2C_INTERFACE_TIMING_0 0x094
110 #define I2C_INTERFACE_TIMING_THIGH GENMASK(13, 8)
111 #define I2C_INTERFACE_TIMING_TLOW GENMASK(5, 0)
112 #define I2C_INTERFACE_TIMING_1 0x098
113 #define I2C_INTERFACE_TIMING_TBUF GENMASK(29, 24)
114 #define I2C_INTERFACE_TIMING_TSU_STO GENMASK(21, 16)
115 #define I2C_INTERFACE_TIMING_THD_STA GENMASK(13, 8)
116 #define I2C_INTERFACE_TIMING_TSU_STA GENMASK(5, 0)
118 #define I2C_HS_INTERFACE_TIMING_0 0x09c
119 #define I2C_HS_INTERFACE_TIMING_THIGH GENMASK(13, 8)
120 #define I2C_HS_INTERFACE_TIMING_TLOW GENMASK(5, 0)
121 #define I2C_HS_INTERFACE_TIMING_1 0x0a0
122 #define I2C_HS_INTERFACE_TIMING_TSU_STO GENMASK(21, 16)
123 #define I2C_HS_INTERFACE_TIMING_THD_STA GENMASK(13, 8)
124 #define I2C_HS_INTERFACE_TIMING_TSU_STA GENMASK(5, 0)
126 #define I2C_MST_FIFO_CONTROL 0x0b4
127 #define I2C_MST_FIFO_CONTROL_RX_FLUSH BIT(0)
128 #define I2C_MST_FIFO_CONTROL_TX_FLUSH BIT(1)
129 #define I2C_MST_FIFO_CONTROL_RX_TRIG(x) (((x) - 1) << 4)
130 #define I2C_MST_FIFO_CONTROL_TX_TRIG(x) (((x) - 1) << 16)
132 #define I2C_MST_FIFO_STATUS 0x0b8
133 #define I2C_MST_FIFO_STATUS_TX GENMASK(23, 16)
134 #define I2C_MST_FIFO_STATUS_RX GENMASK(7, 0)
136 /* configuration load timeout in microseconds */
137 #define I2C_CONFIG_LOAD_TIMEOUT 1000000
139 /* Packet header size in bytes */
140 #define I2C_PACKET_HEADER_SIZE 12
143 * I2C Controller will use PIO mode for transfers up to 32 bytes in order to
144 * avoid DMA overhead, otherwise external APB DMA controller will be used.
145 * Note that the actual MAX PIO length is 20 bytes because 32 bytes include
146 * I2C_PACKET_HEADER_SIZE.
148 #define I2C_PIO_MODE_PREFERRED_LEN 32
151 * msg_end_type: The bus control which need to be send at end of transfer.
152 * @MSG_END_STOP: Send stop pulse at end of transfer.
153 * @MSG_END_REPEAT_START: Send repeat start at end of transfer.
154 * @MSG_END_CONTINUE: The following on message is coming and so do not send
155 * stop or repeat start.
159 MSG_END_REPEAT_START
,
164 * struct tegra_i2c_hw_feature : Different HW support on Tegra
165 * @has_continue_xfer_support: Continue transfer supports.
166 * @has_per_pkt_xfer_complete_irq: Has enable/disable capability for transfer
167 * complete interrupt per packet basis.
168 * @has_config_load_reg: Has the config load register to load the new
170 * @clk_divisor_hs_mode: Clock divisor in HS mode.
171 * @clk_divisor_std_mode: Clock divisor in standard mode. It is
172 * applicable if there is no fast clock source i.e. single clock
174 * @clk_divisor_fast_mode: Clock divisor in fast mode. It is
175 * applicable if there is no fast clock source i.e. single clock
177 * @clk_divisor_fast_plus_mode: Clock divisor in fast mode plus. It is
178 * applicable if there is no fast clock source (i.e. single
180 * @has_multi_master_mode: The I2C controller supports running in single-master
181 * or multi-master mode.
182 * @has_slcg_override_reg: The I2C controller supports a register that
183 * overrides the second level clock gating.
184 * @has_mst_fifo: The I2C controller contains the new MST FIFO interface that
185 * provides additional features and allows for longer messages to
186 * be transferred in one go.
187 * @quirks: i2c adapter quirks for limiting write/read transfer size and not
188 * allowing 0 length transfers.
189 * @supports_bus_clear: Bus Clear support to recover from bus hang during
190 * SDA stuck low from device for some unknown reasons.
191 * @has_apb_dma: Support of APBDMA on corresponding Tegra chip.
192 * @tlow_std_mode: Low period of the clock in standard mode.
193 * @thigh_std_mode: High period of the clock in standard mode.
194 * @tlow_fast_fastplus_mode: Low period of the clock in fast/fast-plus modes.
195 * @thigh_fast_fastplus_mode: High period of the clock in fast/fast-plus modes.
196 * @setup_hold_time_std_mode: Setup and hold time for start and stop conditions
198 * @setup_hold_time_fast_fast_plus_mode: Setup and hold time for start and stop
199 * conditions in fast/fast-plus modes.
200 * @setup_hold_time_hs_mode: Setup and hold time for start and stop conditions
202 * @has_interface_timing_reg: Has interface timing register to program the tuned
205 struct tegra_i2c_hw_feature
{
206 bool has_continue_xfer_support
;
207 bool has_per_pkt_xfer_complete_irq
;
208 bool has_config_load_reg
;
209 int clk_divisor_hs_mode
;
210 int clk_divisor_std_mode
;
211 int clk_divisor_fast_mode
;
212 u16 clk_divisor_fast_plus_mode
;
213 bool has_multi_master_mode
;
214 bool has_slcg_override_reg
;
216 const struct i2c_adapter_quirks
*quirks
;
217 bool supports_bus_clear
;
221 u8 tlow_fast_fastplus_mode
;
222 u8 thigh_fast_fastplus_mode
;
223 u32 setup_hold_time_std_mode
;
224 u32 setup_hold_time_fast_fast_plus_mode
;
225 u32 setup_hold_time_hs_mode
;
226 bool has_interface_timing_reg
;
230 * struct tegra_i2c_dev - per device I2C context
231 * @dev: device reference for power management
232 * @hw: Tegra I2C HW feature
233 * @adapter: core I2C layer adapter information
234 * @div_clk: clock reference for div clock of I2C controller
235 * @clocks: array of I2C controller clocks
236 * @nclocks: number of clocks in the array
237 * @rst: reset control for the I2C controller
238 * @base: ioremapped registers cookie
239 * @base_phys: physical base address of the I2C controller
240 * @cont_id: I2C controller ID, used for packet header
241 * @irq: IRQ number of transfer complete interrupt
242 * @is_dvc: identifies the DVC I2C controller, has a different register layout
243 * @is_vi: identifies the VI I2C controller, has a different register layout
244 * @msg_complete: transfer completion notifier
245 * @msg_err: error code for completed message
246 * @msg_buf: pointer to current message data
247 * @msg_buf_remaining: size of unsent data in the message buffer
248 * @msg_read: identifies read transfers
249 * @bus_clk_rate: current I2C bus clock rate
250 * @is_multimaster_mode: track if I2C controller is in multi-master mode
251 * @tx_dma_chan: DMA transmit channel
252 * @rx_dma_chan: DMA receive channel
253 * @dma_phys: handle to DMA resources
254 * @dma_buf: pointer to allocated DMA buffer
255 * @dma_buf_size: DMA buffer size
256 * @is_curr_dma_xfer: indicates active DMA transfer
257 * @dma_complete: DMA completion notifier
258 * @is_curr_atomic_xfer: indicates active atomic transfer
260 struct tegra_i2c_dev
{
262 const struct tegra_i2c_hw_feature
*hw
;
263 struct i2c_adapter adapter
;
265 struct clk_bulk_data clocks
[2];
266 unsigned int nclocks
;
267 struct reset_control
*rst
;
269 phys_addr_t base_phys
;
274 struct completion msg_complete
;
277 size_t msg_buf_remaining
;
280 bool is_multimaster_mode
;
281 struct dma_chan
*tx_dma_chan
;
282 struct dma_chan
*rx_dma_chan
;
285 unsigned int dma_buf_size
;
286 bool is_curr_dma_xfer
;
287 struct completion dma_complete
;
288 bool is_curr_atomic_xfer
;
291 static int tegra_i2c_init(struct tegra_i2c_dev
*i2c_dev
);
293 static void dvc_writel(struct tegra_i2c_dev
*i2c_dev
, u32 val
,
296 writel_relaxed(val
, i2c_dev
->base
+ reg
);
299 static u32
dvc_readl(struct tegra_i2c_dev
*i2c_dev
, unsigned long reg
)
301 return readl_relaxed(i2c_dev
->base
+ reg
);
305 * i2c_writel and i2c_readl will offset the register if necessary to talk
306 * to the I2C block inside the DVC block
308 static unsigned long tegra_i2c_reg_addr(struct tegra_i2c_dev
*i2c_dev
,
312 reg
+= (reg
>= I2C_TX_FIFO
) ? 0x10 : 0x40;
313 else if (i2c_dev
->is_vi
)
314 reg
= 0xc00 + (reg
<< 2);
318 static void i2c_writel(struct tegra_i2c_dev
*i2c_dev
, u32 val
,
321 writel_relaxed(val
, i2c_dev
->base
+ tegra_i2c_reg_addr(i2c_dev
, reg
));
323 /* Read back register to make sure that register writes completed */
324 if (reg
!= I2C_TX_FIFO
)
325 readl_relaxed(i2c_dev
->base
+ tegra_i2c_reg_addr(i2c_dev
, reg
));
328 static u32
i2c_readl(struct tegra_i2c_dev
*i2c_dev
, unsigned long reg
)
330 return readl_relaxed(i2c_dev
->base
+ tegra_i2c_reg_addr(i2c_dev
, reg
));
333 static void i2c_writesl(struct tegra_i2c_dev
*i2c_dev
, void *data
,
334 unsigned long reg
, int len
)
336 writesl(i2c_dev
->base
+ tegra_i2c_reg_addr(i2c_dev
, reg
), data
, len
);
339 static void i2c_readsl(struct tegra_i2c_dev
*i2c_dev
, void *data
,
340 unsigned long reg
, int len
)
342 readsl(i2c_dev
->base
+ tegra_i2c_reg_addr(i2c_dev
, reg
), data
, len
);
345 static void tegra_i2c_mask_irq(struct tegra_i2c_dev
*i2c_dev
, u32 mask
)
349 int_mask
= i2c_readl(i2c_dev
, I2C_INT_MASK
) & ~mask
;
350 i2c_writel(i2c_dev
, int_mask
, I2C_INT_MASK
);
353 static void tegra_i2c_unmask_irq(struct tegra_i2c_dev
*i2c_dev
, u32 mask
)
357 int_mask
= i2c_readl(i2c_dev
, I2C_INT_MASK
) | mask
;
358 i2c_writel(i2c_dev
, int_mask
, I2C_INT_MASK
);
361 static void tegra_i2c_dma_complete(void *args
)
363 struct tegra_i2c_dev
*i2c_dev
= args
;
365 complete(&i2c_dev
->dma_complete
);
368 static int tegra_i2c_dma_submit(struct tegra_i2c_dev
*i2c_dev
, size_t len
)
370 struct dma_async_tx_descriptor
*dma_desc
;
371 enum dma_transfer_direction dir
;
372 struct dma_chan
*chan
;
374 dev_dbg(i2c_dev
->dev
, "starting DMA for length: %zu\n", len
);
375 reinit_completion(&i2c_dev
->dma_complete
);
376 dir
= i2c_dev
->msg_read
? DMA_DEV_TO_MEM
: DMA_MEM_TO_DEV
;
377 chan
= i2c_dev
->msg_read
? i2c_dev
->rx_dma_chan
: i2c_dev
->tx_dma_chan
;
378 dma_desc
= dmaengine_prep_slave_single(chan
, i2c_dev
->dma_phys
,
379 len
, dir
, DMA_PREP_INTERRUPT
|
382 dev_err(i2c_dev
->dev
, "failed to get DMA descriptor\n");
386 dma_desc
->callback
= tegra_i2c_dma_complete
;
387 dma_desc
->callback_param
= i2c_dev
;
388 dmaengine_submit(dma_desc
);
389 dma_async_issue_pending(chan
);
393 static void tegra_i2c_release_dma(struct tegra_i2c_dev
*i2c_dev
)
395 if (i2c_dev
->dma_buf
) {
396 dma_free_coherent(i2c_dev
->dev
, i2c_dev
->dma_buf_size
,
397 i2c_dev
->dma_buf
, i2c_dev
->dma_phys
);
398 i2c_dev
->dma_buf
= NULL
;
401 if (i2c_dev
->tx_dma_chan
) {
402 dma_release_channel(i2c_dev
->tx_dma_chan
);
403 i2c_dev
->tx_dma_chan
= NULL
;
406 if (i2c_dev
->rx_dma_chan
) {
407 dma_release_channel(i2c_dev
->rx_dma_chan
);
408 i2c_dev
->rx_dma_chan
= NULL
;
412 static int tegra_i2c_init_dma(struct tegra_i2c_dev
*i2c_dev
)
414 struct dma_chan
*chan
;
419 if (!i2c_dev
->hw
->has_apb_dma
|| i2c_dev
->is_vi
)
422 if (!IS_ENABLED(CONFIG_TEGRA20_APB_DMA
)) {
423 dev_dbg(i2c_dev
->dev
, "Support for APB DMA not enabled!\n");
427 chan
= dma_request_chan(i2c_dev
->dev
, "rx");
433 i2c_dev
->rx_dma_chan
= chan
;
435 chan
= dma_request_chan(i2c_dev
->dev
, "tx");
441 i2c_dev
->tx_dma_chan
= chan
;
443 dma_buf
= dma_alloc_coherent(i2c_dev
->dev
, i2c_dev
->dma_buf_size
,
444 &dma_phys
, GFP_KERNEL
| __GFP_NOWARN
);
446 dev_err(i2c_dev
->dev
, "failed to allocate the DMA buffer\n");
451 i2c_dev
->dma_buf
= dma_buf
;
452 i2c_dev
->dma_phys
= dma_phys
;
456 tegra_i2c_release_dma(i2c_dev
);
457 if (err
!= -EPROBE_DEFER
) {
458 dev_err(i2c_dev
->dev
, "cannot use DMA: %d\n", err
);
459 dev_err(i2c_dev
->dev
, "falling back to PIO\n");
466 static int tegra_i2c_flush_fifos(struct tegra_i2c_dev
*i2c_dev
)
468 u32 mask
, val
, offset
, reg_offset
;
472 if (i2c_dev
->hw
->has_mst_fifo
) {
473 mask
= I2C_MST_FIFO_CONTROL_TX_FLUSH
|
474 I2C_MST_FIFO_CONTROL_RX_FLUSH
;
475 offset
= I2C_MST_FIFO_CONTROL
;
477 mask
= I2C_FIFO_CONTROL_TX_FLUSH
|
478 I2C_FIFO_CONTROL_RX_FLUSH
;
479 offset
= I2C_FIFO_CONTROL
;
482 val
= i2c_readl(i2c_dev
, offset
);
484 i2c_writel(i2c_dev
, val
, offset
);
486 reg_offset
= tegra_i2c_reg_addr(i2c_dev
, offset
);
487 addr
= i2c_dev
->base
+ reg_offset
;
489 if (i2c_dev
->is_curr_atomic_xfer
)
490 err
= readl_relaxed_poll_timeout_atomic(addr
, val
, !(val
& mask
),
493 err
= readl_relaxed_poll_timeout(addr
, val
, !(val
& mask
),
497 dev_err(i2c_dev
->dev
, "failed to flush FIFO\n");
503 static int tegra_i2c_empty_rx_fifo(struct tegra_i2c_dev
*i2c_dev
)
507 u8
*buf
= i2c_dev
->msg_buf
;
508 size_t buf_remaining
= i2c_dev
->msg_buf_remaining
;
509 int words_to_transfer
;
512 * Catch overflow due to message fully sent
513 * before the check for RX FIFO availability.
515 if (WARN_ON_ONCE(!(i2c_dev
->msg_buf_remaining
)))
518 if (i2c_dev
->hw
->has_mst_fifo
) {
519 val
= i2c_readl(i2c_dev
, I2C_MST_FIFO_STATUS
);
520 rx_fifo_avail
= FIELD_GET(I2C_MST_FIFO_STATUS_RX
, val
);
522 val
= i2c_readl(i2c_dev
, I2C_FIFO_STATUS
);
523 rx_fifo_avail
= FIELD_GET(I2C_FIFO_STATUS_RX
, val
);
526 /* Rounds down to not include partial word at the end of buf */
527 words_to_transfer
= buf_remaining
/ BYTES_PER_FIFO_WORD
;
528 if (words_to_transfer
> rx_fifo_avail
)
529 words_to_transfer
= rx_fifo_avail
;
531 i2c_readsl(i2c_dev
, buf
, I2C_RX_FIFO
, words_to_transfer
);
533 buf
+= words_to_transfer
* BYTES_PER_FIFO_WORD
;
534 buf_remaining
-= words_to_transfer
* BYTES_PER_FIFO_WORD
;
535 rx_fifo_avail
-= words_to_transfer
;
538 * If there is a partial word at the end of buf, handle it manually to
539 * prevent overwriting past the end of buf
541 if (rx_fifo_avail
> 0 && buf_remaining
> 0) {
543 * buf_remaining > 3 check not needed as rx_fifo_avail == 0
544 * when (words_to_transfer was > rx_fifo_avail) earlier
547 val
= i2c_readl(i2c_dev
, I2C_RX_FIFO
);
548 val
= cpu_to_le32(val
);
549 memcpy(buf
, &val
, buf_remaining
);
554 /* RX FIFO must be drained, otherwise it's an Overflow case. */
555 if (WARN_ON_ONCE(rx_fifo_avail
))
558 i2c_dev
->msg_buf_remaining
= buf_remaining
;
559 i2c_dev
->msg_buf
= buf
;
564 static int tegra_i2c_fill_tx_fifo(struct tegra_i2c_dev
*i2c_dev
)
568 u8
*buf
= i2c_dev
->msg_buf
;
569 size_t buf_remaining
= i2c_dev
->msg_buf_remaining
;
570 int words_to_transfer
;
572 if (i2c_dev
->hw
->has_mst_fifo
) {
573 val
= i2c_readl(i2c_dev
, I2C_MST_FIFO_STATUS
);
574 tx_fifo_avail
= FIELD_GET(I2C_MST_FIFO_STATUS_TX
, val
);
576 val
= i2c_readl(i2c_dev
, I2C_FIFO_STATUS
);
577 tx_fifo_avail
= FIELD_GET(I2C_FIFO_STATUS_TX
, val
);
580 /* Rounds down to not include partial word at the end of buf */
581 words_to_transfer
= buf_remaining
/ BYTES_PER_FIFO_WORD
;
583 /* It's very common to have < 4 bytes, so optimize that case. */
584 if (words_to_transfer
) {
585 if (words_to_transfer
> tx_fifo_avail
)
586 words_to_transfer
= tx_fifo_avail
;
589 * Update state before writing to FIFO. If this casues us
590 * to finish writing all bytes (AKA buf_remaining goes to 0) we
591 * have a potential for an interrupt (PACKET_XFER_COMPLETE is
592 * not maskable). We need to make sure that the isr sees
593 * buf_remaining as 0 and doesn't call us back re-entrantly.
595 buf_remaining
-= words_to_transfer
* BYTES_PER_FIFO_WORD
;
596 tx_fifo_avail
-= words_to_transfer
;
597 i2c_dev
->msg_buf_remaining
= buf_remaining
;
598 i2c_dev
->msg_buf
= buf
+
599 words_to_transfer
* BYTES_PER_FIFO_WORD
;
602 i2c_writesl(i2c_dev
, buf
, I2C_TX_FIFO
, words_to_transfer
);
604 buf
+= words_to_transfer
* BYTES_PER_FIFO_WORD
;
608 * If there is a partial word at the end of buf, handle it manually to
609 * prevent reading past the end of buf, which could cross a page
610 * boundary and fault.
612 if (tx_fifo_avail
> 0 && buf_remaining
> 0) {
614 * buf_remaining > 3 check not needed as tx_fifo_avail == 0
615 * when (words_to_transfer was > tx_fifo_avail) earlier
616 * in this function for non-zero words_to_transfer.
618 memcpy(&val
, buf
, buf_remaining
);
619 val
= le32_to_cpu(val
);
621 /* Again update before writing to FIFO to make sure isr sees. */
622 i2c_dev
->msg_buf_remaining
= 0;
623 i2c_dev
->msg_buf
= NULL
;
626 i2c_writel(i2c_dev
, val
, I2C_TX_FIFO
);
633 * One of the Tegra I2C blocks is inside the DVC (Digital Voltage Controller)
634 * block. This block is identical to the rest of the I2C blocks, except that
635 * it only supports master mode, it has registers moved around, and it needs
636 * some extra init to get it into I2C mode. The register moves are handled
637 * by i2c_readl and i2c_writel
639 static void tegra_dvc_init(struct tegra_i2c_dev
*i2c_dev
)
643 val
= dvc_readl(i2c_dev
, DVC_CTRL_REG3
);
644 val
|= DVC_CTRL_REG3_SW_PROG
;
645 val
|= DVC_CTRL_REG3_I2C_DONE_INTR_EN
;
646 dvc_writel(i2c_dev
, val
, DVC_CTRL_REG3
);
648 val
= dvc_readl(i2c_dev
, DVC_CTRL_REG1
);
649 val
|= DVC_CTRL_REG1_INTR_EN
;
650 dvc_writel(i2c_dev
, val
, DVC_CTRL_REG1
);
653 static int __maybe_unused
tegra_i2c_runtime_resume(struct device
*dev
)
655 struct tegra_i2c_dev
*i2c_dev
= dev_get_drvdata(dev
);
658 ret
= pinctrl_pm_select_default_state(i2c_dev
->dev
);
662 ret
= clk_bulk_enable(i2c_dev
->nclocks
, i2c_dev
->clocks
);
667 * VI I2C device is attached to VE power domain which goes through
668 * power ON/OFF during PM runtime resume/suspend. So, controller
669 * should go through reset and need to re-initialize after power
672 if (i2c_dev
->is_vi
) {
673 ret
= tegra_i2c_init(i2c_dev
);
681 clk_bulk_disable(i2c_dev
->nclocks
, i2c_dev
->clocks
);
686 static int __maybe_unused
tegra_i2c_runtime_suspend(struct device
*dev
)
688 struct tegra_i2c_dev
*i2c_dev
= dev_get_drvdata(dev
);
690 clk_bulk_disable(i2c_dev
->nclocks
, i2c_dev
->clocks
);
692 return pinctrl_pm_select_idle_state(i2c_dev
->dev
);
695 static int tegra_i2c_wait_for_config_load(struct tegra_i2c_dev
*i2c_dev
)
697 unsigned long reg_offset
;
702 if (i2c_dev
->hw
->has_config_load_reg
) {
703 reg_offset
= tegra_i2c_reg_addr(i2c_dev
, I2C_CONFIG_LOAD
);
704 addr
= i2c_dev
->base
+ reg_offset
;
705 i2c_writel(i2c_dev
, I2C_MSTR_CONFIG_LOAD
, I2C_CONFIG_LOAD
);
707 if (i2c_dev
->is_curr_atomic_xfer
)
708 err
= readl_relaxed_poll_timeout_atomic(
709 addr
, val
, val
== 0, 1000,
710 I2C_CONFIG_LOAD_TIMEOUT
);
712 err
= readl_relaxed_poll_timeout(
713 addr
, val
, val
== 0, 1000,
714 I2C_CONFIG_LOAD_TIMEOUT
);
717 dev_warn(i2c_dev
->dev
,
718 "timeout waiting for config load\n");
726 static void tegra_i2c_vi_init(struct tegra_i2c_dev
*i2c_dev
)
730 value
= FIELD_PREP(I2C_INTERFACE_TIMING_THIGH
, 2) |
731 FIELD_PREP(I2C_INTERFACE_TIMING_TLOW
, 4);
732 i2c_writel(i2c_dev
, value
, I2C_INTERFACE_TIMING_0
);
734 value
= FIELD_PREP(I2C_INTERFACE_TIMING_TBUF
, 4) |
735 FIELD_PREP(I2C_INTERFACE_TIMING_TSU_STO
, 7) |
736 FIELD_PREP(I2C_INTERFACE_TIMING_THD_STA
, 4) |
737 FIELD_PREP(I2C_INTERFACE_TIMING_TSU_STA
, 4);
738 i2c_writel(i2c_dev
, value
, I2C_INTERFACE_TIMING_1
);
740 value
= FIELD_PREP(I2C_HS_INTERFACE_TIMING_THIGH
, 3) |
741 FIELD_PREP(I2C_HS_INTERFACE_TIMING_TLOW
, 8);
742 i2c_writel(i2c_dev
, value
, I2C_HS_INTERFACE_TIMING_0
);
744 value
= FIELD_PREP(I2C_HS_INTERFACE_TIMING_TSU_STO
, 11) |
745 FIELD_PREP(I2C_HS_INTERFACE_TIMING_THD_STA
, 11) |
746 FIELD_PREP(I2C_HS_INTERFACE_TIMING_TSU_STA
, 11);
747 i2c_writel(i2c_dev
, value
, I2C_HS_INTERFACE_TIMING_1
);
749 value
= FIELD_PREP(I2C_BC_SCLK_THRESHOLD
, 9) | I2C_BC_STOP_COND
;
750 i2c_writel(i2c_dev
, value
, I2C_BUS_CLEAR_CNFG
);
752 i2c_writel(i2c_dev
, 0x0, I2C_TLOW_SEXT
);
755 static int tegra_i2c_init(struct tegra_i2c_dev
*i2c_dev
)
759 u32 clk_divisor
, clk_multiplier
;
765 * The reset shouldn't ever fail in practice. The failure will be a
766 * sign of a severe problem that needs to be resolved. Still we don't
767 * want to fail the initialization completely because this may break
768 * kernel boot up since voltage regulators use I2C. Hence, we will
769 * emit a noisy warning on error, which won't stay unnoticed and
770 * won't hose machine entirely.
772 err
= reset_control_reset(i2c_dev
->rst
);
776 tegra_dvc_init(i2c_dev
);
778 val
= I2C_CNFG_NEW_MASTER_FSM
| I2C_CNFG_PACKET_MODE_EN
|
779 FIELD_PREP(I2C_CNFG_DEBOUNCE_CNT
, 2);
781 if (i2c_dev
->hw
->has_multi_master_mode
)
782 val
|= I2C_CNFG_MULTI_MASTER_MODE
;
784 i2c_writel(i2c_dev
, val
, I2C_CNFG
);
785 i2c_writel(i2c_dev
, 0, I2C_INT_MASK
);
788 tegra_i2c_vi_init(i2c_dev
);
790 switch (i2c_dev
->bus_clk_rate
) {
791 case I2C_MAX_STANDARD_MODE_FREQ
+ 1 ... I2C_MAX_FAST_MODE_PLUS_FREQ
:
793 tlow
= i2c_dev
->hw
->tlow_fast_fastplus_mode
;
794 thigh
= i2c_dev
->hw
->thigh_fast_fastplus_mode
;
795 tsu_thd
= i2c_dev
->hw
->setup_hold_time_fast_fast_plus_mode
;
797 if (i2c_dev
->bus_clk_rate
> I2C_MAX_FAST_MODE_FREQ
)
798 non_hs_mode
= i2c_dev
->hw
->clk_divisor_fast_plus_mode
;
800 non_hs_mode
= i2c_dev
->hw
->clk_divisor_fast_mode
;
803 case 0 ... I2C_MAX_STANDARD_MODE_FREQ
:
804 tlow
= i2c_dev
->hw
->tlow_std_mode
;
805 thigh
= i2c_dev
->hw
->thigh_std_mode
;
806 tsu_thd
= i2c_dev
->hw
->setup_hold_time_std_mode
;
807 non_hs_mode
= i2c_dev
->hw
->clk_divisor_std_mode
;
811 /* Make sure clock divisor programmed correctly */
812 clk_divisor
= FIELD_PREP(I2C_CLK_DIVISOR_HSMODE
,
813 i2c_dev
->hw
->clk_divisor_hs_mode
) |
814 FIELD_PREP(I2C_CLK_DIVISOR_STD_FAST_MODE
, non_hs_mode
);
815 i2c_writel(i2c_dev
, clk_divisor
, I2C_CLK_DIVISOR
);
817 if (i2c_dev
->hw
->has_interface_timing_reg
) {
818 val
= FIELD_PREP(I2C_INTERFACE_TIMING_THIGH
, thigh
) |
819 FIELD_PREP(I2C_INTERFACE_TIMING_TLOW
, tlow
);
820 i2c_writel(i2c_dev
, val
, I2C_INTERFACE_TIMING_0
);
824 * configure setup and hold times only when tsu_thd is non-zero.
825 * otherwise, preserve the chip default values
827 if (i2c_dev
->hw
->has_interface_timing_reg
&& tsu_thd
)
828 i2c_writel(i2c_dev
, tsu_thd
, I2C_INTERFACE_TIMING_1
);
830 clk_multiplier
= tlow
+ thigh
+ 2;
831 clk_multiplier
*= non_hs_mode
+ 1;
833 err
= clk_set_rate(i2c_dev
->div_clk
,
834 i2c_dev
->bus_clk_rate
* clk_multiplier
);
836 dev_err(i2c_dev
->dev
, "failed to set div-clk rate: %d\n", err
);
840 if (!i2c_dev
->is_dvc
&& !i2c_dev
->is_vi
) {
841 u32 sl_cfg
= i2c_readl(i2c_dev
, I2C_SL_CNFG
);
843 sl_cfg
|= I2C_SL_CNFG_NACK
| I2C_SL_CNFG_NEWSL
;
844 i2c_writel(i2c_dev
, sl_cfg
, I2C_SL_CNFG
);
845 i2c_writel(i2c_dev
, 0xfc, I2C_SL_ADDR1
);
846 i2c_writel(i2c_dev
, 0x00, I2C_SL_ADDR2
);
849 err
= tegra_i2c_flush_fifos(i2c_dev
);
853 if (i2c_dev
->is_multimaster_mode
&& i2c_dev
->hw
->has_slcg_override_reg
)
854 i2c_writel(i2c_dev
, I2C_MST_CORE_CLKEN_OVR
, I2C_CLKEN_OVERRIDE
);
856 err
= tegra_i2c_wait_for_config_load(i2c_dev
);
863 static int tegra_i2c_disable_packet_mode(struct tegra_i2c_dev
*i2c_dev
)
868 * NACK interrupt is generated before the I2C controller generates
869 * the STOP condition on the bus. So wait for 2 clock periods
870 * before disabling the controller so that the STOP condition has
871 * been delivered properly.
873 udelay(DIV_ROUND_UP(2 * 1000000, i2c_dev
->bus_clk_rate
));
875 cnfg
= i2c_readl(i2c_dev
, I2C_CNFG
);
876 if (cnfg
& I2C_CNFG_PACKET_MODE_EN
)
877 i2c_writel(i2c_dev
, cnfg
& ~I2C_CNFG_PACKET_MODE_EN
, I2C_CNFG
);
879 return tegra_i2c_wait_for_config_load(i2c_dev
);
882 static irqreturn_t
tegra_i2c_isr(int irq
, void *dev_id
)
885 const u32 status_err
= I2C_INT_NO_ACK
| I2C_INT_ARBITRATION_LOST
;
886 struct tegra_i2c_dev
*i2c_dev
= dev_id
;
888 status
= i2c_readl(i2c_dev
, I2C_INT_STATUS
);
891 dev_warn(i2c_dev
->dev
, "irq status 0 %08x %08x %08x\n",
892 i2c_readl(i2c_dev
, I2C_PACKET_TRANSFER_STATUS
),
893 i2c_readl(i2c_dev
, I2C_STATUS
),
894 i2c_readl(i2c_dev
, I2C_CNFG
));
895 i2c_dev
->msg_err
|= I2C_ERR_UNKNOWN_INTERRUPT
;
899 if (unlikely(status
& status_err
)) {
900 tegra_i2c_disable_packet_mode(i2c_dev
);
901 if (status
& I2C_INT_NO_ACK
)
902 i2c_dev
->msg_err
|= I2C_ERR_NO_ACK
;
903 if (status
& I2C_INT_ARBITRATION_LOST
)
904 i2c_dev
->msg_err
|= I2C_ERR_ARBITRATION_LOST
;
909 * I2C transfer is terminated during the bus clear so skip
910 * processing the other interrupts.
912 if (i2c_dev
->hw
->supports_bus_clear
&& (status
& I2C_INT_BUS_CLR_DONE
))
915 if (!i2c_dev
->is_curr_dma_xfer
) {
916 if (i2c_dev
->msg_read
&& (status
& I2C_INT_RX_FIFO_DATA_REQ
)) {
917 if (tegra_i2c_empty_rx_fifo(i2c_dev
)) {
919 * Overflow error condition: message fully sent,
920 * with no XFER_COMPLETE interrupt but hardware
921 * asks to transfer more.
923 i2c_dev
->msg_err
|= I2C_ERR_RX_BUFFER_OVERFLOW
;
928 if (!i2c_dev
->msg_read
&& (status
& I2C_INT_TX_FIFO_DATA_REQ
)) {
929 if (i2c_dev
->msg_buf_remaining
)
930 tegra_i2c_fill_tx_fifo(i2c_dev
);
932 tegra_i2c_mask_irq(i2c_dev
,
933 I2C_INT_TX_FIFO_DATA_REQ
);
937 i2c_writel(i2c_dev
, status
, I2C_INT_STATUS
);
939 dvc_writel(i2c_dev
, DVC_STATUS_I2C_DONE_INTR
, DVC_STATUS
);
942 * During message read XFER_COMPLETE interrupt is triggered prior to
943 * DMA completion and during message write XFER_COMPLETE interrupt is
944 * triggered after DMA completion.
945 * PACKETS_XFER_COMPLETE indicates completion of all bytes of transfer.
946 * so forcing msg_buf_remaining to 0 in DMA mode.
948 if (status
& I2C_INT_PACKET_XFER_COMPLETE
) {
949 if (i2c_dev
->is_curr_dma_xfer
)
950 i2c_dev
->msg_buf_remaining
= 0;
952 * Underflow error condition: XFER_COMPLETE before message
955 if (WARN_ON_ONCE(i2c_dev
->msg_buf_remaining
)) {
956 i2c_dev
->msg_err
|= I2C_ERR_UNKNOWN_INTERRUPT
;
959 complete(&i2c_dev
->msg_complete
);
963 /* An error occurred, mask all interrupts */
964 tegra_i2c_mask_irq(i2c_dev
, I2C_INT_NO_ACK
| I2C_INT_ARBITRATION_LOST
|
965 I2C_INT_PACKET_XFER_COMPLETE
| I2C_INT_TX_FIFO_DATA_REQ
|
966 I2C_INT_RX_FIFO_DATA_REQ
);
967 if (i2c_dev
->hw
->supports_bus_clear
)
968 tegra_i2c_mask_irq(i2c_dev
, I2C_INT_BUS_CLR_DONE
);
969 i2c_writel(i2c_dev
, status
, I2C_INT_STATUS
);
971 dvc_writel(i2c_dev
, DVC_STATUS_I2C_DONE_INTR
, DVC_STATUS
);
973 if (i2c_dev
->is_curr_dma_xfer
) {
974 if (i2c_dev
->msg_read
)
975 dmaengine_terminate_async(i2c_dev
->rx_dma_chan
);
977 dmaengine_terminate_async(i2c_dev
->tx_dma_chan
);
979 complete(&i2c_dev
->dma_complete
);
982 complete(&i2c_dev
->msg_complete
);
987 static void tegra_i2c_config_fifo_trig(struct tegra_i2c_dev
*i2c_dev
,
992 struct dma_slave_config slv_config
= {0};
993 struct dma_chan
*chan
;
995 unsigned long reg_offset
;
997 if (i2c_dev
->hw
->has_mst_fifo
)
998 reg
= I2C_MST_FIFO_CONTROL
;
1000 reg
= I2C_FIFO_CONTROL
;
1002 if (i2c_dev
->is_curr_dma_xfer
) {
1005 else if (len
& 0x10)
1010 if (i2c_dev
->msg_read
) {
1011 chan
= i2c_dev
->rx_dma_chan
;
1012 reg_offset
= tegra_i2c_reg_addr(i2c_dev
, I2C_RX_FIFO
);
1013 slv_config
.src_addr
= i2c_dev
->base_phys
+ reg_offset
;
1014 slv_config
.src_addr_width
= DMA_SLAVE_BUSWIDTH_4_BYTES
;
1015 slv_config
.src_maxburst
= dma_burst
;
1017 if (i2c_dev
->hw
->has_mst_fifo
)
1018 val
= I2C_MST_FIFO_CONTROL_RX_TRIG(dma_burst
);
1020 val
= I2C_FIFO_CONTROL_RX_TRIG(dma_burst
);
1022 chan
= i2c_dev
->tx_dma_chan
;
1023 reg_offset
= tegra_i2c_reg_addr(i2c_dev
, I2C_TX_FIFO
);
1024 slv_config
.dst_addr
= i2c_dev
->base_phys
+ reg_offset
;
1025 slv_config
.dst_addr_width
= DMA_SLAVE_BUSWIDTH_4_BYTES
;
1026 slv_config
.dst_maxburst
= dma_burst
;
1028 if (i2c_dev
->hw
->has_mst_fifo
)
1029 val
= I2C_MST_FIFO_CONTROL_TX_TRIG(dma_burst
);
1031 val
= I2C_FIFO_CONTROL_TX_TRIG(dma_burst
);
1034 slv_config
.device_fc
= true;
1035 ret
= dmaengine_slave_config(chan
, &slv_config
);
1037 dev_err(i2c_dev
->dev
, "DMA slave config failed: %d\n",
1039 dev_err(i2c_dev
->dev
, "falling back to PIO\n");
1040 tegra_i2c_release_dma(i2c_dev
);
1041 i2c_dev
->is_curr_dma_xfer
= false;
1047 if (i2c_dev
->hw
->has_mst_fifo
)
1048 val
= I2C_MST_FIFO_CONTROL_TX_TRIG(8) |
1049 I2C_MST_FIFO_CONTROL_RX_TRIG(1);
1051 val
= I2C_FIFO_CONTROL_TX_TRIG(8) |
1052 I2C_FIFO_CONTROL_RX_TRIG(1);
1054 i2c_writel(i2c_dev
, val
, reg
);
1057 static unsigned long
1058 tegra_i2c_poll_completion_timeout(struct tegra_i2c_dev
*i2c_dev
,
1059 struct completion
*complete
,
1060 unsigned int timeout_ms
)
1062 ktime_t ktime
= ktime_get();
1063 ktime_t ktimeout
= ktime_add_ms(ktime
, timeout_ms
);
1066 u32 status
= i2c_readl(i2c_dev
, I2C_INT_STATUS
);
1069 tegra_i2c_isr(i2c_dev
->irq
, i2c_dev
);
1071 if (completion_done(complete
)) {
1072 s64 delta
= ktime_ms_delta(ktimeout
, ktime
);
1074 return msecs_to_jiffies(delta
) ?: 1;
1077 ktime
= ktime_get();
1079 } while (ktime_before(ktime
, ktimeout
));
1084 static unsigned long
1085 tegra_i2c_wait_completion_timeout(struct tegra_i2c_dev
*i2c_dev
,
1086 struct completion
*complete
,
1087 unsigned int timeout_ms
)
1091 if (i2c_dev
->is_curr_atomic_xfer
) {
1092 ret
= tegra_i2c_poll_completion_timeout(i2c_dev
, complete
,
1095 enable_irq(i2c_dev
->irq
);
1096 ret
= wait_for_completion_timeout(complete
,
1097 msecs_to_jiffies(timeout_ms
));
1098 disable_irq(i2c_dev
->irq
);
1101 * Under some rare circumstances (like running KASAN +
1102 * NFS root) CPU, which handles interrupt, may stuck in
1103 * uninterruptible state for a significant time. In this
1104 * case we will get timeout if I2C transfer is running on
1105 * a sibling CPU, despite of IRQ being raised.
1107 * In order to handle this rare condition, the IRQ status
1108 * needs to be checked after timeout.
1111 ret
= tegra_i2c_poll_completion_timeout(i2c_dev
,
1118 static int tegra_i2c_issue_bus_clear(struct i2c_adapter
*adap
)
1120 struct tegra_i2c_dev
*i2c_dev
= i2c_get_adapdata(adap
);
1122 unsigned long time_left
;
1125 reinit_completion(&i2c_dev
->msg_complete
);
1126 reg
= FIELD_PREP(I2C_BC_SCLK_THRESHOLD
, 9) | I2C_BC_STOP_COND
|
1128 i2c_writel(i2c_dev
, reg
, I2C_BUS_CLEAR_CNFG
);
1129 if (i2c_dev
->hw
->has_config_load_reg
) {
1130 err
= tegra_i2c_wait_for_config_load(i2c_dev
);
1135 reg
|= I2C_BC_ENABLE
;
1136 i2c_writel(i2c_dev
, reg
, I2C_BUS_CLEAR_CNFG
);
1137 tegra_i2c_unmask_irq(i2c_dev
, I2C_INT_BUS_CLR_DONE
);
1139 time_left
= tegra_i2c_wait_completion_timeout(
1140 i2c_dev
, &i2c_dev
->msg_complete
, 50);
1141 tegra_i2c_mask_irq(i2c_dev
, I2C_INT_BUS_CLR_DONE
);
1143 if (time_left
== 0) {
1144 dev_err(i2c_dev
->dev
, "timed out for bus clear\n");
1148 reg
= i2c_readl(i2c_dev
, I2C_BUS_CLEAR_STATUS
);
1149 if (!(reg
& I2C_BC_STATUS
)) {
1150 dev_err(i2c_dev
->dev
,
1151 "un-recovered arbitration lost\n");
1158 static int tegra_i2c_xfer_msg(struct tegra_i2c_dev
*i2c_dev
,
1159 struct i2c_msg
*msg
,
1160 enum msg_end_type end_state
)
1164 unsigned long time_left
;
1169 u16 xfer_time
= 100;
1171 err
= tegra_i2c_flush_fifos(i2c_dev
);
1175 i2c_dev
->msg_buf
= msg
->buf
;
1176 i2c_dev
->msg_buf_remaining
= msg
->len
;
1177 i2c_dev
->msg_err
= I2C_ERR_NONE
;
1178 i2c_dev
->msg_read
= (msg
->flags
& I2C_M_RD
);
1179 reinit_completion(&i2c_dev
->msg_complete
);
1181 if (i2c_dev
->msg_read
)
1182 xfer_size
= msg
->len
;
1184 xfer_size
= msg
->len
+ I2C_PACKET_HEADER_SIZE
;
1186 xfer_size
= ALIGN(xfer_size
, BYTES_PER_FIFO_WORD
);
1187 i2c_dev
->is_curr_dma_xfer
= (xfer_size
> I2C_PIO_MODE_PREFERRED_LEN
) &&
1189 !i2c_dev
->is_curr_atomic_xfer
;
1190 tegra_i2c_config_fifo_trig(i2c_dev
, xfer_size
);
1191 dma
= i2c_dev
->is_curr_dma_xfer
;
1193 * Transfer time in mSec = Total bits / transfer rate
1194 * Total bits = 9 bits per byte (including ACK bit) + Start & stop bits
1196 xfer_time
+= DIV_ROUND_CLOSEST(((xfer_size
* 9) + 2) * MSEC_PER_SEC
,
1197 i2c_dev
->bus_clk_rate
);
1199 int_mask
= I2C_INT_NO_ACK
| I2C_INT_ARBITRATION_LOST
;
1200 tegra_i2c_unmask_irq(i2c_dev
, int_mask
);
1202 if (i2c_dev
->msg_read
) {
1203 dma_sync_single_for_device(i2c_dev
->dev
,
1207 err
= tegra_i2c_dma_submit(i2c_dev
, xfer_size
);
1209 dev_err(i2c_dev
->dev
,
1210 "starting RX DMA failed, err %d\n",
1216 dma_sync_single_for_cpu(i2c_dev
->dev
,
1220 buffer
= i2c_dev
->dma_buf
;
1224 packet_header
= FIELD_PREP(PACKET_HEADER0_HEADER_SIZE
, 0) |
1225 FIELD_PREP(PACKET_HEADER0_PROTOCOL
,
1226 PACKET_HEADER0_PROTOCOL_I2C
) |
1227 FIELD_PREP(PACKET_HEADER0_CONT_ID
, i2c_dev
->cont_id
) |
1228 FIELD_PREP(PACKET_HEADER0_PACKET_ID
, 1);
1229 if (dma
&& !i2c_dev
->msg_read
)
1230 *buffer
++ = packet_header
;
1232 i2c_writel(i2c_dev
, packet_header
, I2C_TX_FIFO
);
1234 packet_header
= msg
->len
- 1;
1235 if (dma
&& !i2c_dev
->msg_read
)
1236 *buffer
++ = packet_header
;
1238 i2c_writel(i2c_dev
, packet_header
, I2C_TX_FIFO
);
1240 packet_header
= I2C_HEADER_IE_ENABLE
;
1241 if (end_state
== MSG_END_CONTINUE
)
1242 packet_header
|= I2C_HEADER_CONTINUE_XFER
;
1243 else if (end_state
== MSG_END_REPEAT_START
)
1244 packet_header
|= I2C_HEADER_REPEAT_START
;
1245 if (msg
->flags
& I2C_M_TEN
) {
1246 packet_header
|= msg
->addr
;
1247 packet_header
|= I2C_HEADER_10BIT_ADDR
;
1249 packet_header
|= msg
->addr
<< I2C_HEADER_SLAVE_ADDR_SHIFT
;
1251 if (msg
->flags
& I2C_M_IGNORE_NAK
)
1252 packet_header
|= I2C_HEADER_CONT_ON_NAK
;
1253 if (msg
->flags
& I2C_M_RD
)
1254 packet_header
|= I2C_HEADER_READ
;
1255 if (dma
&& !i2c_dev
->msg_read
)
1256 *buffer
++ = packet_header
;
1258 i2c_writel(i2c_dev
, packet_header
, I2C_TX_FIFO
);
1260 if (!i2c_dev
->msg_read
) {
1262 memcpy(buffer
, msg
->buf
, msg
->len
);
1263 dma_sync_single_for_device(i2c_dev
->dev
,
1267 err
= tegra_i2c_dma_submit(i2c_dev
, xfer_size
);
1269 dev_err(i2c_dev
->dev
,
1270 "starting TX DMA failed, err %d\n",
1275 tegra_i2c_fill_tx_fifo(i2c_dev
);
1279 if (i2c_dev
->hw
->has_per_pkt_xfer_complete_irq
)
1280 int_mask
|= I2C_INT_PACKET_XFER_COMPLETE
;
1282 if (msg
->flags
& I2C_M_RD
)
1283 int_mask
|= I2C_INT_RX_FIFO_DATA_REQ
;
1284 else if (i2c_dev
->msg_buf_remaining
)
1285 int_mask
|= I2C_INT_TX_FIFO_DATA_REQ
;
1288 tegra_i2c_unmask_irq(i2c_dev
, int_mask
);
1289 dev_dbg(i2c_dev
->dev
, "unmasked irq: %02x\n",
1290 i2c_readl(i2c_dev
, I2C_INT_MASK
));
1293 time_left
= tegra_i2c_wait_completion_timeout(
1294 i2c_dev
, &i2c_dev
->dma_complete
, xfer_time
);
1297 * Synchronize DMA first, since dmaengine_terminate_sync()
1298 * performs synchronization after the transfer's termination
1299 * and we want to get a completion if transfer succeeded.
1301 dmaengine_synchronize(i2c_dev
->msg_read
?
1302 i2c_dev
->rx_dma_chan
:
1303 i2c_dev
->tx_dma_chan
);
1305 dmaengine_terminate_sync(i2c_dev
->msg_read
?
1306 i2c_dev
->rx_dma_chan
:
1307 i2c_dev
->tx_dma_chan
);
1309 if (!time_left
&& !completion_done(&i2c_dev
->dma_complete
)) {
1310 dev_err(i2c_dev
->dev
, "DMA transfer timeout\n");
1311 tegra_i2c_init(i2c_dev
);
1315 if (i2c_dev
->msg_read
&& i2c_dev
->msg_err
== I2C_ERR_NONE
) {
1316 dma_sync_single_for_cpu(i2c_dev
->dev
,
1320 memcpy(i2c_dev
->msg_buf
, i2c_dev
->dma_buf
,
1325 time_left
= tegra_i2c_wait_completion_timeout(
1326 i2c_dev
, &i2c_dev
->msg_complete
, xfer_time
);
1328 tegra_i2c_mask_irq(i2c_dev
, int_mask
);
1330 if (time_left
== 0) {
1331 dev_err(i2c_dev
->dev
, "i2c transfer timed out\n");
1332 tegra_i2c_init(i2c_dev
);
1336 dev_dbg(i2c_dev
->dev
, "transfer complete: %lu %d %d\n",
1337 time_left
, completion_done(&i2c_dev
->msg_complete
),
1340 i2c_dev
->is_curr_dma_xfer
= false;
1341 if (likely(i2c_dev
->msg_err
== I2C_ERR_NONE
))
1344 tegra_i2c_init(i2c_dev
);
1345 /* start recovery upon arbitration loss in single master mode */
1346 if (i2c_dev
->msg_err
== I2C_ERR_ARBITRATION_LOST
) {
1347 if (!i2c_dev
->is_multimaster_mode
)
1348 return i2c_recover_bus(&i2c_dev
->adapter
);
1352 if (i2c_dev
->msg_err
== I2C_ERR_NO_ACK
) {
1353 if (msg
->flags
& I2C_M_IGNORE_NAK
)
1361 static int tegra_i2c_xfer(struct i2c_adapter
*adap
, struct i2c_msg msgs
[],
1364 struct tegra_i2c_dev
*i2c_dev
= i2c_get_adapdata(adap
);
1368 ret
= pm_runtime_get_sync(i2c_dev
->dev
);
1370 dev_err(i2c_dev
->dev
, "runtime resume failed %d\n", ret
);
1371 pm_runtime_put_noidle(i2c_dev
->dev
);
1375 for (i
= 0; i
< num
; i
++) {
1376 enum msg_end_type end_type
= MSG_END_STOP
;
1378 if (i
< (num
- 1)) {
1379 if (msgs
[i
+ 1].flags
& I2C_M_NOSTART
)
1380 end_type
= MSG_END_CONTINUE
;
1382 end_type
= MSG_END_REPEAT_START
;
1384 ret
= tegra_i2c_xfer_msg(i2c_dev
, &msgs
[i
], end_type
);
1389 pm_runtime_put(i2c_dev
->dev
);
1394 static int tegra_i2c_xfer_atomic(struct i2c_adapter
*adap
,
1395 struct i2c_msg msgs
[], int num
)
1397 struct tegra_i2c_dev
*i2c_dev
= i2c_get_adapdata(adap
);
1400 i2c_dev
->is_curr_atomic_xfer
= true;
1401 ret
= tegra_i2c_xfer(adap
, msgs
, num
);
1402 i2c_dev
->is_curr_atomic_xfer
= false;
1407 static u32
tegra_i2c_func(struct i2c_adapter
*adap
)
1409 struct tegra_i2c_dev
*i2c_dev
= i2c_get_adapdata(adap
);
1410 u32 ret
= I2C_FUNC_I2C
| (I2C_FUNC_SMBUS_EMUL
& ~I2C_FUNC_SMBUS_QUICK
) |
1411 I2C_FUNC_10BIT_ADDR
| I2C_FUNC_PROTOCOL_MANGLING
;
1413 if (i2c_dev
->hw
->has_continue_xfer_support
)
1414 ret
|= I2C_FUNC_NOSTART
;
1418 static void tegra_i2c_parse_dt(struct tegra_i2c_dev
*i2c_dev
)
1420 struct device_node
*np
= i2c_dev
->dev
->of_node
;
1424 ret
= of_property_read_u32(np
, "clock-frequency",
1425 &i2c_dev
->bus_clk_rate
);
1427 i2c_dev
->bus_clk_rate
= I2C_MAX_STANDARD_MODE_FREQ
; /* default clock rate */
1429 multi_mode
= of_property_read_bool(np
, "multi-master");
1430 i2c_dev
->is_multimaster_mode
= multi_mode
;
1433 static const struct i2c_algorithm tegra_i2c_algo
= {
1434 .master_xfer
= tegra_i2c_xfer
,
1435 .master_xfer_atomic
= tegra_i2c_xfer_atomic
,
1436 .functionality
= tegra_i2c_func
,
1439 /* payload size is only 12 bit */
1440 static const struct i2c_adapter_quirks tegra_i2c_quirks
= {
1441 .flags
= I2C_AQ_NO_ZERO_LEN
,
1442 .max_read_len
= SZ_4K
,
1443 .max_write_len
= SZ_4K
- I2C_PACKET_HEADER_SIZE
,
1446 static const struct i2c_adapter_quirks tegra194_i2c_quirks
= {
1447 .flags
= I2C_AQ_NO_ZERO_LEN
,
1448 .max_write_len
= SZ_64K
- I2C_PACKET_HEADER_SIZE
,
1451 static struct i2c_bus_recovery_info tegra_i2c_recovery_info
= {
1452 .recover_bus
= tegra_i2c_issue_bus_clear
,
1455 static const struct tegra_i2c_hw_feature tegra20_i2c_hw
= {
1456 .has_continue_xfer_support
= false,
1457 .has_per_pkt_xfer_complete_irq
= false,
1458 .clk_divisor_hs_mode
= 3,
1459 .clk_divisor_std_mode
= 0,
1460 .clk_divisor_fast_mode
= 0,
1461 .clk_divisor_fast_plus_mode
= 0,
1462 .has_config_load_reg
= false,
1463 .has_multi_master_mode
= false,
1464 .has_slcg_override_reg
= false,
1465 .has_mst_fifo
= false,
1466 .quirks
= &tegra_i2c_quirks
,
1467 .supports_bus_clear
= false,
1468 .has_apb_dma
= true,
1469 .tlow_std_mode
= 0x4,
1470 .thigh_std_mode
= 0x2,
1471 .tlow_fast_fastplus_mode
= 0x4,
1472 .thigh_fast_fastplus_mode
= 0x2,
1473 .setup_hold_time_std_mode
= 0x0,
1474 .setup_hold_time_fast_fast_plus_mode
= 0x0,
1475 .setup_hold_time_hs_mode
= 0x0,
1476 .has_interface_timing_reg
= false,
1479 static const struct tegra_i2c_hw_feature tegra30_i2c_hw
= {
1480 .has_continue_xfer_support
= true,
1481 .has_per_pkt_xfer_complete_irq
= false,
1482 .clk_divisor_hs_mode
= 3,
1483 .clk_divisor_std_mode
= 0,
1484 .clk_divisor_fast_mode
= 0,
1485 .clk_divisor_fast_plus_mode
= 0,
1486 .has_config_load_reg
= false,
1487 .has_multi_master_mode
= false,
1488 .has_slcg_override_reg
= false,
1489 .has_mst_fifo
= false,
1490 .quirks
= &tegra_i2c_quirks
,
1491 .supports_bus_clear
= false,
1492 .has_apb_dma
= true,
1493 .tlow_std_mode
= 0x4,
1494 .thigh_std_mode
= 0x2,
1495 .tlow_fast_fastplus_mode
= 0x4,
1496 .thigh_fast_fastplus_mode
= 0x2,
1497 .setup_hold_time_std_mode
= 0x0,
1498 .setup_hold_time_fast_fast_plus_mode
= 0x0,
1499 .setup_hold_time_hs_mode
= 0x0,
1500 .has_interface_timing_reg
= false,
1503 static const struct tegra_i2c_hw_feature tegra114_i2c_hw
= {
1504 .has_continue_xfer_support
= true,
1505 .has_per_pkt_xfer_complete_irq
= true,
1506 .clk_divisor_hs_mode
= 1,
1507 .clk_divisor_std_mode
= 0x19,
1508 .clk_divisor_fast_mode
= 0x19,
1509 .clk_divisor_fast_plus_mode
= 0x10,
1510 .has_config_load_reg
= false,
1511 .has_multi_master_mode
= false,
1512 .has_slcg_override_reg
= false,
1513 .has_mst_fifo
= false,
1514 .quirks
= &tegra_i2c_quirks
,
1515 .supports_bus_clear
= true,
1516 .has_apb_dma
= true,
1517 .tlow_std_mode
= 0x4,
1518 .thigh_std_mode
= 0x2,
1519 .tlow_fast_fastplus_mode
= 0x4,
1520 .thigh_fast_fastplus_mode
= 0x2,
1521 .setup_hold_time_std_mode
= 0x0,
1522 .setup_hold_time_fast_fast_plus_mode
= 0x0,
1523 .setup_hold_time_hs_mode
= 0x0,
1524 .has_interface_timing_reg
= false,
1527 static const struct tegra_i2c_hw_feature tegra124_i2c_hw
= {
1528 .has_continue_xfer_support
= true,
1529 .has_per_pkt_xfer_complete_irq
= true,
1530 .clk_divisor_hs_mode
= 1,
1531 .clk_divisor_std_mode
= 0x19,
1532 .clk_divisor_fast_mode
= 0x19,
1533 .clk_divisor_fast_plus_mode
= 0x10,
1534 .has_config_load_reg
= true,
1535 .has_multi_master_mode
= false,
1536 .has_slcg_override_reg
= true,
1537 .has_mst_fifo
= false,
1538 .quirks
= &tegra_i2c_quirks
,
1539 .supports_bus_clear
= true,
1540 .has_apb_dma
= true,
1541 .tlow_std_mode
= 0x4,
1542 .thigh_std_mode
= 0x2,
1543 .tlow_fast_fastplus_mode
= 0x4,
1544 .thigh_fast_fastplus_mode
= 0x2,
1545 .setup_hold_time_std_mode
= 0x0,
1546 .setup_hold_time_fast_fast_plus_mode
= 0x0,
1547 .setup_hold_time_hs_mode
= 0x0,
1548 .has_interface_timing_reg
= true,
1551 static const struct tegra_i2c_hw_feature tegra210_i2c_hw
= {
1552 .has_continue_xfer_support
= true,
1553 .has_per_pkt_xfer_complete_irq
= true,
1554 .clk_divisor_hs_mode
= 1,
1555 .clk_divisor_std_mode
= 0x19,
1556 .clk_divisor_fast_mode
= 0x19,
1557 .clk_divisor_fast_plus_mode
= 0x10,
1558 .has_config_load_reg
= true,
1559 .has_multi_master_mode
= false,
1560 .has_slcg_override_reg
= true,
1561 .has_mst_fifo
= false,
1562 .quirks
= &tegra_i2c_quirks
,
1563 .supports_bus_clear
= true,
1564 .has_apb_dma
= true,
1565 .tlow_std_mode
= 0x4,
1566 .thigh_std_mode
= 0x2,
1567 .tlow_fast_fastplus_mode
= 0x4,
1568 .thigh_fast_fastplus_mode
= 0x2,
1569 .setup_hold_time_std_mode
= 0,
1570 .setup_hold_time_fast_fast_plus_mode
= 0,
1571 .setup_hold_time_hs_mode
= 0,
1572 .has_interface_timing_reg
= true,
1575 static const struct tegra_i2c_hw_feature tegra186_i2c_hw
= {
1576 .has_continue_xfer_support
= true,
1577 .has_per_pkt_xfer_complete_irq
= true,
1578 .clk_divisor_hs_mode
= 1,
1579 .clk_divisor_std_mode
= 0x16,
1580 .clk_divisor_fast_mode
= 0x19,
1581 .clk_divisor_fast_plus_mode
= 0x10,
1582 .has_config_load_reg
= true,
1583 .has_multi_master_mode
= false,
1584 .has_slcg_override_reg
= true,
1585 .has_mst_fifo
= false,
1586 .quirks
= &tegra_i2c_quirks
,
1587 .supports_bus_clear
= true,
1588 .has_apb_dma
= false,
1589 .tlow_std_mode
= 0x4,
1590 .thigh_std_mode
= 0x3,
1591 .tlow_fast_fastplus_mode
= 0x4,
1592 .thigh_fast_fastplus_mode
= 0x2,
1593 .setup_hold_time_std_mode
= 0,
1594 .setup_hold_time_fast_fast_plus_mode
= 0,
1595 .setup_hold_time_hs_mode
= 0,
1596 .has_interface_timing_reg
= true,
1599 static const struct tegra_i2c_hw_feature tegra194_i2c_hw
= {
1600 .has_continue_xfer_support
= true,
1601 .has_per_pkt_xfer_complete_irq
= true,
1602 .clk_divisor_hs_mode
= 1,
1603 .clk_divisor_std_mode
= 0x4f,
1604 .clk_divisor_fast_mode
= 0x3c,
1605 .clk_divisor_fast_plus_mode
= 0x16,
1606 .has_config_load_reg
= true,
1607 .has_multi_master_mode
= true,
1608 .has_slcg_override_reg
= true,
1609 .has_mst_fifo
= true,
1610 .quirks
= &tegra194_i2c_quirks
,
1611 .supports_bus_clear
= true,
1612 .has_apb_dma
= false,
1613 .tlow_std_mode
= 0x8,
1614 .thigh_std_mode
= 0x7,
1615 .tlow_fast_fastplus_mode
= 0x2,
1616 .thigh_fast_fastplus_mode
= 0x2,
1617 .setup_hold_time_std_mode
= 0x08080808,
1618 .setup_hold_time_fast_fast_plus_mode
= 0x02020202,
1619 .setup_hold_time_hs_mode
= 0x090909,
1620 .has_interface_timing_reg
= true,
1623 /* Match table for of_platform binding */
1624 static const struct of_device_id tegra_i2c_of_match
[] = {
1625 { .compatible
= "nvidia,tegra194-i2c", .data
= &tegra194_i2c_hw
, },
1626 { .compatible
= "nvidia,tegra186-i2c", .data
= &tegra186_i2c_hw
, },
1627 { .compatible
= "nvidia,tegra210-i2c-vi", .data
= &tegra210_i2c_hw
, },
1628 { .compatible
= "nvidia,tegra210-i2c", .data
= &tegra210_i2c_hw
, },
1629 { .compatible
= "nvidia,tegra124-i2c", .data
= &tegra124_i2c_hw
, },
1630 { .compatible
= "nvidia,tegra114-i2c", .data
= &tegra114_i2c_hw
, },
1631 { .compatible
= "nvidia,tegra30-i2c", .data
= &tegra30_i2c_hw
, },
1632 { .compatible
= "nvidia,tegra20-i2c", .data
= &tegra20_i2c_hw
, },
1633 { .compatible
= "nvidia,tegra20-i2c-dvc", .data
= &tegra20_i2c_hw
, },
1636 MODULE_DEVICE_TABLE(of
, tegra_i2c_of_match
);
1638 static int tegra_i2c_init_clocks(struct tegra_i2c_dev
*i2c_dev
)
1642 i2c_dev
->clocks
[i2c_dev
->nclocks
++].id
= "div-clk";
1644 if (i2c_dev
->hw
== &tegra20_i2c_hw
|| i2c_dev
->hw
== &tegra30_i2c_hw
)
1645 i2c_dev
->clocks
[i2c_dev
->nclocks
++].id
= "fast-clk";
1648 i2c_dev
->clocks
[i2c_dev
->nclocks
++].id
= "slow";
1650 err
= devm_clk_bulk_get(i2c_dev
->dev
, i2c_dev
->nclocks
,
1655 err
= clk_bulk_prepare(i2c_dev
->nclocks
, i2c_dev
->clocks
);
1659 i2c_dev
->div_clk
= i2c_dev
->clocks
[0].clk
;
1661 if (!i2c_dev
->is_multimaster_mode
)
1664 err
= clk_enable(i2c_dev
->div_clk
);
1666 dev_err(i2c_dev
->dev
, "failed to enable div-clk: %d\n", err
);
1667 goto unprepare_clocks
;
1673 clk_bulk_unprepare(i2c_dev
->nclocks
, i2c_dev
->clocks
);
1678 static void tegra_i2c_release_clocks(struct tegra_i2c_dev
*i2c_dev
)
1680 if (i2c_dev
->is_multimaster_mode
)
1681 clk_disable(i2c_dev
->div_clk
);
1683 clk_bulk_unprepare(i2c_dev
->nclocks
, i2c_dev
->clocks
);
1686 static int tegra_i2c_probe(struct platform_device
*pdev
)
1688 struct device
*dev
= &pdev
->dev
;
1689 struct tegra_i2c_dev
*i2c_dev
;
1690 struct resource
*res
;
1692 phys_addr_t base_phys
;
1696 base
= devm_platform_get_and_ioremap_resource(pdev
, 0, &res
);
1698 return PTR_ERR(base
);
1700 base_phys
= res
->start
;
1702 irq
= platform_get_irq(pdev
, 0);
1706 i2c_dev
= devm_kzalloc(&pdev
->dev
, sizeof(*i2c_dev
), GFP_KERNEL
);
1710 i2c_dev
->base
= base
;
1711 i2c_dev
->base_phys
= base_phys
;
1712 i2c_dev
->adapter
.algo
= &tegra_i2c_algo
;
1713 i2c_dev
->adapter
.retries
= 1;
1714 i2c_dev
->adapter
.timeout
= 6 * HZ
;
1716 i2c_dev
->cont_id
= pdev
->id
;
1717 i2c_dev
->dev
= &pdev
->dev
;
1719 i2c_dev
->rst
= devm_reset_control_get_exclusive(&pdev
->dev
, "i2c");
1720 if (IS_ERR(i2c_dev
->rst
)) {
1721 dev_err_probe(&pdev
->dev
, PTR_ERR(i2c_dev
->rst
),
1722 "failed to get reset control\n");
1723 return PTR_ERR(i2c_dev
->rst
);
1726 tegra_i2c_parse_dt(i2c_dev
);
1728 ret
= tegra_i2c_init_clocks(i2c_dev
);
1732 i2c_dev
->hw
= of_device_get_match_data(&pdev
->dev
);
1733 i2c_dev
->is_dvc
= of_device_is_compatible(pdev
->dev
.of_node
,
1734 "nvidia,tegra20-i2c-dvc");
1735 i2c_dev
->is_vi
= of_device_is_compatible(dev
->of_node
,
1736 "nvidia,tegra210-i2c-vi");
1737 i2c_dev
->adapter
.quirks
= i2c_dev
->hw
->quirks
;
1738 i2c_dev
->dma_buf_size
= i2c_dev
->adapter
.quirks
->max_write_len
+
1739 I2C_PACKET_HEADER_SIZE
;
1740 init_completion(&i2c_dev
->msg_complete
);
1741 init_completion(&i2c_dev
->dma_complete
);
1743 platform_set_drvdata(pdev
, i2c_dev
);
1746 * VI I2C is in VE power domain which is not always on and not
1747 * an IRQ safe. So, IRQ safe device can't be attached to a non-IRQ
1748 * safe domain as it prevents powering off the PM domain.
1749 * Also, VI I2C device don't need to use runtime IRQ safe as it will
1750 * not be used for atomic transfers.
1752 if (!i2c_dev
->is_vi
)
1753 pm_runtime_irq_safe(&pdev
->dev
);
1754 pm_runtime_enable(&pdev
->dev
);
1755 ret
= pm_runtime_get_sync(i2c_dev
->dev
);
1757 dev_err(dev
, "runtime resume failed\n");
1761 if (i2c_dev
->hw
->supports_bus_clear
)
1762 i2c_dev
->adapter
.bus_recovery_info
= &tegra_i2c_recovery_info
;
1764 ret
= tegra_i2c_init_dma(i2c_dev
);
1768 ret
= tegra_i2c_init(i2c_dev
);
1770 dev_err(&pdev
->dev
, "Failed to initialize i2c controller\n");
1774 irq_set_status_flags(i2c_dev
->irq
, IRQ_NOAUTOEN
);
1776 ret
= devm_request_irq(&pdev
->dev
, i2c_dev
->irq
, tegra_i2c_isr
,
1777 IRQF_NO_SUSPEND
, dev_name(&pdev
->dev
), i2c_dev
);
1781 i2c_set_adapdata(&i2c_dev
->adapter
, i2c_dev
);
1782 i2c_dev
->adapter
.owner
= THIS_MODULE
;
1783 i2c_dev
->adapter
.class = I2C_CLASS_DEPRECATED
;
1784 strlcpy(i2c_dev
->adapter
.name
, dev_name(&pdev
->dev
),
1785 sizeof(i2c_dev
->adapter
.name
));
1786 i2c_dev
->adapter
.dev
.parent
= &pdev
->dev
;
1787 i2c_dev
->adapter
.nr
= pdev
->id
;
1788 i2c_dev
->adapter
.dev
.of_node
= pdev
->dev
.of_node
;
1790 ret
= i2c_add_numbered_adapter(&i2c_dev
->adapter
);
1794 pm_runtime_put(&pdev
->dev
);
1799 tegra_i2c_release_dma(i2c_dev
);
1802 pm_runtime_put_sync(&pdev
->dev
);
1803 pm_runtime_disable(&pdev
->dev
);
1804 tegra_i2c_release_clocks(i2c_dev
);
1809 static int tegra_i2c_remove(struct platform_device
*pdev
)
1811 struct tegra_i2c_dev
*i2c_dev
= platform_get_drvdata(pdev
);
1813 i2c_del_adapter(&i2c_dev
->adapter
);
1815 pm_runtime_disable(&pdev
->dev
);
1817 tegra_i2c_release_dma(i2c_dev
);
1818 tegra_i2c_release_clocks(i2c_dev
);
1822 static int __maybe_unused
tegra_i2c_suspend(struct device
*dev
)
1824 struct tegra_i2c_dev
*i2c_dev
= dev_get_drvdata(dev
);
1827 i2c_mark_adapter_suspended(&i2c_dev
->adapter
);
1829 if (!pm_runtime_status_suspended(dev
))
1830 err
= tegra_i2c_runtime_suspend(dev
);
1835 static int __maybe_unused
tegra_i2c_resume(struct device
*dev
)
1837 struct tegra_i2c_dev
*i2c_dev
= dev_get_drvdata(dev
);
1841 * We need to ensure that clocks are enabled so that registers can be
1842 * restored in tegra_i2c_init().
1844 err
= tegra_i2c_runtime_resume(dev
);
1848 err
= tegra_i2c_init(i2c_dev
);
1853 * In case we are runtime suspended, disable clocks again so that we
1854 * don't unbalance the clock reference counts during the next runtime
1855 * resume transition.
1857 if (pm_runtime_status_suspended(dev
)) {
1858 err
= tegra_i2c_runtime_suspend(dev
);
1863 i2c_mark_adapter_resumed(&i2c_dev
->adapter
);
1868 static const struct dev_pm_ops tegra_i2c_pm
= {
1869 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(tegra_i2c_suspend
, tegra_i2c_resume
)
1870 SET_RUNTIME_PM_OPS(tegra_i2c_runtime_suspend
, tegra_i2c_runtime_resume
,
1874 static struct platform_driver tegra_i2c_driver
= {
1875 .probe
= tegra_i2c_probe
,
1876 .remove
= tegra_i2c_remove
,
1878 .name
= "tegra-i2c",
1879 .of_match_table
= tegra_i2c_of_match
,
1880 .pm
= &tegra_i2c_pm
,
1884 module_platform_driver(tegra_i2c_driver
);
1886 MODULE_DESCRIPTION("nVidia Tegra2 I2C Bus Controller driver");
1887 MODULE_AUTHOR("Colin Cross");
1888 MODULE_LICENSE("GPL v2");