3 * Copyright (c) 2002-2007 Xilinx Inc.
4 * Copyright (c) 2009-2010 Intel Corporation
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20 * This code was implemented by Mocean Laboratories AB when porting linux
21 * to the automotive development board Russellville. The copyright holder
22 * as seen in the header is Intel corporation.
23 * Mocean Laboratories forked off the GNU/Linux platform work into a
24 * separate company called Pelagicore AB, which committed the code to the
31 #include <linux/kernel.h>
32 #include <linux/module.h>
33 #include <linux/init.h>
34 #include <linux/errno.h>
35 #include <linux/delay.h>
36 #include <linux/platform_device.h>
37 #include <linux/mfd/core.h>
38 #include <linux/i2c.h>
39 #include <linux/interrupt.h>
40 #include <linux/wait.h>
41 #include <linux/i2c-xiic.h>
43 #include <linux/slab.h>
45 #define DRIVER_NAME "xiic-i2c"
47 enum xilinx_i2c_state
{
54 * struct xiic_i2c - Internal representation of the XIIC I2C bus
55 * @base: Memory base of the HW registers
56 * @wait: Wait queue for callers
57 * @adap: Kernel adapter representation
58 * @tx_msg: Messages from above to be sent
59 * @lock: Mutual exclusion
60 * @tx_pos: Current pos in TX message
61 * @nmsgs: Number of messages in tx_msg
63 * @rx_msg: Current RX message
64 * @rx_pos: Position within current RX message
68 wait_queue_head_t wait
;
69 struct i2c_adapter adap
;
70 struct i2c_msg
*tx_msg
;
74 enum xilinx_i2c_state state
;
75 struct i2c_msg
*rx_msg
;
80 #define XIIC_MSB_OFFSET 0
81 #define XIIC_REG_OFFSET (0x100+XIIC_MSB_OFFSET)
84 * Register offsets in bytes from RegisterBase. Three is added to the
85 * base offset to access LSB (IBM style) of the word
87 #define XIIC_CR_REG_OFFSET (0x00+XIIC_REG_OFFSET) /* Control Register */
88 #define XIIC_SR_REG_OFFSET (0x04+XIIC_REG_OFFSET) /* Status Register */
89 #define XIIC_DTR_REG_OFFSET (0x08+XIIC_REG_OFFSET) /* Data Tx Register */
90 #define XIIC_DRR_REG_OFFSET (0x0C+XIIC_REG_OFFSET) /* Data Rx Register */
91 #define XIIC_ADR_REG_OFFSET (0x10+XIIC_REG_OFFSET) /* Address Register */
92 #define XIIC_TFO_REG_OFFSET (0x14+XIIC_REG_OFFSET) /* Tx FIFO Occupancy */
93 #define XIIC_RFO_REG_OFFSET (0x18+XIIC_REG_OFFSET) /* Rx FIFO Occupancy */
94 #define XIIC_TBA_REG_OFFSET (0x1C+XIIC_REG_OFFSET) /* 10 Bit Address reg */
95 #define XIIC_RFD_REG_OFFSET (0x20+XIIC_REG_OFFSET) /* Rx FIFO Depth reg */
96 #define XIIC_GPO_REG_OFFSET (0x24+XIIC_REG_OFFSET) /* Output Register */
98 /* Control Register masks */
99 #define XIIC_CR_ENABLE_DEVICE_MASK 0x01 /* Device enable = 1 */
100 #define XIIC_CR_TX_FIFO_RESET_MASK 0x02 /* Transmit FIFO reset=1 */
101 #define XIIC_CR_MSMS_MASK 0x04 /* Master starts Txing=1 */
102 #define XIIC_CR_DIR_IS_TX_MASK 0x08 /* Dir of tx. Txing=1 */
103 #define XIIC_CR_NO_ACK_MASK 0x10 /* Tx Ack. NO ack = 1 */
104 #define XIIC_CR_REPEATED_START_MASK 0x20 /* Repeated start = 1 */
105 #define XIIC_CR_GENERAL_CALL_MASK 0x40 /* Gen Call enabled = 1 */
107 /* Status Register masks */
108 #define XIIC_SR_GEN_CALL_MASK 0x01 /* 1=a mstr issued a GC */
109 #define XIIC_SR_ADDR_AS_SLAVE_MASK 0x02 /* 1=when addr as slave */
110 #define XIIC_SR_BUS_BUSY_MASK 0x04 /* 1 = bus is busy */
111 #define XIIC_SR_MSTR_RDING_SLAVE_MASK 0x08 /* 1=Dir: mstr <-- slave */
112 #define XIIC_SR_TX_FIFO_FULL_MASK 0x10 /* 1 = Tx FIFO full */
113 #define XIIC_SR_RX_FIFO_FULL_MASK 0x20 /* 1 = Rx FIFO full */
114 #define XIIC_SR_RX_FIFO_EMPTY_MASK 0x40 /* 1 = Rx FIFO empty */
115 #define XIIC_SR_TX_FIFO_EMPTY_MASK 0x80 /* 1 = Tx FIFO empty */
117 /* Interrupt Status Register masks Interrupt occurs when... */
118 #define XIIC_INTR_ARB_LOST_MASK 0x01 /* 1 = arbitration lost */
119 #define XIIC_INTR_TX_ERROR_MASK 0x02 /* 1=Tx error/msg complete */
120 #define XIIC_INTR_TX_EMPTY_MASK 0x04 /* 1 = Tx FIFO/reg empty */
121 #define XIIC_INTR_RX_FULL_MASK 0x08 /* 1=Rx FIFO/reg=OCY level */
122 #define XIIC_INTR_BNB_MASK 0x10 /* 1 = Bus not busy */
123 #define XIIC_INTR_AAS_MASK 0x20 /* 1 = when addr as slave */
124 #define XIIC_INTR_NAAS_MASK 0x40 /* 1 = not addr as slave */
125 #define XIIC_INTR_TX_HALF_MASK 0x80 /* 1 = TX FIFO half empty */
127 /* The following constants specify the depth of the FIFOs */
128 #define IIC_RX_FIFO_DEPTH 16 /* Rx fifo capacity */
129 #define IIC_TX_FIFO_DEPTH 16 /* Tx fifo capacity */
131 /* The following constants specify groups of interrupts that are typically
132 * enabled or disables at the same time
134 #define XIIC_TX_INTERRUPTS \
135 (XIIC_INTR_TX_ERROR_MASK | XIIC_INTR_TX_EMPTY_MASK | XIIC_INTR_TX_HALF_MASK)
137 #define XIIC_TX_RX_INTERRUPTS (XIIC_INTR_RX_FULL_MASK | XIIC_TX_INTERRUPTS)
139 /* The following constants are used with the following macros to specify the
140 * operation, a read or write operation.
142 #define XIIC_READ_OPERATION 1
143 #define XIIC_WRITE_OPERATION 0
146 * Tx Fifo upper bit masks.
148 #define XIIC_TX_DYN_START_MASK 0x0100 /* 1 = Set dynamic start */
149 #define XIIC_TX_DYN_STOP_MASK 0x0200 /* 1 = Set dynamic stop */
152 * The following constants define the register offsets for the Interrupt
153 * registers. There are some holes in the memory map for reserved addresses
154 * to allow other registers to be added and still match the memory map of the
155 * interrupt controller registers
157 #define XIIC_DGIER_OFFSET 0x1C /* Device Global Interrupt Enable Register */
158 #define XIIC_IISR_OFFSET 0x20 /* Interrupt Status Register */
159 #define XIIC_IIER_OFFSET 0x28 /* Interrupt Enable Register */
160 #define XIIC_RESETR_OFFSET 0x40 /* Reset Register */
162 #define XIIC_RESET_MASK 0xAUL
165 * The following constant is used for the device global interrupt enable
166 * register, to enable all interrupts for the device, this is the only bit
169 #define XIIC_GINTR_ENABLE_MASK 0x80000000UL
171 #define xiic_tx_space(i2c) ((i2c)->tx_msg->len - (i2c)->tx_pos)
172 #define xiic_rx_space(i2c) ((i2c)->rx_msg->len - (i2c)->rx_pos)
174 static void xiic_start_xfer(struct xiic_i2c
*i2c
);
175 static void __xiic_start_xfer(struct xiic_i2c
*i2c
);
177 static inline void xiic_setreg8(struct xiic_i2c
*i2c
, int reg
, u8 value
)
179 iowrite8(value
, i2c
->base
+ reg
);
182 static inline u8
xiic_getreg8(struct xiic_i2c
*i2c
, int reg
)
184 return ioread8(i2c
->base
+ reg
);
187 static inline void xiic_setreg16(struct xiic_i2c
*i2c
, int reg
, u16 value
)
189 iowrite16(value
, i2c
->base
+ reg
);
192 static inline void xiic_setreg32(struct xiic_i2c
*i2c
, int reg
, int value
)
194 iowrite32(value
, i2c
->base
+ reg
);
197 static inline int xiic_getreg32(struct xiic_i2c
*i2c
, int reg
)
199 return ioread32(i2c
->base
+ reg
);
202 static inline void xiic_irq_dis(struct xiic_i2c
*i2c
, u32 mask
)
204 u32 ier
= xiic_getreg32(i2c
, XIIC_IIER_OFFSET
);
205 xiic_setreg32(i2c
, XIIC_IIER_OFFSET
, ier
& ~mask
);
208 static inline void xiic_irq_en(struct xiic_i2c
*i2c
, u32 mask
)
210 u32 ier
= xiic_getreg32(i2c
, XIIC_IIER_OFFSET
);
211 xiic_setreg32(i2c
, XIIC_IIER_OFFSET
, ier
| mask
);
214 static inline void xiic_irq_clr(struct xiic_i2c
*i2c
, u32 mask
)
216 u32 isr
= xiic_getreg32(i2c
, XIIC_IISR_OFFSET
);
217 xiic_setreg32(i2c
, XIIC_IISR_OFFSET
, isr
& mask
);
220 static inline void xiic_irq_clr_en(struct xiic_i2c
*i2c
, u32 mask
)
222 xiic_irq_clr(i2c
, mask
);
223 xiic_irq_en(i2c
, mask
);
226 static void xiic_clear_rx_fifo(struct xiic_i2c
*i2c
)
229 for (sr
= xiic_getreg8(i2c
, XIIC_SR_REG_OFFSET
);
230 !(sr
& XIIC_SR_RX_FIFO_EMPTY_MASK
);
231 sr
= xiic_getreg8(i2c
, XIIC_SR_REG_OFFSET
))
232 xiic_getreg8(i2c
, XIIC_DRR_REG_OFFSET
);
235 static void xiic_reinit(struct xiic_i2c
*i2c
)
237 xiic_setreg32(i2c
, XIIC_RESETR_OFFSET
, XIIC_RESET_MASK
);
239 /* Set receive Fifo depth to maximum (zero based). */
240 xiic_setreg8(i2c
, XIIC_RFD_REG_OFFSET
, IIC_RX_FIFO_DEPTH
- 1);
243 xiic_setreg8(i2c
, XIIC_CR_REG_OFFSET
, XIIC_CR_TX_FIFO_RESET_MASK
);
245 /* Enable IIC Device, remove Tx Fifo reset & disable general call. */
246 xiic_setreg8(i2c
, XIIC_CR_REG_OFFSET
, XIIC_CR_ENABLE_DEVICE_MASK
);
248 /* make sure RX fifo is empty */
249 xiic_clear_rx_fifo(i2c
);
251 /* Enable interrupts */
252 xiic_setreg32(i2c
, XIIC_DGIER_OFFSET
, XIIC_GINTR_ENABLE_MASK
);
254 xiic_irq_clr_en(i2c
, XIIC_INTR_AAS_MASK
| XIIC_INTR_ARB_LOST_MASK
);
257 static void xiic_deinit(struct xiic_i2c
*i2c
)
261 xiic_setreg32(i2c
, XIIC_RESETR_OFFSET
, XIIC_RESET_MASK
);
263 /* Disable IIC Device. */
264 cr
= xiic_getreg8(i2c
, XIIC_CR_REG_OFFSET
);
265 xiic_setreg8(i2c
, XIIC_CR_REG_OFFSET
, cr
& ~XIIC_CR_ENABLE_DEVICE_MASK
);
268 static void xiic_read_rx(struct xiic_i2c
*i2c
)
273 bytes_in_fifo
= xiic_getreg8(i2c
, XIIC_RFO_REG_OFFSET
) + 1;
275 dev_dbg(i2c
->adap
.dev
.parent
, "%s entry, bytes in fifo: %d, msg: %d"
276 ", SR: 0x%x, CR: 0x%x\n",
277 __func__
, bytes_in_fifo
, xiic_rx_space(i2c
),
278 xiic_getreg8(i2c
, XIIC_SR_REG_OFFSET
),
279 xiic_getreg8(i2c
, XIIC_CR_REG_OFFSET
));
281 if (bytes_in_fifo
> xiic_rx_space(i2c
))
282 bytes_in_fifo
= xiic_rx_space(i2c
);
284 for (i
= 0; i
< bytes_in_fifo
; i
++)
285 i2c
->rx_msg
->buf
[i2c
->rx_pos
++] =
286 xiic_getreg8(i2c
, XIIC_DRR_REG_OFFSET
);
288 xiic_setreg8(i2c
, XIIC_RFD_REG_OFFSET
,
289 (xiic_rx_space(i2c
) > IIC_RX_FIFO_DEPTH
) ?
290 IIC_RX_FIFO_DEPTH
- 1 : xiic_rx_space(i2c
) - 1);
293 static int xiic_tx_fifo_space(struct xiic_i2c
*i2c
)
295 /* return the actual space left in the FIFO */
296 return IIC_TX_FIFO_DEPTH
- xiic_getreg8(i2c
, XIIC_TFO_REG_OFFSET
) - 1;
299 static void xiic_fill_tx_fifo(struct xiic_i2c
*i2c
)
301 u8 fifo_space
= xiic_tx_fifo_space(i2c
);
302 int len
= xiic_tx_space(i2c
);
304 len
= (len
> fifo_space
) ? fifo_space
: len
;
306 dev_dbg(i2c
->adap
.dev
.parent
, "%s entry, len: %d, fifo space: %d\n",
307 __func__
, len
, fifo_space
);
310 u16 data
= i2c
->tx_msg
->buf
[i2c
->tx_pos
++];
311 if ((xiic_tx_space(i2c
) == 0) && (i2c
->nmsgs
== 1)) {
312 /* last message in transfer -> STOP */
313 data
|= XIIC_TX_DYN_STOP_MASK
;
314 dev_dbg(i2c
->adap
.dev
.parent
, "%s TX STOP\n", __func__
);
316 xiic_setreg16(i2c
, XIIC_DTR_REG_OFFSET
, data
);
318 xiic_setreg8(i2c
, XIIC_DTR_REG_OFFSET
, data
);
322 static void xiic_wakeup(struct xiic_i2c
*i2c
, int code
)
331 static void xiic_process(struct xiic_i2c
*i2c
)
336 /* Get the interrupt Status from the IPIF. There is no clearing of
337 * interrupts in the IPIF. Interrupts must be cleared at the source.
338 * To find which interrupts are pending; AND interrupts pending with
341 isr
= xiic_getreg32(i2c
, XIIC_IISR_OFFSET
);
342 ier
= xiic_getreg32(i2c
, XIIC_IIER_OFFSET
);
345 dev_dbg(i2c
->adap
.dev
.parent
, "%s entry, IER: 0x%x, ISR: 0x%x, "
346 "pend: 0x%x, SR: 0x%x, msg: %p, nmsgs: %d\n",
347 __func__
, ier
, isr
, pend
, xiic_getreg8(i2c
, XIIC_SR_REG_OFFSET
),
348 i2c
->tx_msg
, i2c
->nmsgs
);
350 /* Do not processes a devices interrupts if the device has no
356 /* Service requesting interrupt */
357 if ((pend
& XIIC_INTR_ARB_LOST_MASK
) ||
358 ((pend
& XIIC_INTR_TX_ERROR_MASK
) &&
359 !(pend
& XIIC_INTR_RX_FULL_MASK
))) {
360 /* bus arbritration lost, or...
361 * Transmit error _OR_ RX completed
362 * if this happens when RX_FULL is not set
363 * this is probably a TX error
366 dev_dbg(i2c
->adap
.dev
.parent
, "%s error\n", __func__
);
368 /* dynamic mode seem to suffer from problems if we just flushes
369 * fifos and the next message is a TX with len 0 (only addr)
370 * reset the IP instead of just flush fifos
375 xiic_wakeup(i2c
, STATE_ERROR
);
377 } else if (pend
& XIIC_INTR_RX_FULL_MASK
) {
378 /* Receive register/FIFO is full */
380 clr
= XIIC_INTR_RX_FULL_MASK
;
382 dev_dbg(i2c
->adap
.dev
.parent
,
383 "%s unexpexted RX IRQ\n", __func__
);
384 xiic_clear_rx_fifo(i2c
);
389 if (xiic_rx_space(i2c
) == 0) {
390 /* this is the last part of the message */
393 /* also clear TX error if there (RX complete) */
394 clr
|= (isr
& XIIC_INTR_TX_ERROR_MASK
);
396 dev_dbg(i2c
->adap
.dev
.parent
,
397 "%s end of message, nmsgs: %d\n",
398 __func__
, i2c
->nmsgs
);
400 /* send next message if this wasn't the last,
401 * otherwise the transfer will be finialise when
402 * receiving the bus not busy interrupt
404 if (i2c
->nmsgs
> 1) {
407 dev_dbg(i2c
->adap
.dev
.parent
,
408 "%s will start next...\n", __func__
);
410 __xiic_start_xfer(i2c
);
413 } else if (pend
& XIIC_INTR_BNB_MASK
) {
414 /* IIC bus has transitioned to not busy */
415 clr
= XIIC_INTR_BNB_MASK
;
417 /* The bus is not busy, disable BusNotBusy interrupt */
418 xiic_irq_dis(i2c
, XIIC_INTR_BNB_MASK
);
423 if ((i2c
->nmsgs
== 1) && !i2c
->rx_msg
&&
424 xiic_tx_space(i2c
) == 0)
425 xiic_wakeup(i2c
, STATE_DONE
);
427 xiic_wakeup(i2c
, STATE_ERROR
);
429 } else if (pend
& (XIIC_INTR_TX_EMPTY_MASK
| XIIC_INTR_TX_HALF_MASK
)) {
430 /* Transmit register/FIFO is empty or ½ empty */
433 (XIIC_INTR_TX_EMPTY_MASK
| XIIC_INTR_TX_HALF_MASK
);
436 dev_dbg(i2c
->adap
.dev
.parent
,
437 "%s unexpexted TX IRQ\n", __func__
);
441 xiic_fill_tx_fifo(i2c
);
443 /* current message sent and there is space in the fifo */
444 if (!xiic_tx_space(i2c
) && xiic_tx_fifo_space(i2c
) >= 2) {
445 dev_dbg(i2c
->adap
.dev
.parent
,
446 "%s end of message sent, nmsgs: %d\n",
447 __func__
, i2c
->nmsgs
);
448 if (i2c
->nmsgs
> 1) {
451 __xiic_start_xfer(i2c
);
453 xiic_irq_dis(i2c
, XIIC_INTR_TX_HALF_MASK
);
455 dev_dbg(i2c
->adap
.dev
.parent
,
456 "%s Got TX IRQ but no more to do...\n",
459 } else if (!xiic_tx_space(i2c
) && (i2c
->nmsgs
== 1))
460 /* current frame is sent and is last,
461 * make sure to disable tx half
463 xiic_irq_dis(i2c
, XIIC_INTR_TX_HALF_MASK
);
465 /* got IRQ which is not acked */
466 dev_err(i2c
->adap
.dev
.parent
, "%s Got unexpected IRQ\n",
471 dev_dbg(i2c
->adap
.dev
.parent
, "%s clr: 0x%x\n", __func__
, clr
);
473 xiic_setreg32(i2c
, XIIC_IISR_OFFSET
, clr
);
476 static int xiic_bus_busy(struct xiic_i2c
*i2c
)
478 u8 sr
= xiic_getreg8(i2c
, XIIC_SR_REG_OFFSET
);
480 return (sr
& XIIC_SR_BUS_BUSY_MASK
) ? -EBUSY
: 0;
483 static int xiic_busy(struct xiic_i2c
*i2c
)
491 /* for instance if previous transfer was terminated due to TX error
492 * it might be that the bus is on it's way to become available
493 * give it at most 3 ms to wake
495 err
= xiic_bus_busy(i2c
);
496 while (err
&& tries
--) {
498 err
= xiic_bus_busy(i2c
);
504 static void xiic_start_recv(struct xiic_i2c
*i2c
)
507 struct i2c_msg
*msg
= i2c
->rx_msg
= i2c
->tx_msg
;
509 /* Clear and enable Rx full interrupt. */
510 xiic_irq_clr_en(i2c
, XIIC_INTR_RX_FULL_MASK
| XIIC_INTR_TX_ERROR_MASK
);
512 /* we want to get all but last byte, because the TX_ERROR IRQ is used
513 * to inidicate error ACK on the address, and negative ack on the last
514 * received byte, so to not mix them receive all but last.
515 * In the case where there is only one byte to receive
516 * we can check if ERROR and RX full is set at the same time
518 rx_watermark
= msg
->len
;
519 if (rx_watermark
> IIC_RX_FIFO_DEPTH
)
520 rx_watermark
= IIC_RX_FIFO_DEPTH
;
521 xiic_setreg8(i2c
, XIIC_RFD_REG_OFFSET
, rx_watermark
- 1);
523 if (!(msg
->flags
& I2C_M_NOSTART
))
524 /* write the address */
525 xiic_setreg16(i2c
, XIIC_DTR_REG_OFFSET
,
526 (msg
->addr
<< 1) | XIIC_READ_OPERATION
|
527 XIIC_TX_DYN_START_MASK
);
529 xiic_irq_clr_en(i2c
, XIIC_INTR_BNB_MASK
);
531 xiic_setreg16(i2c
, XIIC_DTR_REG_OFFSET
,
532 msg
->len
| ((i2c
->nmsgs
== 1) ? XIIC_TX_DYN_STOP_MASK
: 0));
534 /* very last, enable bus not busy as well */
535 xiic_irq_clr_en(i2c
, XIIC_INTR_BNB_MASK
);
537 /* the message is tx:ed */
538 i2c
->tx_pos
= msg
->len
;
541 static void xiic_start_send(struct xiic_i2c
*i2c
)
543 struct i2c_msg
*msg
= i2c
->tx_msg
;
545 xiic_irq_clr(i2c
, XIIC_INTR_TX_ERROR_MASK
);
547 dev_dbg(i2c
->adap
.dev
.parent
, "%s entry, msg: %p, len: %d, "
548 "ISR: 0x%x, CR: 0x%x\n",
549 __func__
, msg
, msg
->len
, xiic_getreg32(i2c
, XIIC_IISR_OFFSET
),
550 xiic_getreg8(i2c
, XIIC_CR_REG_OFFSET
));
552 if (!(msg
->flags
& I2C_M_NOSTART
)) {
553 /* write the address */
554 u16 data
= ((msg
->addr
<< 1) & 0xfe) | XIIC_WRITE_OPERATION
|
555 XIIC_TX_DYN_START_MASK
;
556 if ((i2c
->nmsgs
== 1) && msg
->len
== 0)
557 /* no data and last message -> add STOP */
558 data
|= XIIC_TX_DYN_STOP_MASK
;
560 xiic_setreg16(i2c
, XIIC_DTR_REG_OFFSET
, data
);
563 xiic_fill_tx_fifo(i2c
);
565 /* Clear any pending Tx empty, Tx Error and then enable them. */
566 xiic_irq_clr_en(i2c
, XIIC_INTR_TX_EMPTY_MASK
| XIIC_INTR_TX_ERROR_MASK
|
570 static irqreturn_t
xiic_isr(int irq
, void *dev_id
)
572 struct xiic_i2c
*i2c
= dev_id
;
574 spin_lock(&i2c
->lock
);
575 /* disable interrupts globally */
576 xiic_setreg32(i2c
, XIIC_DGIER_OFFSET
, 0);
578 dev_dbg(i2c
->adap
.dev
.parent
, "%s entry\n", __func__
);
582 xiic_setreg32(i2c
, XIIC_DGIER_OFFSET
, XIIC_GINTR_ENABLE_MASK
);
583 spin_unlock(&i2c
->lock
);
588 static void __xiic_start_xfer(struct xiic_i2c
*i2c
)
591 int fifo_space
= xiic_tx_fifo_space(i2c
);
592 dev_dbg(i2c
->adap
.dev
.parent
, "%s entry, msg: %p, fifos space: %d\n",
593 __func__
, i2c
->tx_msg
, fifo_space
);
600 i2c
->state
= STATE_START
;
601 while ((fifo_space
>= 2) && (first
|| (i2c
->nmsgs
> 1))) {
609 if (i2c
->tx_msg
->flags
& I2C_M_RD
) {
610 /* we dont date putting several reads in the FIFO */
611 xiic_start_recv(i2c
);
614 xiic_start_send(i2c
);
615 if (xiic_tx_space(i2c
) != 0) {
616 /* the message could not be completely sent */
621 fifo_space
= xiic_tx_fifo_space(i2c
);
624 /* there are more messages or the current one could not be completely
625 * put into the FIFO, also enable the half empty interrupt
627 if (i2c
->nmsgs
> 1 || xiic_tx_space(i2c
))
628 xiic_irq_clr_en(i2c
, XIIC_INTR_TX_HALF_MASK
);
632 static void xiic_start_xfer(struct xiic_i2c
*i2c
)
636 spin_lock_irqsave(&i2c
->lock
, flags
);
638 /* disable interrupts globally */
639 xiic_setreg32(i2c
, XIIC_DGIER_OFFSET
, 0);
640 spin_unlock_irqrestore(&i2c
->lock
, flags
);
642 __xiic_start_xfer(i2c
);
643 xiic_setreg32(i2c
, XIIC_DGIER_OFFSET
, XIIC_GINTR_ENABLE_MASK
);
646 static int xiic_xfer(struct i2c_adapter
*adap
, struct i2c_msg
*msgs
, int num
)
648 struct xiic_i2c
*i2c
= i2c_get_adapdata(adap
);
651 dev_dbg(adap
->dev
.parent
, "%s entry SR: 0x%x\n", __func__
,
652 xiic_getreg8(i2c
, XIIC_SR_REG_OFFSET
));
654 err
= xiic_busy(i2c
);
661 xiic_start_xfer(i2c
);
663 if (wait_event_timeout(i2c
->wait
, (i2c
->state
== STATE_ERROR
) ||
664 (i2c
->state
== STATE_DONE
), HZ
))
665 return (i2c
->state
== STATE_DONE
) ? num
: -EIO
;
674 static u32
xiic_func(struct i2c_adapter
*adap
)
676 return I2C_FUNC_I2C
| I2C_FUNC_SMBUS_EMUL
;
679 static const struct i2c_algorithm xiic_algorithm
= {
680 .master_xfer
= xiic_xfer
,
681 .functionality
= xiic_func
,
684 static struct i2c_adapter xiic_adapter
= {
685 .owner
= THIS_MODULE
,
687 .class = I2C_CLASS_HWMON
| I2C_CLASS_SPD
,
688 .algo
= &xiic_algorithm
,
692 static int __devinit
xiic_i2c_probe(struct platform_device
*pdev
)
694 struct xiic_i2c
*i2c
;
695 struct xiic_i2c_platform_data
*pdata
;
696 struct resource
*res
;
700 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
702 goto resource_missing
;
704 irq
= platform_get_irq(pdev
, 0);
706 goto resource_missing
;
708 pdata
= mfd_get_data(pdev
);
712 i2c
= kzalloc(sizeof(*i2c
), GFP_KERNEL
);
716 if (!request_mem_region(res
->start
, resource_size(res
), pdev
->name
)) {
717 dev_err(&pdev
->dev
, "Memory region busy\n");
719 goto request_mem_failed
;
722 i2c
->base
= ioremap(res
->start
, resource_size(res
));
724 dev_err(&pdev
->dev
, "Unable to map registers\n");
729 /* hook up driver to tree */
730 platform_set_drvdata(pdev
, i2c
);
731 i2c
->adap
= xiic_adapter
;
732 i2c_set_adapdata(&i2c
->adap
, i2c
);
733 i2c
->adap
.dev
.parent
= &pdev
->dev
;
737 spin_lock_init(&i2c
->lock
);
738 init_waitqueue_head(&i2c
->wait
);
739 ret
= request_irq(irq
, xiic_isr
, 0, pdev
->name
, i2c
);
741 dev_err(&pdev
->dev
, "Cannot claim IRQ\n");
742 goto request_irq_failed
;
745 /* add i2c adapter to i2c tree */
746 ret
= i2c_add_adapter(&i2c
->adap
);
748 dev_err(&pdev
->dev
, "Failed to add adapter\n");
749 goto add_adapter_failed
;
752 /* add in known devices to the bus */
753 for (i
= 0; i
< pdata
->num_devices
; i
++)
754 i2c_new_device(&i2c
->adap
, pdata
->devices
+ i
);
764 release_mem_region(res
->start
, resource_size(res
));
770 dev_err(&pdev
->dev
, "IRQ or Memory resource is missing\n");
774 static int __devexit
xiic_i2c_remove(struct platform_device
* pdev
)
776 struct xiic_i2c
*i2c
= platform_get_drvdata(pdev
);
777 struct resource
*res
;
779 /* remove adapter & data */
780 i2c_del_adapter(&i2c
->adap
);
784 platform_set_drvdata(pdev
, NULL
);
786 free_irq(platform_get_irq(pdev
, 0), i2c
);
790 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
792 release_mem_region(res
->start
, resource_size(res
));
800 /* work with hotplug and coldplug */
801 MODULE_ALIAS("platform:"DRIVER_NAME
);
803 static struct platform_driver xiic_i2c_driver
= {
804 .probe
= xiic_i2c_probe
,
805 .remove
= __devexit_p(xiic_i2c_remove
),
807 .owner
= THIS_MODULE
,
812 static int __init
xiic_i2c_init(void)
814 return platform_driver_register(&xiic_i2c_driver
);
817 static void __exit
xiic_i2c_exit(void)
819 platform_driver_unregister(&xiic_i2c_driver
);
822 module_init(xiic_i2c_init
);
823 module_exit(xiic_i2c_exit
);
825 MODULE_AUTHOR("info@mocean-labs.com");
826 MODULE_DESCRIPTION("Xilinx I2C bus driver");
827 MODULE_LICENSE("GPL v2");