drivers/i2c/busses/i2c-xlp9xx.c

   1 /*
   2  * Copyright (c) 2003-2015 Broadcom Corporation
   3  *
   4  * This file is licensed under the terms of the GNU General Public
   5  * License version 2. This program is licensed "as is" without any
   6  * warranty of any kind, whether express or implied.
   7  */
   8
   9 #include <linux/acpi.h>
  10 #include <linux/clk.h>
  11 #include <linux/completion.h>
  12 #include <linux/i2c.h>
  13 #include <linux/init.h>
  14 #include <linux/interrupt.h>
  15 #include <linux/io.h>
  16 #include <linux/kernel.h>
  17 #include <linux/module.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/delay.h>
  20
  21 #define XLP9XX_I2C_DIV                  0x0
  22 #define XLP9XX_I2C_CTRL                 0x1
  23 #define XLP9XX_I2C_CMD                  0x2
  24 #define XLP9XX_I2C_STATUS               0x3
  25 #define XLP9XX_I2C_MTXFIFO              0x4
  26 #define XLP9XX_I2C_MRXFIFO              0x5
  27 #define XLP9XX_I2C_MFIFOCTRL            0x6
  28 #define XLP9XX_I2C_STXFIFO              0x7
  29 #define XLP9XX_I2C_SRXFIFO              0x8
  30 #define XLP9XX_I2C_SFIFOCTRL            0x9
  31 #define XLP9XX_I2C_SLAVEADDR            0xA
  32 #define XLP9XX_I2C_OWNADDR              0xB
  33 #define XLP9XX_I2C_FIFOWCNT             0xC
  34 #define XLP9XX_I2C_INTEN                0xD
  35 #define XLP9XX_I2C_INTST                0xE
  36 #define XLP9XX_I2C_WAITCNT              0xF
  37 #define XLP9XX_I2C_TIMEOUT              0X10
  38 #define XLP9XX_I2C_GENCALLADDR          0x11
  39
  40 #define XLP9XX_I2C_STATUS_BUSY          BIT(0)
  41
  42 #define XLP9XX_I2C_CMD_START            BIT(7)
  43 #define XLP9XX_I2C_CMD_STOP             BIT(6)
  44 #define XLP9XX_I2C_CMD_READ             BIT(5)
  45 #define XLP9XX_I2C_CMD_WRITE            BIT(4)
  46 #define XLP9XX_I2C_CMD_ACK              BIT(3)
  47
  48 #define XLP9XX_I2C_CTRL_MCTLEN_SHIFT    16
  49 #define XLP9XX_I2C_CTRL_MCTLEN_MASK     0xffff0000
  50 #define XLP9XX_I2C_CTRL_RST             BIT(8)
  51 #define XLP9XX_I2C_CTRL_EN              BIT(6)
  52 #define XLP9XX_I2C_CTRL_MASTER          BIT(4)
  53 #define XLP9XX_I2C_CTRL_FIFORD          BIT(1)
  54 #define XLP9XX_I2C_CTRL_ADDMODE         BIT(0)
  55
  56 #define XLP9XX_I2C_INTEN_NACKADDR       BIT(25)
  57 #define XLP9XX_I2C_INTEN_SADDR          BIT(13)
  58 #define XLP9XX_I2C_INTEN_DATADONE       BIT(12)
  59 #define XLP9XX_I2C_INTEN_ARLOST         BIT(11)
  60 #define XLP9XX_I2C_INTEN_MFIFOFULL      BIT(4)
  61 #define XLP9XX_I2C_INTEN_MFIFOEMTY      BIT(3)
  62 #define XLP9XX_I2C_INTEN_MFIFOHI        BIT(2)
  63 #define XLP9XX_I2C_INTEN_BUSERR         BIT(0)
  64
  65 #define XLP9XX_I2C_MFIFOCTRL_HITH_SHIFT         8
  66 #define XLP9XX_I2C_MFIFOCTRL_LOTH_SHIFT         0
  67 #define XLP9XX_I2C_MFIFOCTRL_RST                BIT(16)
  68
  69 #define XLP9XX_I2C_SLAVEADDR_RW                 BIT(0)
  70 #define XLP9XX_I2C_SLAVEADDR_ADDR_SHIFT         1
  71
  72 #define XLP9XX_I2C_IP_CLK_FREQ          133000000UL
  73 #define XLP9XX_I2C_DEFAULT_FREQ         100000
  74 #define XLP9XX_I2C_HIGH_FREQ            400000
  75 #define XLP9XX_I2C_FIFO_SIZE            0x80U
  76 #define XLP9XX_I2C_TIMEOUT_MS           1000
  77 #define XLP9XX_I2C_BUSY_TIMEOUT         50
  78
  79 #define XLP9XX_I2C_FIFO_WCNT_MASK       0xff
  80 #define XLP9XX_I2C_STATUS_ERRMASK       (XLP9XX_I2C_INTEN_ARLOST | \
  81                         XLP9XX_I2C_INTEN_NACKADDR | XLP9XX_I2C_INTEN_BUSERR)
  82
  83 struct xlp9xx_i2c_dev {
  84         struct device *dev;
  85         struct i2c_adapter adapter;
  86         struct completion msg_complete;
  87         int irq;
  88         bool msg_read;
  89         bool len_recv;
  90         bool client_pec;
  91         u32 __iomem *base;
  92         u32 msg_buf_remaining;
  93         u32 msg_len;
  94         u32 ip_clk_hz;
  95         u32 clk_hz;
  96         u32 msg_err;
  97         u8 *msg_buf;
  98 };
  99
 100 static inline void xlp9xx_write_i2c_reg(struct xlp9xx_i2c_dev *priv,
 101                                         unsigned long reg, u32 val)
 102 {
 103         writel(val, priv->base + reg);
 104 }
 105
 106 static inline u32 xlp9xx_read_i2c_reg(struct xlp9xx_i2c_dev *priv,
 107                                       unsigned long reg)
 108 {
 109         return readl(priv->base + reg);
 110 }
 111
 112 static void xlp9xx_i2c_mask_irq(struct xlp9xx_i2c_dev *priv, u32 mask)
 113 {
 114         u32 inten;
 115
 116         inten = xlp9xx_read_i2c_reg(priv, XLP9XX_I2C_INTEN) & ~mask;
 117         xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_INTEN, inten);
 118 }
 119
 120 static void xlp9xx_i2c_unmask_irq(struct xlp9xx_i2c_dev *priv, u32 mask)
 121 {
 122         u32 inten;
 123
 124         inten = xlp9xx_read_i2c_reg(priv, XLP9XX_I2C_INTEN) | mask;
 125         xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_INTEN, inten);
 126 }
 127
 128 static void xlp9xx_i2c_update_rx_fifo_thres(struct xlp9xx_i2c_dev *priv)
 129 {
 130         u32 thres;
 131
 132         if (priv->len_recv)
 133                 /* interrupt after the first read to examine
 134                  * the length byte before proceeding further
 135                  */
 136                 thres = 1;
 137         else if (priv->msg_buf_remaining > XLP9XX_I2C_FIFO_SIZE)
 138                 thres = XLP9XX_I2C_FIFO_SIZE;
 139         else
 140                 thres = priv->msg_buf_remaining;
 141
 142         xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_MFIFOCTRL,
 143                              thres << XLP9XX_I2C_MFIFOCTRL_HITH_SHIFT);
 144 }
 145
 146 static void xlp9xx_i2c_fill_tx_fifo(struct xlp9xx_i2c_dev *priv)
 147 {
 148         u32 len, i;
 149         u8 *buf = priv->msg_buf;
 150
 151         len = min(priv->msg_buf_remaining, XLP9XX_I2C_FIFO_SIZE);
 152         for (i = 0; i < len; i++)
 153                 xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_MTXFIFO, buf[i]);
 154         priv->msg_buf_remaining -= len;
 155         priv->msg_buf += len;
 156 }
 157
 158 static void xlp9xx_i2c_update_rlen(struct xlp9xx_i2c_dev *priv)
 159 {
 160         u32 val, len;
 161
 162         /*
 163          * Update receive length. Re-read len to get the latest value,
 164          * and then add 4 to have a minimum value that can be safely
 165          * written. This is to account for the byte read above, the
 166          * transfer in progress and any delays in the register I/O
 167          */
 168         val = xlp9xx_read_i2c_reg(priv, XLP9XX_I2C_CTRL);
 169         len = xlp9xx_read_i2c_reg(priv, XLP9XX_I2C_FIFOWCNT) &
 170                                   XLP9XX_I2C_FIFO_WCNT_MASK;
 171         len = max_t(u32, priv->msg_len, len + 4);
 172         val = (val & ~XLP9XX_I2C_CTRL_MCTLEN_MASK) |
 173                         (len << XLP9XX_I2C_CTRL_MCTLEN_SHIFT);
 174         xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_CTRL, val);
 175 }
 176
 177 static void xlp9xx_i2c_drain_rx_fifo(struct xlp9xx_i2c_dev *priv)
 178 {
 179         u32 len, i;
 180         u8 rlen, *buf = priv->msg_buf;
 181
 182         len = xlp9xx_read_i2c_reg(priv, XLP9XX_I2C_FIFOWCNT) &
 183                                   XLP9XX_I2C_FIFO_WCNT_MASK;
 184         if (!len)
 185                 return;
 186         if (priv->len_recv) {
 187                 /* read length byte */
 188                 rlen = xlp9xx_read_i2c_reg(priv, XLP9XX_I2C_MRXFIFO);
 189                 *buf++ = rlen;
 190                 if (priv->client_pec)
 191                         ++rlen;
 192                 /* update remaining bytes and message length */
 193                 priv->msg_buf_remaining = rlen;
 194                 priv->msg_len = rlen + 1;
 195                 priv->len_recv = false;
 196                 xlp9xx_i2c_update_rlen(priv);
 197         } else {
 198                 len = min(priv->msg_buf_remaining, len);
 199                 for (i = 0; i < len; i++, buf++)
 200                         *buf = xlp9xx_read_i2c_reg(priv, XLP9XX_I2C_MRXFIFO);
 201
 202                 priv->msg_buf_remaining -= len;
 203         }
 204
 205         priv->msg_buf = buf;
 206
 207         if (priv->msg_buf_remaining)
 208                 xlp9xx_i2c_update_rx_fifo_thres(priv);
 209 }
 210
 211 static irqreturn_t xlp9xx_i2c_isr(int irq, void *dev_id)
 212 {
 213         struct xlp9xx_i2c_dev *priv = dev_id;
 214         u32 status;
 215
 216         status = xlp9xx_read_i2c_reg(priv, XLP9XX_I2C_INTST);
 217         if (status == 0)
 218                 return IRQ_NONE;
 219
 220         xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_INTST, status);
 221         if (status & XLP9XX_I2C_STATUS_ERRMASK) {
 222                 priv->msg_err = status;
 223                 goto xfer_done;
 224         }
 225
 226         /* SADDR ACK for SMBUS_QUICK */
 227         if ((status & XLP9XX_I2C_INTEN_SADDR) && (priv->msg_len == 0))
 228                 goto xfer_done;
 229
 230         if (!priv->msg_read) {
 231                 if (status & XLP9XX_I2C_INTEN_MFIFOEMTY) {
 232                         /* TX FIFO got empty, fill it up again */
 233                         if (priv->msg_buf_remaining)
 234                                 xlp9xx_i2c_fill_tx_fifo(priv);
 235                         else
 236                                 xlp9xx_i2c_mask_irq(priv,
 237                                                     XLP9XX_I2C_INTEN_MFIFOEMTY);
 238                 }
 239         } else {
 240                 if (status & (XLP9XX_I2C_INTEN_DATADONE |
 241                               XLP9XX_I2C_INTEN_MFIFOHI)) {
 242                         /* data is in FIFO, read it */
 243                         if (priv->msg_buf_remaining)
 244                                 xlp9xx_i2c_drain_rx_fifo(priv);
 245                 }
 246         }
 247
 248         /* Transfer complete */
 249         if (status & XLP9XX_I2C_INTEN_DATADONE)
 250                 goto xfer_done;
 251
 252         return IRQ_HANDLED;
 253
 254 xfer_done:
 255         xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_INTEN, 0);
 256         complete(&priv->msg_complete);
 257         return IRQ_HANDLED;
 258 }
 259
 260 static int xlp9xx_i2c_check_bus_status(struct xlp9xx_i2c_dev *priv)
 261 {
 262         u32 status;
 263         u32 busy_timeout = XLP9XX_I2C_BUSY_TIMEOUT;
 264
 265         while (busy_timeout) {
 266                 status = xlp9xx_read_i2c_reg(priv, XLP9XX_I2C_STATUS);
 267                 if ((status & XLP9XX_I2C_STATUS_BUSY) == 0)
 268                         break;
 269
 270                 busy_timeout--;
 271                 usleep_range(1000, 1100);
 272         }
 273
 274         if (!busy_timeout)
 275                 return -EIO;
 276
 277         return 0;
 278 }
 279
 280 static int xlp9xx_i2c_init(struct xlp9xx_i2c_dev *priv)
 281 {
 282         u32 prescale;
 283
 284         /*
 285          * The controller uses 5 * SCL clock internally.
 286          * So prescale value should be divided by 5.
 287          */
 288         prescale = DIV_ROUND_UP(priv->ip_clk_hz, priv->clk_hz);
 289         prescale = ((prescale - 8) / 5) - 1;
 290         xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_CTRL, XLP9XX_I2C_CTRL_RST);
 291         xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_CTRL, XLP9XX_I2C_CTRL_EN |
 292                              XLP9XX_I2C_CTRL_MASTER);
 293         xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_DIV, prescale);
 294         xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_INTEN, 0);
 295
 296         return 0;
 297 }
 298
 299 static int xlp9xx_i2c_xfer_msg(struct xlp9xx_i2c_dev *priv, struct i2c_msg *msg,
 300                                int last_msg)
 301 {
 302         unsigned long timeleft;
 303         u32 intr_mask, cmd, val, len;
 304
 305         priv->msg_buf = msg->buf;
 306         priv->msg_buf_remaining = priv->msg_len = msg->len;
 307         priv->msg_err = 0;
 308         priv->msg_read = (msg->flags & I2C_M_RD);
 309         reinit_completion(&priv->msg_complete);
 310
 311         /* Reset FIFO */
 312         xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_MFIFOCTRL,
 313                              XLP9XX_I2C_MFIFOCTRL_RST);
 314
 315         /* set FIFO threshold if reading */
 316         if (priv->msg_read)
 317                 xlp9xx_i2c_update_rx_fifo_thres(priv);
 318
 319         /* set slave addr */
 320         xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_SLAVEADDR,
 321                              (msg->addr << XLP9XX_I2C_SLAVEADDR_ADDR_SHIFT) |
 322                              (priv->msg_read ? XLP9XX_I2C_SLAVEADDR_RW : 0));
 323
 324         /* Build control word for transfer */
 325         val = xlp9xx_read_i2c_reg(priv, XLP9XX_I2C_CTRL);
 326         if (!priv->msg_read)
 327                 val &= ~XLP9XX_I2C_CTRL_FIFORD;
 328         else
 329                 val |= XLP9XX_I2C_CTRL_FIFORD;  /* read */
 330
 331         if (msg->flags & I2C_M_TEN)
 332                 val |= XLP9XX_I2C_CTRL_ADDMODE; /* 10-bit address mode*/
 333         else
 334                 val &= ~XLP9XX_I2C_CTRL_ADDMODE;
 335
 336         priv->len_recv = msg->flags & I2C_M_RECV_LEN;
 337         len = priv->len_recv ? XLP9XX_I2C_FIFO_SIZE : msg->len;
 338         priv->client_pec = msg->flags & I2C_CLIENT_PEC;
 339
 340         /* set data length to be transferred */
 341         val = (val & ~XLP9XX_I2C_CTRL_MCTLEN_MASK) |
 342               (len << XLP9XX_I2C_CTRL_MCTLEN_SHIFT);
 343         xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_CTRL, val);
 344
 345         /* fill fifo during tx */
 346         if (!priv->msg_read)
 347                 xlp9xx_i2c_fill_tx_fifo(priv);
 348
 349         /* set interrupt mask */
 350         intr_mask = (XLP9XX_I2C_INTEN_ARLOST | XLP9XX_I2C_INTEN_BUSERR |
 351                      XLP9XX_I2C_INTEN_NACKADDR | XLP9XX_I2C_INTEN_DATADONE);
 352
 353         if (priv->msg_read) {
 354                 intr_mask |= XLP9XX_I2C_INTEN_MFIFOHI;
 355                 if (msg->len == 0)
 356                         intr_mask |= XLP9XX_I2C_INTEN_SADDR;
 357         } else {
 358                 if (msg->len == 0)
 359                         intr_mask |= XLP9XX_I2C_INTEN_SADDR;
 360                 else
 361                         intr_mask |= XLP9XX_I2C_INTEN_MFIFOEMTY;
 362         }
 363         xlp9xx_i2c_unmask_irq(priv, intr_mask);
 364
 365         /* set cmd reg */
 366         cmd = XLP9XX_I2C_CMD_START;
 367         if (msg->len)
 368                 cmd |= (priv->msg_read ?
 369                         XLP9XX_I2C_CMD_READ : XLP9XX_I2C_CMD_WRITE);
 370         if (last_msg)
 371                 cmd |= XLP9XX_I2C_CMD_STOP;
 372
 373         xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_CMD, cmd);
 374
 375         timeleft = msecs_to_jiffies(XLP9XX_I2C_TIMEOUT_MS);
 376         timeleft = wait_for_completion_timeout(&priv->msg_complete, timeleft);
 377
 378         if (priv->msg_err & XLP9XX_I2C_INTEN_BUSERR) {
 379                 dev_dbg(priv->dev, "transfer error %x!\n", priv->msg_err);
 380                 xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_CMD, XLP9XX_I2C_CMD_STOP);
 381                 return -EIO;
 382         } else if (priv->msg_err & XLP9XX_I2C_INTEN_NACKADDR) {
 383                 return -ENXIO;
 384         }
 385
 386         if (timeleft == 0) {
 387                 dev_dbg(priv->dev, "i2c transfer timed out!\n");
 388                 xlp9xx_i2c_init(priv);
 389                 return -ETIMEDOUT;
 390         }
 391
 392         /* update msg->len with actual received length */
 393         if (msg->flags & I2C_M_RECV_LEN)
 394                 msg->len = priv->msg_len;
 395         return 0;
 396 }
 397
 398 static int xlp9xx_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs,
 399                            int num)
 400 {
 401         int i, ret;
 402         struct xlp9xx_i2c_dev *priv = i2c_get_adapdata(adap);
 403
 404         ret = xlp9xx_i2c_check_bus_status(priv);
 405         if (ret) {
 406                 xlp9xx_i2c_init(priv);
 407                 ret = xlp9xx_i2c_check_bus_status(priv);
 408                 if (ret)
 409                         return ret;
 410         }
 411
 412         for (i = 0; i < num; i++) {
 413                 ret = xlp9xx_i2c_xfer_msg(priv, &msgs[i], i == num - 1);
 414                 if (ret != 0)
 415                         return ret;
 416         }
 417
 418         return num;
 419 }
 420
 421 static u32 xlp9xx_i2c_functionality(struct i2c_adapter *adapter)
 422 {
 423         return I2C_FUNC_SMBUS_EMUL | I2C_FUNC_SMBUS_READ_BLOCK_DATA |
 424                         I2C_FUNC_I2C | I2C_FUNC_10BIT_ADDR;
 425 }
 426
 427 static const struct i2c_algorithm xlp9xx_i2c_algo = {
 428         .master_xfer = xlp9xx_i2c_xfer,
 429         .functionality = xlp9xx_i2c_functionality,
 430 };
 431
 432 static int xlp9xx_i2c_get_frequency(struct platform_device *pdev,
 433                                     struct xlp9xx_i2c_dev *priv)
 434 {
 435         struct clk *clk;
 436         u32 freq;
 437         int err;
 438
 439         clk = devm_clk_get(&pdev->dev, NULL);
 440         if (IS_ERR(clk)) {
 441                 priv->ip_clk_hz = XLP9XX_I2C_IP_CLK_FREQ;
 442                 dev_dbg(&pdev->dev, "using default input frequency %u\n",
 443                         priv->ip_clk_hz);
 444         } else {
 445                 priv->ip_clk_hz = clk_get_rate(clk);
 446         }
 447
 448         err = device_property_read_u32(&pdev->dev, "clock-frequency", &freq);
 449         if (err) {
 450                 freq = XLP9XX_I2C_DEFAULT_FREQ;
 451                 dev_dbg(&pdev->dev, "using default frequency %u\n", freq);
 452         } else if (freq == 0 || freq > XLP9XX_I2C_HIGH_FREQ) {
 453                 dev_warn(&pdev->dev, "invalid frequency %u, using default\n",
 454                          freq);
 455                 freq = XLP9XX_I2C_DEFAULT_FREQ;
 456         }
 457         priv->clk_hz = freq;
 458
 459         return 0;
 460 }
 461
 462 static int xlp9xx_i2c_probe(struct platform_device *pdev)
 463 {
 464         struct xlp9xx_i2c_dev *priv;
 465         struct resource *res;
 466         int err = 0;
 467
 468         priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
 469         if (!priv)
 470                 return -ENOMEM;
 471
 472         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 473         priv->base = devm_ioremap_resource(&pdev->dev, res);
 474         if (IS_ERR(priv->base))
 475                 return PTR_ERR(priv->base);
 476
 477         priv->irq = platform_get_irq(pdev, 0);
 478         if (priv->irq <= 0) {
 479                 dev_err(&pdev->dev, "invalid irq!\n");
 480                 return priv->irq;
 481         }
 482
 483         xlp9xx_i2c_get_frequency(pdev, priv);
 484         xlp9xx_i2c_init(priv);
 485
 486         err = devm_request_irq(&pdev->dev, priv->irq, xlp9xx_i2c_isr, 0,
 487                                pdev->name, priv);
 488         if (err) {
 489                 dev_err(&pdev->dev, "IRQ request failed!\n");
 490                 return err;
 491         }
 492
 493         init_completion(&priv->msg_complete);
 494         priv->adapter.dev.parent = &pdev->dev;
 495         priv->adapter.algo = &xlp9xx_i2c_algo;
 496         priv->adapter.class = I2C_CLASS_HWMON;
 497         ACPI_COMPANION_SET(&priv->adapter.dev, ACPI_COMPANION(&pdev->dev));
 498         priv->adapter.dev.of_node = pdev->dev.of_node;
 499         priv->dev = &pdev->dev;
 500
 501         snprintf(priv->adapter.name, sizeof(priv->adapter.name), "xlp9xx-i2c");
 502         i2c_set_adapdata(&priv->adapter, priv);
 503
 504         err = i2c_add_adapter(&priv->adapter);
 505         if (err)
 506                 return err;
 507
 508         platform_set_drvdata(pdev, priv);
 509         dev_dbg(&pdev->dev, "I2C bus:%d added\n", priv->adapter.nr);
 510
 511         return 0;
 512 }
 513
 514 static int xlp9xx_i2c_remove(struct platform_device *pdev)
 515 {
 516         struct xlp9xx_i2c_dev *priv;
 517
 518         priv = platform_get_drvdata(pdev);
 519         xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_INTEN, 0);
 520         synchronize_irq(priv->irq);
 521         i2c_del_adapter(&priv->adapter);
 522         xlp9xx_write_i2c_reg(priv, XLP9XX_I2C_CTRL, 0);
 523
 524         return 0;
 525 }
 526
 527 static const struct of_device_id xlp9xx_i2c_of_match[] = {
 528         { .compatible = "netlogic,xlp980-i2c", },
 529         { /* sentinel */ },
 530 };
 531 MODULE_DEVICE_TABLE(of, xlp9xx_i2c_of_match);
 532
 533 #ifdef CONFIG_ACPI
 534 static const struct acpi_device_id xlp9xx_i2c_acpi_ids[] = {
 535         {"BRCM9007", 0},
 536         {"CAV9007",  0},
 537         {}
 538 };
 539 MODULE_DEVICE_TABLE(acpi, xlp9xx_i2c_acpi_ids);
 540 #endif
 541
 542 static struct platform_driver xlp9xx_i2c_driver = {
 543         .probe = xlp9xx_i2c_probe,
 544         .remove = xlp9xx_i2c_remove,
 545         .driver = {
 546                 .name = "xlp9xx-i2c",
 547                 .of_match_table = xlp9xx_i2c_of_match,
 548                 .acpi_match_table = ACPI_PTR(xlp9xx_i2c_acpi_ids),
 549         },
 550 };
 551
 552 module_platform_driver(xlp9xx_i2c_driver);
 553
 554 MODULE_AUTHOR("Subhendu Sekhar Behera <sbehera@broadcom.com>");
 555 MODULE_DESCRIPTION("XLP9XX/5XX I2C Bus Controller Driver");
 556 MODULE_LICENSE("GPL v2");