2 * linux/drivers/ide/arm/icside.c
4 * Copyright (c) 1996-2004 Russell King.
6 * Please note that this platform does not support 32-bit IDE IO.
9 #include <linux/string.h>
10 #include <linux/module.h>
11 #include <linux/ioport.h>
12 #include <linux/slab.h>
13 #include <linux/blkdev.h>
14 #include <linux/errno.h>
15 #include <linux/hdreg.h>
16 #include <linux/ide.h>
17 #include <linux/dma-mapping.h>
18 #include <linux/device.h>
19 #include <linux/init.h>
20 #include <linux/scatterlist.h>
23 #include <asm/ecard.h>
26 #define ICS_IDENT_OFFSET 0x2280
28 #define ICS_ARCIN_V5_INTRSTAT 0x0000
29 #define ICS_ARCIN_V5_INTROFFSET 0x0004
30 #define ICS_ARCIN_V5_IDEOFFSET 0x2800
31 #define ICS_ARCIN_V5_IDEALTOFFSET 0x2b80
32 #define ICS_ARCIN_V5_IDESTEPPING 6
34 #define ICS_ARCIN_V6_IDEOFFSET_1 0x2000
35 #define ICS_ARCIN_V6_INTROFFSET_1 0x2200
36 #define ICS_ARCIN_V6_INTRSTAT_1 0x2290
37 #define ICS_ARCIN_V6_IDEALTOFFSET_1 0x2380
38 #define ICS_ARCIN_V6_IDEOFFSET_2 0x3000
39 #define ICS_ARCIN_V6_INTROFFSET_2 0x3200
40 #define ICS_ARCIN_V6_INTRSTAT_2 0x3290
41 #define ICS_ARCIN_V6_IDEALTOFFSET_2 0x3380
42 #define ICS_ARCIN_V6_IDESTEPPING 6
45 unsigned int dataoffset
;
46 unsigned int ctrloffset
;
47 unsigned int stepping
;
50 static struct cardinfo icside_cardinfo_v5
= {
51 .dataoffset
= ICS_ARCIN_V5_IDEOFFSET
,
52 .ctrloffset
= ICS_ARCIN_V5_IDEALTOFFSET
,
53 .stepping
= ICS_ARCIN_V5_IDESTEPPING
,
56 static struct cardinfo icside_cardinfo_v6_1
= {
57 .dataoffset
= ICS_ARCIN_V6_IDEOFFSET_1
,
58 .ctrloffset
= ICS_ARCIN_V6_IDEALTOFFSET_1
,
59 .stepping
= ICS_ARCIN_V6_IDESTEPPING
,
62 static struct cardinfo icside_cardinfo_v6_2
= {
63 .dataoffset
= ICS_ARCIN_V6_IDEOFFSET_2
,
64 .ctrloffset
= ICS_ARCIN_V6_IDEALTOFFSET_2
,
65 .stepping
= ICS_ARCIN_V6_IDESTEPPING
,
71 void __iomem
*irq_port
;
72 void __iomem
*ioc_base
;
74 /* parent device... until the IDE core gets one of its own */
79 #define ICS_TYPE_A3IN 0
80 #define ICS_TYPE_A3USER 1
82 #define ICS_TYPE_V5 15
83 #define ICS_TYPE_NOTYPE ((unsigned int)-1)
85 /* ---------------- Version 5 PCB Support Functions --------------------- */
86 /* Prototype: icside_irqenable_arcin_v5 (struct expansion_card *ec, int irqnr)
87 * Purpose : enable interrupts from card
89 static void icside_irqenable_arcin_v5 (struct expansion_card
*ec
, int irqnr
)
91 struct icside_state
*state
= ec
->irq_data
;
93 writeb(0, state
->irq_port
+ ICS_ARCIN_V5_INTROFFSET
);
96 /* Prototype: icside_irqdisable_arcin_v5 (struct expansion_card *ec, int irqnr)
97 * Purpose : disable interrupts from card
99 static void icside_irqdisable_arcin_v5 (struct expansion_card
*ec
, int irqnr
)
101 struct icside_state
*state
= ec
->irq_data
;
103 readb(state
->irq_port
+ ICS_ARCIN_V5_INTROFFSET
);
106 static const expansioncard_ops_t icside_ops_arcin_v5
= {
107 .irqenable
= icside_irqenable_arcin_v5
,
108 .irqdisable
= icside_irqdisable_arcin_v5
,
112 /* ---------------- Version 6 PCB Support Functions --------------------- */
113 /* Prototype: icside_irqenable_arcin_v6 (struct expansion_card *ec, int irqnr)
114 * Purpose : enable interrupts from card
116 static void icside_irqenable_arcin_v6 (struct expansion_card
*ec
, int irqnr
)
118 struct icside_state
*state
= ec
->irq_data
;
119 void __iomem
*base
= state
->irq_port
;
123 switch (state
->channel
) {
125 writeb(0, base
+ ICS_ARCIN_V6_INTROFFSET_1
);
126 readb(base
+ ICS_ARCIN_V6_INTROFFSET_2
);
129 writeb(0, base
+ ICS_ARCIN_V6_INTROFFSET_2
);
130 readb(base
+ ICS_ARCIN_V6_INTROFFSET_1
);
135 /* Prototype: icside_irqdisable_arcin_v6 (struct expansion_card *ec, int irqnr)
136 * Purpose : disable interrupts from card
138 static void icside_irqdisable_arcin_v6 (struct expansion_card
*ec
, int irqnr
)
140 struct icside_state
*state
= ec
->irq_data
;
144 readb(state
->irq_port
+ ICS_ARCIN_V6_INTROFFSET_1
);
145 readb(state
->irq_port
+ ICS_ARCIN_V6_INTROFFSET_2
);
148 /* Prototype: icside_irqprobe(struct expansion_card *ec)
149 * Purpose : detect an active interrupt from card
151 static int icside_irqpending_arcin_v6(struct expansion_card
*ec
)
153 struct icside_state
*state
= ec
->irq_data
;
155 return readb(state
->irq_port
+ ICS_ARCIN_V6_INTRSTAT_1
) & 1 ||
156 readb(state
->irq_port
+ ICS_ARCIN_V6_INTRSTAT_2
) & 1;
159 static const expansioncard_ops_t icside_ops_arcin_v6
= {
160 .irqenable
= icside_irqenable_arcin_v6
,
161 .irqdisable
= icside_irqdisable_arcin_v6
,
162 .irqpending
= icside_irqpending_arcin_v6
,
166 * Handle routing of interrupts. This is called before
167 * we write the command to the drive.
169 static void icside_maskproc(ide_drive_t
*drive
, int mask
)
171 ide_hwif_t
*hwif
= HWIF(drive
);
172 struct icside_state
*state
= hwif
->hwif_data
;
175 local_irq_save(flags
);
177 state
->channel
= hwif
->channel
;
179 if (state
->enabled
&& !mask
) {
180 switch (hwif
->channel
) {
182 writeb(0, state
->irq_port
+ ICS_ARCIN_V6_INTROFFSET_1
);
183 readb(state
->irq_port
+ ICS_ARCIN_V6_INTROFFSET_2
);
186 writeb(0, state
->irq_port
+ ICS_ARCIN_V6_INTROFFSET_2
);
187 readb(state
->irq_port
+ ICS_ARCIN_V6_INTROFFSET_1
);
191 readb(state
->irq_port
+ ICS_ARCIN_V6_INTROFFSET_2
);
192 readb(state
->irq_port
+ ICS_ARCIN_V6_INTROFFSET_1
);
195 local_irq_restore(flags
);
198 #ifdef CONFIG_BLK_DEV_IDEDMA_ICS
202 * Similar to the BM-DMA, but we use the RiscPCs IOMD DMA controllers.
203 * There is only one DMA controller per card, which means that only
204 * one drive can be accessed at one time. NOTE! We do not enforce that
205 * here, but we rely on the main IDE driver spotting that both
206 * interfaces use the same IRQ, which should guarantee this.
209 static void icside_build_sglist(ide_drive_t
*drive
, struct request
*rq
)
211 ide_hwif_t
*hwif
= drive
->hwif
;
212 struct icside_state
*state
= hwif
->hwif_data
;
213 struct scatterlist
*sg
= hwif
->sg_table
;
215 ide_map_sg(drive
, rq
);
217 if (rq_data_dir(rq
) == READ
)
218 hwif
->sg_dma_direction
= DMA_FROM_DEVICE
;
220 hwif
->sg_dma_direction
= DMA_TO_DEVICE
;
222 hwif
->sg_nents
= dma_map_sg(state
->dev
, sg
, hwif
->sg_nents
,
223 hwif
->sg_dma_direction
);
227 * Configure the IOMD to give the appropriate timings for the transfer
228 * mode being requested. We take the advice of the ATA standards, and
229 * calculate the cycle time based on the transfer mode, and the EIDE
230 * MW DMA specs that the drive provides in the IDENTIFY command.
232 * We have the following IOMD DMA modes to choose from:
234 * Type Active Recovery Cycle
235 * A 250 (250) 312 (550) 562 (800)
237 * C 125 (125) 125 (375) 250 (500)
240 * (figures in brackets are actual measured timings)
242 * However, we also need to take care of the read/write active and
246 * Mode Active -- Recovery -- Cycle IOMD type
247 * MW0 215 50 215 480 A
251 static int icside_set_speed(ide_drive_t
*drive
, u8 xfer_mode
)
253 int on
= 0, cycle_time
= 0, use_dma_info
= 0;
256 * Limit the transfer speed to MW_DMA_2.
258 if (xfer_mode
> XFER_MW_DMA_2
)
259 xfer_mode
= XFER_MW_DMA_2
;
284 * If we're going to be doing MW_DMA_1 or MW_DMA_2, we should
285 * take care to note the values in the ID...
287 if (use_dma_info
&& drive
->id
->eide_dma_time
> cycle_time
)
288 cycle_time
= drive
->id
->eide_dma_time
;
290 drive
->drive_data
= cycle_time
;
292 if (cycle_time
&& ide_config_drive_speed(drive
, xfer_mode
) == 0)
295 drive
->drive_data
= 480;
297 printk("%s: %s selected (peak %dMB/s)\n", drive
->name
,
298 ide_xfer_verbose(xfer_mode
), 2000 / drive
->drive_data
);
300 drive
->current_speed
= xfer_mode
;
305 static void icside_dma_host_off(ide_drive_t
*drive
)
309 static void icside_dma_off_quietly(ide_drive_t
*drive
)
311 drive
->using_dma
= 0;
314 static void icside_dma_host_on(ide_drive_t
*drive
)
318 static int icside_dma_on(ide_drive_t
*drive
)
320 drive
->using_dma
= 1;
325 static int icside_dma_check(ide_drive_t
*drive
)
327 struct hd_driveid
*id
= drive
->id
;
328 ide_hwif_t
*hwif
= HWIF(drive
);
329 int xfer_mode
= XFER_PIO_2
;
332 if (!(id
->capability
& 1) || !hwif
->autodma
)
336 * Consult the list of known "bad" drives
338 if (__ide_dma_bad_drive(drive
))
342 * Enable DMA on any drive that has multiword DMA
344 if (id
->field_valid
& 2) {
345 xfer_mode
= ide_max_dma_mode(drive
);
350 * Consult the list of known "good" drives
352 if (__ide_dma_good_drive(drive
)) {
353 if (id
->eide_dma_time
> 150)
355 xfer_mode
= XFER_MW_DMA_1
;
359 on
= icside_set_speed(drive
, xfer_mode
);
364 static int icside_dma_end(ide_drive_t
*drive
)
366 ide_hwif_t
*hwif
= HWIF(drive
);
367 struct icside_state
*state
= hwif
->hwif_data
;
369 drive
->waiting_for_dma
= 0;
371 disable_dma(hwif
->hw
.dma
);
373 /* Teardown mappings after DMA has completed. */
374 dma_unmap_sg(state
->dev
, hwif
->sg_table
, hwif
->sg_nents
,
375 hwif
->sg_dma_direction
);
377 return get_dma_residue(hwif
->hw
.dma
) != 0;
380 static void icside_dma_start(ide_drive_t
*drive
)
382 ide_hwif_t
*hwif
= HWIF(drive
);
384 /* We can not enable DMA on both channels simultaneously. */
385 BUG_ON(dma_channel_active(hwif
->hw
.dma
));
386 enable_dma(hwif
->hw
.dma
);
389 static int icside_dma_setup(ide_drive_t
*drive
)
391 ide_hwif_t
*hwif
= HWIF(drive
);
392 struct request
*rq
= hwif
->hwgroup
->rq
;
393 unsigned int dma_mode
;
396 dma_mode
= DMA_MODE_WRITE
;
398 dma_mode
= DMA_MODE_READ
;
401 * We can not enable DMA on both channels.
403 BUG_ON(dma_channel_active(hwif
->hw
.dma
));
405 icside_build_sglist(drive
, rq
);
408 * Ensure that we have the right interrupt routed.
410 icside_maskproc(drive
, 0);
413 * Route the DMA signals to the correct interface.
415 writeb(hwif
->select_data
, hwif
->config_data
);
418 * Select the correct timing for this drive.
420 set_dma_speed(hwif
->hw
.dma
, drive
->drive_data
);
423 * Tell the DMA engine about the SG table and
426 set_dma_sg(hwif
->hw
.dma
, hwif
->sg_table
, hwif
->sg_nents
);
427 set_dma_mode(hwif
->hw
.dma
, dma_mode
);
429 drive
->waiting_for_dma
= 1;
434 static void icside_dma_exec_cmd(ide_drive_t
*drive
, u8 cmd
)
436 /* issue cmd to drive */
437 ide_execute_command(drive
, cmd
, ide_dma_intr
, 2 * WAIT_CMD
, NULL
);
440 static int icside_dma_test_irq(ide_drive_t
*drive
)
442 ide_hwif_t
*hwif
= HWIF(drive
);
443 struct icside_state
*state
= hwif
->hwif_data
;
445 return readb(state
->irq_port
+
447 ICS_ARCIN_V6_INTRSTAT_2
:
448 ICS_ARCIN_V6_INTRSTAT_1
)) & 1;
451 static void icside_dma_timeout(ide_drive_t
*drive
)
453 printk(KERN_ERR
"%s: DMA timeout occurred: ", drive
->name
);
455 if (icside_dma_test_irq(drive
))
458 ide_dump_status(drive
, "DMA timeout", HWIF(drive
)->INB(IDE_STATUS_REG
));
460 icside_dma_end(drive
);
463 static void icside_dma_lost_irq(ide_drive_t
*drive
)
465 printk(KERN_ERR
"%s: IRQ lost\n", drive
->name
);
468 static void icside_dma_init(ide_hwif_t
*hwif
)
470 printk(" %s: SG-DMA", hwif
->name
);
473 hwif
->mwdma_mask
= 7; /* MW0..2 */
474 hwif
->swdma_mask
= 7; /* SW0..2 */
476 hwif
->dmatable_cpu
= NULL
;
477 hwif
->dmatable_dma
= 0;
478 hwif
->speedproc
= icside_set_speed
;
481 hwif
->ide_dma_check
= icside_dma_check
;
482 hwif
->dma_host_off
= icside_dma_host_off
;
483 hwif
->dma_off_quietly
= icside_dma_off_quietly
;
484 hwif
->dma_host_on
= icside_dma_host_on
;
485 hwif
->ide_dma_on
= icside_dma_on
;
486 hwif
->dma_setup
= icside_dma_setup
;
487 hwif
->dma_exec_cmd
= icside_dma_exec_cmd
;
488 hwif
->dma_start
= icside_dma_start
;
489 hwif
->ide_dma_end
= icside_dma_end
;
490 hwif
->ide_dma_test_irq
= icside_dma_test_irq
;
491 hwif
->dma_timeout
= icside_dma_timeout
;
492 hwif
->dma_lost_irq
= icside_dma_lost_irq
;
494 hwif
->drives
[0].autodma
= hwif
->autodma
;
495 hwif
->drives
[1].autodma
= hwif
->autodma
;
497 printk(" capable%s\n", hwif
->autodma
? ", auto-enable" : "");
500 #define icside_dma_init(hwif) (0)
503 static ide_hwif_t
*icside_find_hwif(unsigned long dataport
)
508 for (index
= 0; index
< MAX_HWIFS
; ++index
) {
509 hwif
= &ide_hwifs
[index
];
510 if (hwif
->io_ports
[IDE_DATA_OFFSET
] == dataport
)
514 for (index
= 0; index
< MAX_HWIFS
; ++index
) {
515 hwif
= &ide_hwifs
[index
];
516 if (!hwif
->io_ports
[IDE_DATA_OFFSET
])
526 icside_setup(void __iomem
*base
, struct cardinfo
*info
, struct expansion_card
*ec
)
528 unsigned long port
= (unsigned long)base
+ info
->dataoffset
;
531 hwif
= icside_find_hwif(port
);
535 memset(&hwif
->hw
, 0, sizeof(hw_regs_t
));
538 * Ensure we're using MMIO
540 default_hwif_mmiops(hwif
);
543 for (i
= IDE_DATA_OFFSET
; i
<= IDE_STATUS_OFFSET
; i
++) {
544 hwif
->hw
.io_ports
[i
] = port
;
545 hwif
->io_ports
[i
] = port
;
546 port
+= 1 << info
->stepping
;
548 hwif
->hw
.io_ports
[IDE_CONTROL_OFFSET
] = (unsigned long)base
+ info
->ctrloffset
;
549 hwif
->io_ports
[IDE_CONTROL_OFFSET
] = (unsigned long)base
+ info
->ctrloffset
;
550 hwif
->hw
.irq
= ec
->irq
;
553 hwif
->chipset
= ide_acorn
;
554 hwif
->gendev
.parent
= &ec
->dev
;
561 icside_register_v5(struct icside_state
*state
, struct expansion_card
*ec
)
566 base
= ecardm_iomap(ec
, ECARD_RES_MEMC
, 0, 0);
570 state
->irq_port
= base
;
572 ec
->irqaddr
= base
+ ICS_ARCIN_V5_INTRSTAT
;
575 ecard_setirq(ec
, &icside_ops_arcin_v5
, state
);
578 * Be on the safe side - disable interrupts
580 icside_irqdisable_arcin_v5(ec
, 0);
582 hwif
= icside_setup(base
, &icside_cardinfo_v5
, ec
);
586 state
->hwif
[0] = hwif
;
588 probe_hwif_init(hwif
);
590 ide_proc_register_port(hwif
);
596 icside_register_v6(struct icside_state
*state
, struct expansion_card
*ec
)
598 ide_hwif_t
*hwif
, *mate
;
599 void __iomem
*ioc_base
, *easi_base
;
600 unsigned int sel
= 0;
603 ioc_base
= ecardm_iomap(ec
, ECARD_RES_IOCFAST
, 0, 0);
609 easi_base
= ioc_base
;
611 if (ecard_resource_flags(ec
, ECARD_RES_EASI
)) {
612 easi_base
= ecardm_iomap(ec
, ECARD_RES_EASI
, 0, 0);
619 * Enable access to the EASI region.
624 writeb(sel
, ioc_base
);
626 ecard_setirq(ec
, &icside_ops_arcin_v6
, state
);
628 state
->irq_port
= easi_base
;
629 state
->ioc_base
= ioc_base
;
632 * Be on the safe side - disable interrupts
634 icside_irqdisable_arcin_v6(ec
, 0);
637 * Find and register the interfaces.
639 hwif
= icside_setup(easi_base
, &icside_cardinfo_v6_1
, ec
);
640 mate
= icside_setup(easi_base
, &icside_cardinfo_v6_2
, ec
);
642 if (!hwif
|| !mate
) {
647 state
->hwif
[0] = hwif
;
648 state
->hwif
[1] = mate
;
650 hwif
->maskproc
= icside_maskproc
;
652 hwif
->hwif_data
= state
;
654 hwif
->serialized
= 1;
655 hwif
->config_data
= (unsigned long)ioc_base
;
656 hwif
->select_data
= sel
;
657 hwif
->hw
.dma
= ec
->dma
;
659 mate
->maskproc
= icside_maskproc
;
661 mate
->hwif_data
= state
;
663 mate
->serialized
= 1;
664 mate
->config_data
= (unsigned long)ioc_base
;
665 mate
->select_data
= sel
| 1;
666 mate
->hw
.dma
= ec
->dma
;
668 if (ec
->dma
!= NO_DMA
&& !request_dma(ec
->dma
, hwif
->name
)) {
669 icside_dma_init(hwif
);
670 icside_dma_init(mate
);
673 probe_hwif_init(hwif
);
674 probe_hwif_init(mate
);
676 ide_proc_register_port(hwif
);
677 ide_proc_register_port(mate
);
686 icside_probe(struct expansion_card
*ec
, const struct ecard_id
*id
)
688 struct icside_state
*state
;
692 ret
= ecard_request_resources(ec
);
696 state
= kmalloc(sizeof(struct icside_state
), GFP_KERNEL
);
702 memset(state
, 0, sizeof(state
));
703 state
->type
= ICS_TYPE_NOTYPE
;
704 state
->dev
= &ec
->dev
;
706 idmem
= ecardm_iomap(ec
, ECARD_RES_IOCFAST
, 0, 0);
710 type
= readb(idmem
+ ICS_IDENT_OFFSET
) & 1;
711 type
|= (readb(idmem
+ ICS_IDENT_OFFSET
+ 4) & 1) << 1;
712 type
|= (readb(idmem
+ ICS_IDENT_OFFSET
+ 8) & 1) << 2;
713 type
|= (readb(idmem
+ ICS_IDENT_OFFSET
+ 12) & 1) << 3;
714 ecardm_iounmap(ec
, idmem
);
719 switch (state
->type
) {
721 dev_warn(&ec
->dev
, "A3IN unsupported\n");
725 case ICS_TYPE_A3USER
:
726 dev_warn(&ec
->dev
, "A3USER unsupported\n");
731 ret
= icside_register_v5(state
, ec
);
735 ret
= icside_register_v6(state
, ec
);
739 dev_warn(&ec
->dev
, "unknown interface type\n");
745 ecard_set_drvdata(ec
, state
);
751 ecard_release_resources(ec
);
756 static void __devexit
icside_remove(struct expansion_card
*ec
)
758 struct icside_state
*state
= ecard_get_drvdata(ec
);
760 switch (state
->type
) {
762 /* FIXME: tell IDE to stop using the interface */
764 /* Disable interrupts */
765 icside_irqdisable_arcin_v5(ec
, 0);
769 /* FIXME: tell IDE to stop using the interface */
770 if (ec
->dma
!= NO_DMA
)
773 /* Disable interrupts */
774 icside_irqdisable_arcin_v6(ec
, 0);
776 /* Reset the ROM pointer/EASI selection */
777 writeb(0, state
->ioc_base
);
781 ecard_set_drvdata(ec
, NULL
);
784 ecard_release_resources(ec
);
787 static void icside_shutdown(struct expansion_card
*ec
)
789 struct icside_state
*state
= ecard_get_drvdata(ec
);
793 * Disable interrupts from this card. We need to do
794 * this before disabling EASI since we may be accessing
795 * this register via that region.
797 local_irq_save(flags
);
798 ec
->ops
->irqdisable(ec
, 0);
799 local_irq_restore(flags
);
802 * Reset the ROM pointer so that we can read the ROM
803 * after a soft reboot. This also disables access to
804 * the IDE taskfile via the EASI region.
807 writeb(0, state
->ioc_base
);
810 static const struct ecard_id icside_ids
[] = {
811 { MANU_ICS
, PROD_ICS_IDE
},
812 { MANU_ICS2
, PROD_ICS2_IDE
},
816 static struct ecard_driver icside_driver
= {
817 .probe
= icside_probe
,
818 .remove
= __devexit_p(icside_remove
),
819 .shutdown
= icside_shutdown
,
820 .id_table
= icside_ids
,
826 static int __init
icside_init(void)
828 return ecard_register_driver(&icside_driver
);
831 MODULE_AUTHOR("Russell King <rmk@arm.linux.org.uk>");
832 MODULE_LICENSE("GPL");
833 MODULE_DESCRIPTION("ICS IDE driver");
835 module_init(icside_init
);