2 * Copyright (c) 1996-2004 Russell King.
4 * Please note that this platform does not support 32-bit IDE IO.
7 #include <linux/string.h>
8 #include <linux/module.h>
9 #include <linux/ioport.h>
10 #include <linux/slab.h>
11 #include <linux/blkdev.h>
12 #include <linux/errno.h>
13 #include <linux/ide.h>
14 #include <linux/dma-mapping.h>
15 #include <linux/device.h>
16 #include <linux/init.h>
17 #include <linux/scatterlist.h>
21 #include <asm/ecard.h>
23 #define DRV_NAME "icside"
25 #define ICS_IDENT_OFFSET 0x2280
27 #define ICS_ARCIN_V5_INTRSTAT 0x0000
28 #define ICS_ARCIN_V5_INTROFFSET 0x0004
29 #define ICS_ARCIN_V5_IDEOFFSET 0x2800
30 #define ICS_ARCIN_V5_IDEALTOFFSET 0x2b80
31 #define ICS_ARCIN_V5_IDESTEPPING 6
33 #define ICS_ARCIN_V6_IDEOFFSET_1 0x2000
34 #define ICS_ARCIN_V6_INTROFFSET_1 0x2200
35 #define ICS_ARCIN_V6_INTRSTAT_1 0x2290
36 #define ICS_ARCIN_V6_IDEALTOFFSET_1 0x2380
37 #define ICS_ARCIN_V6_IDEOFFSET_2 0x3000
38 #define ICS_ARCIN_V6_INTROFFSET_2 0x3200
39 #define ICS_ARCIN_V6_INTRSTAT_2 0x3290
40 #define ICS_ARCIN_V6_IDEALTOFFSET_2 0x3380
41 #define ICS_ARCIN_V6_IDESTEPPING 6
44 unsigned int dataoffset
;
45 unsigned int ctrloffset
;
46 unsigned int stepping
;
49 static struct cardinfo icside_cardinfo_v5
= {
50 .dataoffset
= ICS_ARCIN_V5_IDEOFFSET
,
51 .ctrloffset
= ICS_ARCIN_V5_IDEALTOFFSET
,
52 .stepping
= ICS_ARCIN_V5_IDESTEPPING
,
55 static struct cardinfo icside_cardinfo_v6_1
= {
56 .dataoffset
= ICS_ARCIN_V6_IDEOFFSET_1
,
57 .ctrloffset
= ICS_ARCIN_V6_IDEALTOFFSET_1
,
58 .stepping
= ICS_ARCIN_V6_IDESTEPPING
,
61 static struct cardinfo icside_cardinfo_v6_2
= {
62 .dataoffset
= ICS_ARCIN_V6_IDEOFFSET_2
,
63 .ctrloffset
= ICS_ARCIN_V6_IDEALTOFFSET_2
,
64 .stepping
= ICS_ARCIN_V6_IDESTEPPING
,
68 void __iomem
*irq_port
;
69 void __iomem
*ioc_base
;
72 struct ide_host
*host
;
75 #define ICS_TYPE_A3IN 0
76 #define ICS_TYPE_A3USER 1
78 #define ICS_TYPE_V5 15
79 #define ICS_TYPE_NOTYPE ((unsigned int)-1)
81 /* ---------------- Version 5 PCB Support Functions --------------------- */
82 /* Prototype: icside_irqenable_arcin_v5 (struct expansion_card *ec, int irqnr)
83 * Purpose : enable interrupts from card
85 static void icside_irqenable_arcin_v5 (struct expansion_card
*ec
, int irqnr
)
87 struct icside_state
*state
= ec
->irq_data
;
89 writeb(0, state
->irq_port
+ ICS_ARCIN_V5_INTROFFSET
);
92 /* Prototype: icside_irqdisable_arcin_v5 (struct expansion_card *ec, int irqnr)
93 * Purpose : disable interrupts from card
95 static void icside_irqdisable_arcin_v5 (struct expansion_card
*ec
, int irqnr
)
97 struct icside_state
*state
= ec
->irq_data
;
99 readb(state
->irq_port
+ ICS_ARCIN_V5_INTROFFSET
);
102 static const expansioncard_ops_t icside_ops_arcin_v5
= {
103 .irqenable
= icside_irqenable_arcin_v5
,
104 .irqdisable
= icside_irqdisable_arcin_v5
,
108 /* ---------------- Version 6 PCB Support Functions --------------------- */
109 /* Prototype: icside_irqenable_arcin_v6 (struct expansion_card *ec, int irqnr)
110 * Purpose : enable interrupts from card
112 static void icside_irqenable_arcin_v6 (struct expansion_card
*ec
, int irqnr
)
114 struct icside_state
*state
= ec
->irq_data
;
115 void __iomem
*base
= state
->irq_port
;
117 writeb(0, base
+ ICS_ARCIN_V6_INTROFFSET_1
);
118 readb(base
+ ICS_ARCIN_V6_INTROFFSET_2
);
120 writeb(0, base
+ ICS_ARCIN_V6_INTROFFSET_2
);
121 readb(base
+ ICS_ARCIN_V6_INTROFFSET_1
);
124 /* Prototype: icside_irqdisable_arcin_v6 (struct expansion_card *ec, int irqnr)
125 * Purpose : disable interrupts from card
127 static void icside_irqdisable_arcin_v6 (struct expansion_card
*ec
, int irqnr
)
129 struct icside_state
*state
= ec
->irq_data
;
131 readb(state
->irq_port
+ ICS_ARCIN_V6_INTROFFSET_1
);
132 readb(state
->irq_port
+ ICS_ARCIN_V6_INTROFFSET_2
);
135 /* Prototype: icside_irqprobe(struct expansion_card *ec)
136 * Purpose : detect an active interrupt from card
138 static int icside_irqpending_arcin_v6(struct expansion_card
*ec
)
140 struct icside_state
*state
= ec
->irq_data
;
142 return readb(state
->irq_port
+ ICS_ARCIN_V6_INTRSTAT_1
) & 1 ||
143 readb(state
->irq_port
+ ICS_ARCIN_V6_INTRSTAT_2
) & 1;
146 static const expansioncard_ops_t icside_ops_arcin_v6
= {
147 .irqenable
= icside_irqenable_arcin_v6
,
148 .irqdisable
= icside_irqdisable_arcin_v6
,
149 .irqpending
= icside_irqpending_arcin_v6
,
152 #ifdef CONFIG_BLK_DEV_IDEDMA_ICS
156 * Similar to the BM-DMA, but we use the RiscPCs IOMD DMA controllers.
157 * There is only one DMA controller per card, which means that only
158 * one drive can be accessed at one time. NOTE! We do not enforce that
159 * here, but we rely on the main IDE driver spotting that both
160 * interfaces use the same IRQ, which should guarantee this.
164 * Configure the IOMD to give the appropriate timings for the transfer
165 * mode being requested. We take the advice of the ATA standards, and
166 * calculate the cycle time based on the transfer mode, and the EIDE
167 * MW DMA specs that the drive provides in the IDENTIFY command.
169 * We have the following IOMD DMA modes to choose from:
171 * Type Active Recovery Cycle
172 * A 250 (250) 312 (550) 562 (800)
174 * C 125 (125) 125 (375) 250 (500)
177 * (figures in brackets are actual measured timings)
179 * However, we also need to take care of the read/write active and
183 * Mode Active -- Recovery -- Cycle IOMD type
184 * MW0 215 50 215 480 A
188 static void icside_set_dma_mode(ide_drive_t
*drive
, const u8 xfer_mode
)
190 int cycle_time
, use_dma_info
= 0;
215 * If we're going to be doing MW_DMA_1 or MW_DMA_2, we should
216 * take care to note the values in the ID...
218 if (use_dma_info
&& drive
->id
[ATA_ID_EIDE_DMA_TIME
] > cycle_time
)
219 cycle_time
= drive
->id
[ATA_ID_EIDE_DMA_TIME
];
221 drive
->drive_data
= cycle_time
;
223 printk("%s: %s selected (peak %dMB/s)\n", drive
->name
,
224 ide_xfer_verbose(xfer_mode
), 2000 / drive
->drive_data
);
227 static const struct ide_port_ops icside_v6_port_ops
= {
228 .set_dma_mode
= icside_set_dma_mode
,
231 static void icside_dma_host_set(ide_drive_t
*drive
, int on
)
235 static int icside_dma_end(ide_drive_t
*drive
)
237 ide_hwif_t
*hwif
= drive
->hwif
;
238 struct expansion_card
*ec
= ECARD_DEV(hwif
->dev
);
240 disable_dma(ec
->dma
);
242 return get_dma_residue(ec
->dma
) != 0;
245 static void icside_dma_start(ide_drive_t
*drive
)
247 ide_hwif_t
*hwif
= drive
->hwif
;
248 struct expansion_card
*ec
= ECARD_DEV(hwif
->dev
);
250 /* We can not enable DMA on both channels simultaneously. */
251 BUG_ON(dma_channel_active(ec
->dma
));
255 static int icside_dma_setup(ide_drive_t
*drive
, struct ide_cmd
*cmd
)
257 ide_hwif_t
*hwif
= drive
->hwif
;
258 struct expansion_card
*ec
= ECARD_DEV(hwif
->dev
);
259 struct icside_state
*state
= ecard_get_drvdata(ec
);
260 unsigned int dma_mode
;
262 if (cmd
->tf_flags
& IDE_TFLAG_WRITE
)
263 dma_mode
= DMA_MODE_WRITE
;
265 dma_mode
= DMA_MODE_READ
;
268 * We can not enable DMA on both channels.
270 BUG_ON(dma_channel_active(ec
->dma
));
273 * Route the DMA signals to the correct interface.
275 writeb(state
->sel
| hwif
->channel
, state
->ioc_base
);
278 * Select the correct timing for this drive.
280 set_dma_speed(ec
->dma
, drive
->drive_data
);
283 * Tell the DMA engine about the SG table and
286 set_dma_sg(ec
->dma
, hwif
->sg_table
, cmd
->sg_nents
);
287 set_dma_mode(ec
->dma
, dma_mode
);
292 static int icside_dma_test_irq(ide_drive_t
*drive
)
294 ide_hwif_t
*hwif
= drive
->hwif
;
295 struct expansion_card
*ec
= ECARD_DEV(hwif
->dev
);
296 struct icside_state
*state
= ecard_get_drvdata(ec
);
298 return readb(state
->irq_port
+
300 ICS_ARCIN_V6_INTRSTAT_2
:
301 ICS_ARCIN_V6_INTRSTAT_1
)) & 1;
304 static int icside_dma_init(ide_hwif_t
*hwif
, const struct ide_port_info
*d
)
306 hwif
->dmatable_cpu
= NULL
;
307 hwif
->dmatable_dma
= 0;
312 static const struct ide_dma_ops icside_v6_dma_ops
= {
313 .dma_host_set
= icside_dma_host_set
,
314 .dma_setup
= icside_dma_setup
,
315 .dma_start
= icside_dma_start
,
316 .dma_end
= icside_dma_end
,
317 .dma_test_irq
= icside_dma_test_irq
,
318 .dma_lost_irq
= ide_dma_lost_irq
,
321 #define icside_v6_dma_ops NULL
324 static int icside_dma_off_init(ide_hwif_t
*hwif
, const struct ide_port_info
*d
)
329 static void icside_setup_ports(struct ide_hw
*hw
, void __iomem
*base
,
330 struct cardinfo
*info
, struct expansion_card
*ec
)
332 unsigned long port
= (unsigned long)base
+ info
->dataoffset
;
334 hw
->io_ports
.data_addr
= port
;
335 hw
->io_ports
.error_addr
= port
+ (1 << info
->stepping
);
336 hw
->io_ports
.nsect_addr
= port
+ (2 << info
->stepping
);
337 hw
->io_ports
.lbal_addr
= port
+ (3 << info
->stepping
);
338 hw
->io_ports
.lbam_addr
= port
+ (4 << info
->stepping
);
339 hw
->io_ports
.lbah_addr
= port
+ (5 << info
->stepping
);
340 hw
->io_ports
.device_addr
= port
+ (6 << info
->stepping
);
341 hw
->io_ports
.status_addr
= port
+ (7 << info
->stepping
);
342 hw
->io_ports
.ctl_addr
= (unsigned long)base
+ info
->ctrloffset
;
348 static const struct ide_port_info icside_v5_port_info
= {
349 .host_flags
= IDE_HFLAG_NO_DMA
,
350 .chipset
= ide_acorn
,
354 icside_register_v5(struct icside_state
*state
, struct expansion_card
*ec
)
357 struct ide_host
*host
;
358 struct ide_hw hw
, *hws
[] = { &hw
};
361 base
= ecardm_iomap(ec
, ECARD_RES_MEMC
, 0, 0);
365 state
->irq_port
= base
;
367 ec
->irqaddr
= base
+ ICS_ARCIN_V5_INTRSTAT
;
370 ecard_setirq(ec
, &icside_ops_arcin_v5
, state
);
373 * Be on the safe side - disable interrupts
375 icside_irqdisable_arcin_v5(ec
, 0);
377 icside_setup_ports(&hw
, base
, &icside_cardinfo_v5
, ec
);
379 host
= ide_host_alloc(&icside_v5_port_info
, hws
, 1);
385 ecard_set_drvdata(ec
, state
);
387 ret
= ide_host_register(host
, &icside_v5_port_info
, hws
);
394 ecard_set_drvdata(ec
, NULL
);
398 static const struct ide_port_info icside_v6_port_info __initdata
= {
399 .init_dma
= icside_dma_off_init
,
400 .dma_ops
= &icside_v6_dma_ops
,
401 .host_flags
= IDE_HFLAG_SERIALIZE
| IDE_HFLAG_MMIO
,
402 .mwdma_mask
= ATA_MWDMA2
,
403 .swdma_mask
= ATA_SWDMA2
,
404 .chipset
= ide_acorn
,
408 icside_register_v6(struct icside_state
*state
, struct expansion_card
*ec
)
410 void __iomem
*ioc_base
, *easi_base
;
411 struct ide_host
*host
;
412 unsigned int sel
= 0;
414 struct ide_hw hw
[2], *hws
[] = { &hw
[0], &hw
[1] };
415 struct ide_port_info d
= icside_v6_port_info
;
417 ioc_base
= ecardm_iomap(ec
, ECARD_RES_IOCFAST
, 0, 0);
423 easi_base
= ioc_base
;
425 if (ecard_resource_flags(ec
, ECARD_RES_EASI
)) {
426 easi_base
= ecardm_iomap(ec
, ECARD_RES_EASI
, 0, 0);
433 * Enable access to the EASI region.
438 writeb(sel
, ioc_base
);
440 ecard_setirq(ec
, &icside_ops_arcin_v6
, state
);
442 state
->irq_port
= easi_base
;
443 state
->ioc_base
= ioc_base
;
447 * Be on the safe side - disable interrupts
449 icside_irqdisable_arcin_v6(ec
, 0);
451 icside_setup_ports(&hw
[0], easi_base
, &icside_cardinfo_v6_1
, ec
);
452 icside_setup_ports(&hw
[1], easi_base
, &icside_cardinfo_v6_2
, ec
);
454 host
= ide_host_alloc(&d
, hws
, 2);
460 ecard_set_drvdata(ec
, state
);
462 if (ec
->dma
!= NO_DMA
&& !request_dma(ec
->dma
, DRV_NAME
)) {
463 d
.init_dma
= icside_dma_init
;
464 d
.port_ops
= &icside_v6_port_ops
;
468 ret
= ide_host_register(host
, &d
, hws
);
477 ecard_set_drvdata(ec
, NULL
);
483 icside_probe(struct expansion_card
*ec
, const struct ecard_id
*id
)
485 struct icside_state
*state
;
489 ret
= ecard_request_resources(ec
);
493 state
= kzalloc(sizeof(struct icside_state
), GFP_KERNEL
);
499 state
->type
= ICS_TYPE_NOTYPE
;
501 idmem
= ecardm_iomap(ec
, ECARD_RES_IOCFAST
, 0, 0);
505 type
= readb(idmem
+ ICS_IDENT_OFFSET
) & 1;
506 type
|= (readb(idmem
+ ICS_IDENT_OFFSET
+ 4) & 1) << 1;
507 type
|= (readb(idmem
+ ICS_IDENT_OFFSET
+ 8) & 1) << 2;
508 type
|= (readb(idmem
+ ICS_IDENT_OFFSET
+ 12) & 1) << 3;
509 ecardm_iounmap(ec
, idmem
);
514 switch (state
->type
) {
516 dev_warn(&ec
->dev
, "A3IN unsupported\n");
520 case ICS_TYPE_A3USER
:
521 dev_warn(&ec
->dev
, "A3USER unsupported\n");
526 ret
= icside_register_v5(state
, ec
);
530 ret
= icside_register_v6(state
, ec
);
534 dev_warn(&ec
->dev
, "unknown interface type\n");
544 ecard_release_resources(ec
);
549 static void __devexit
icside_remove(struct expansion_card
*ec
)
551 struct icside_state
*state
= ecard_get_drvdata(ec
);
553 switch (state
->type
) {
555 /* FIXME: tell IDE to stop using the interface */
557 /* Disable interrupts */
558 icside_irqdisable_arcin_v5(ec
, 0);
562 /* FIXME: tell IDE to stop using the interface */
563 if (ec
->dma
!= NO_DMA
)
566 /* Disable interrupts */
567 icside_irqdisable_arcin_v6(ec
, 0);
569 /* Reset the ROM pointer/EASI selection */
570 writeb(0, state
->ioc_base
);
574 ecard_set_drvdata(ec
, NULL
);
577 ecard_release_resources(ec
);
580 static void icside_shutdown(struct expansion_card
*ec
)
582 struct icside_state
*state
= ecard_get_drvdata(ec
);
586 * Disable interrupts from this card. We need to do
587 * this before disabling EASI since we may be accessing
588 * this register via that region.
590 local_irq_save(flags
);
591 ec
->ops
->irqdisable(ec
, 0);
592 local_irq_restore(flags
);
595 * Reset the ROM pointer so that we can read the ROM
596 * after a soft reboot. This also disables access to
597 * the IDE taskfile via the EASI region.
600 writeb(0, state
->ioc_base
);
603 static const struct ecard_id icside_ids
[] = {
604 { MANU_ICS
, PROD_ICS_IDE
},
605 { MANU_ICS2
, PROD_ICS2_IDE
},
609 static struct ecard_driver icside_driver
= {
610 .probe
= icside_probe
,
611 .remove
= __devexit_p(icside_remove
),
612 .shutdown
= icside_shutdown
,
613 .id_table
= icside_ids
,
619 static int __init
icside_init(void)
621 return ecard_register_driver(&icside_driver
);
624 static void __exit
icside_exit(void)
626 ecard_remove_driver(&icside_driver
);
629 MODULE_AUTHOR("Russell King <rmk@arm.linux.org.uk>");
630 MODULE_LICENSE("GPL");
631 MODULE_DESCRIPTION("ICS IDE driver");
633 module_init(icside_init
);
634 module_exit(icside_exit
);