2 * linux/drivers/ide/mips/au1xxx-ide.c version 01.30.00 Aug. 02 2005
4 * BRIEF MODULE DESCRIPTION
5 * AMD Alchemy Au1xxx IDE interface routines over the Static Bus
7 * Copyright (c) 2003-2005 AMD, Personal Connectivity Solutions
9 * This program is free software; you can redistribute it and/or modify it under
10 * the terms of the GNU General Public License as published by the Free Software
11 * Foundation; either version 2 of the License, or (at your option) any later
14 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES,
15 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
16 * FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR
17 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
18 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
19 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
20 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
21 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
22 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
23 * POSSIBILITY OF SUCH DAMAGE.
25 * You should have received a copy of the GNU General Public License along with
26 * this program; if not, write to the Free Software Foundation, Inc.,
27 * 675 Mass Ave, Cambridge, MA 02139, USA.
29 * Note: for more information, please refer "AMD Alchemy Au1200/Au1550 IDE
30 * Interface and Linux Device Driver" Application Note.
32 #include <linux/types.h>
33 #include <linux/module.h>
34 #include <linux/kernel.h>
35 #include <linux/delay.h>
36 #include <linux/platform_device.h>
38 #include <linux/init.h>
39 #include <linux/ide.h>
40 #include <linux/sysdev.h>
42 #include <linux/dma-mapping.h>
44 #include "ide-timing.h"
47 #include <asm/mach-au1x00/au1xxx.h>
48 #include <asm/mach-au1x00/au1xxx_dbdma.h>
50 #include <asm/mach-au1x00/au1xxx_ide.h>
52 #define DRV_NAME "au1200-ide"
53 #define DRV_VERSION "1.0"
54 #define DRV_AUTHOR "Enrico Walther <enrico.walther@amd.com> / Pete Popov <ppopov@embeddedalley.com>"
56 /* enable the burstmode in the dbdma */
57 #define IDE_AU1XXX_BURSTMODE 1
59 static _auide_hwif auide_hwif
;
60 static int dbdma_init_done
;
62 #if defined(CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA)
64 void auide_insw(unsigned long port
, void *addr
, u32 count
)
66 _auide_hwif
*ahwif
= &auide_hwif
;
70 if(!put_dest_flags(ahwif
->rx_chan
, (void*)addr
, count
<< 1,
72 printk(KERN_ERR
"%s failed %d\n", __FUNCTION__
, __LINE__
);
75 ctp
= *((chan_tab_t
**)ahwif
->rx_chan
);
77 while (dp
->dscr_cmd0
& DSCR_CMD0_V
)
79 ctp
->cur_ptr
= au1xxx_ddma_get_nextptr_virt(dp
);
82 void auide_outsw(unsigned long port
, void *addr
, u32 count
)
84 _auide_hwif
*ahwif
= &auide_hwif
;
88 if(!put_source_flags(ahwif
->tx_chan
, (void*)addr
,
89 count
<< 1, DDMA_FLAGS_NOIE
)) {
90 printk(KERN_ERR
"%s failed %d\n", __FUNCTION__
, __LINE__
);
93 ctp
= *((chan_tab_t
**)ahwif
->tx_chan
);
95 while (dp
->dscr_cmd0
& DSCR_CMD0_V
)
97 ctp
->cur_ptr
= au1xxx_ddma_get_nextptr_virt(dp
);
102 static void auide_tune_drive(ide_drive_t
*drive
, byte pio
)
108 /* get the best pio mode for the drive */
109 pio
= ide_get_best_pio_mode(drive
, pio
, 4);
111 printk(KERN_INFO
"%s: setting Au1XXX IDE to PIO mode%d\n",
115 mem_stcfg
= au_readl(MEM_STCFG2
);
120 mem_sttime
= SBC_IDE_TIMING(PIO0
);
122 /* set configuration for RCS2# */
123 mem_stcfg
|= TS_MASK
;
124 mem_stcfg
&= ~TCSOE_MASK
;
125 mem_stcfg
&= ~TOECS_MASK
;
126 mem_stcfg
|= SBC_IDE_PIO0_TCSOE
| SBC_IDE_PIO0_TOECS
;
130 mem_sttime
= SBC_IDE_TIMING(PIO1
);
132 /* set configuration for RCS2# */
133 mem_stcfg
|= TS_MASK
;
134 mem_stcfg
&= ~TCSOE_MASK
;
135 mem_stcfg
&= ~TOECS_MASK
;
136 mem_stcfg
|= SBC_IDE_PIO1_TCSOE
| SBC_IDE_PIO1_TOECS
;
140 mem_sttime
= SBC_IDE_TIMING(PIO2
);
142 /* set configuration for RCS2# */
143 mem_stcfg
&= ~TS_MASK
;
144 mem_stcfg
&= ~TCSOE_MASK
;
145 mem_stcfg
&= ~TOECS_MASK
;
146 mem_stcfg
|= SBC_IDE_PIO2_TCSOE
| SBC_IDE_PIO2_TOECS
;
150 mem_sttime
= SBC_IDE_TIMING(PIO3
);
152 /* set configuration for RCS2# */
153 mem_stcfg
&= ~TS_MASK
;
154 mem_stcfg
&= ~TCSOE_MASK
;
155 mem_stcfg
&= ~TOECS_MASK
;
156 mem_stcfg
|= SBC_IDE_PIO3_TCSOE
| SBC_IDE_PIO3_TOECS
;
161 mem_sttime
= SBC_IDE_TIMING(PIO4
);
163 /* set configuration for RCS2# */
164 mem_stcfg
&= ~TS_MASK
;
165 mem_stcfg
&= ~TCSOE_MASK
;
166 mem_stcfg
&= ~TOECS_MASK
;
167 mem_stcfg
|= SBC_IDE_PIO4_TCSOE
| SBC_IDE_PIO4_TOECS
;
171 au_writel(mem_sttime
,MEM_STTIME2
);
172 au_writel(mem_stcfg
,MEM_STCFG2
);
174 speed
= pio
+ XFER_PIO_0
;
175 ide_config_drive_speed(drive
, speed
);
178 static int auide_tune_chipset (ide_drive_t
*drive
, u8 speed
)
184 mem_stcfg
= au_readl(MEM_STCFG2
);
186 if (speed
>= XFER_PIO_0
&& speed
<= XFER_PIO_4
) {
187 auide_tune_drive(drive
, speed
- XFER_PIO_0
);
192 #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
194 mem_sttime
= SBC_IDE_TIMING(MDMA2
);
196 /* set configuration for RCS2# */
197 mem_stcfg
&= ~TS_MASK
;
198 mem_stcfg
&= ~TCSOE_MASK
;
199 mem_stcfg
&= ~TOECS_MASK
;
200 mem_stcfg
|= SBC_IDE_MDMA2_TCSOE
| SBC_IDE_MDMA2_TOECS
;
204 mem_sttime
= SBC_IDE_TIMING(MDMA1
);
206 /* set configuration for RCS2# */
207 mem_stcfg
&= ~TS_MASK
;
208 mem_stcfg
&= ~TCSOE_MASK
;
209 mem_stcfg
&= ~TOECS_MASK
;
210 mem_stcfg
|= SBC_IDE_MDMA1_TCSOE
| SBC_IDE_MDMA1_TOECS
;
214 mem_sttime
= SBC_IDE_TIMING(MDMA0
);
216 /* set configuration for RCS2# */
217 mem_stcfg
|= TS_MASK
;
218 mem_stcfg
&= ~TCSOE_MASK
;
219 mem_stcfg
&= ~TOECS_MASK
;
220 mem_stcfg
|= SBC_IDE_MDMA0_TCSOE
| SBC_IDE_MDMA0_TOECS
;
228 if (ide_config_drive_speed(drive
, speed
))
231 au_writel(mem_sttime
,MEM_STTIME2
);
232 au_writel(mem_stcfg
,MEM_STCFG2
);
238 * Multi-Word DMA + DbDMA functions
241 #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
243 static int auide_build_sglist(ide_drive_t
*drive
, struct request
*rq
)
245 ide_hwif_t
*hwif
= drive
->hwif
;
246 _auide_hwif
*ahwif
= (_auide_hwif
*)hwif
->hwif_data
;
247 struct scatterlist
*sg
= hwif
->sg_table
;
249 ide_map_sg(drive
, rq
);
251 if (rq_data_dir(rq
) == READ
)
252 hwif
->sg_dma_direction
= DMA_FROM_DEVICE
;
254 hwif
->sg_dma_direction
= DMA_TO_DEVICE
;
256 return dma_map_sg(ahwif
->dev
, sg
, hwif
->sg_nents
,
257 hwif
->sg_dma_direction
);
260 static int auide_build_dmatable(ide_drive_t
*drive
)
262 int i
, iswrite
, count
= 0;
263 ide_hwif_t
*hwif
= HWIF(drive
);
265 struct request
*rq
= HWGROUP(drive
)->rq
;
267 _auide_hwif
*ahwif
= (_auide_hwif
*)hwif
->hwif_data
;
268 struct scatterlist
*sg
;
270 iswrite
= (rq_data_dir(rq
) == WRITE
);
271 /* Save for interrupt context */
272 ahwif
->drive
= drive
;
275 hwif
->sg_nents
= i
= auide_build_sglist(drive
, rq
);
280 /* fill the descriptors */
282 while (i
&& sg_dma_len(sg
)) {
286 cur_addr
= sg_dma_address(sg
);
287 cur_len
= sg_dma_len(sg
);
290 u32 flags
= DDMA_FLAGS_NOIE
;
291 unsigned int tc
= (cur_len
< 0xfe00)? cur_len
: 0xfe00;
293 if (++count
>= PRD_ENTRIES
) {
294 printk(KERN_WARNING
"%s: DMA table too small\n",
296 goto use_pio_instead
;
299 /* Lets enable intr for the last descriptor only */
301 flags
= DDMA_FLAGS_IE
;
303 flags
= DDMA_FLAGS_NOIE
;
306 if(!put_source_flags(ahwif
->tx_chan
,
307 (void*)(page_address(sg
->page
)
310 printk(KERN_ERR
"%s failed %d\n",
311 __FUNCTION__
, __LINE__
);
315 if(!put_dest_flags(ahwif
->rx_chan
,
316 (void*)(page_address(sg
->page
)
319 printk(KERN_ERR
"%s failed %d\n",
320 __FUNCTION__
, __LINE__
);
335 dma_unmap_sg(ahwif
->dev
,
338 hwif
->sg_dma_direction
);
340 return 0; /* revert to PIO for this request */
343 static int auide_dma_end(ide_drive_t
*drive
)
345 ide_hwif_t
*hwif
= HWIF(drive
);
346 _auide_hwif
*ahwif
= (_auide_hwif
*)hwif
->hwif_data
;
348 if (hwif
->sg_nents
) {
349 dma_unmap_sg(ahwif
->dev
, hwif
->sg_table
, hwif
->sg_nents
,
350 hwif
->sg_dma_direction
);
357 static void auide_dma_start(ide_drive_t
*drive
)
362 static void auide_dma_exec_cmd(ide_drive_t
*drive
, u8 command
)
364 /* issue cmd to drive */
365 ide_execute_command(drive
, command
, &ide_dma_intr
,
369 static int auide_dma_setup(ide_drive_t
*drive
)
371 struct request
*rq
= HWGROUP(drive
)->rq
;
373 if (!auide_build_dmatable(drive
)) {
374 ide_map_sg(drive
, rq
);
378 drive
->waiting_for_dma
= 1;
382 static int auide_dma_check(ide_drive_t
*drive
)
384 u8 speed
= ide_max_dma_mode(drive
);
386 if( dbdma_init_done
== 0 ){
387 auide_hwif
.white_list
= ide_in_drive_list(drive
->id
,
389 auide_hwif
.black_list
= ide_in_drive_list(drive
->id
,
391 auide_hwif
.drive
= drive
;
392 auide_ddma_init(&auide_hwif
);
396 /* Is the drive in our DMA black list? */
398 if ( auide_hwif
.black_list
) {
399 drive
->using_dma
= 0;
401 /* Borrowed the warning message from ide-dma.c */
403 printk(KERN_WARNING
"%s: Disabling DMA for %s (blacklisted)\n",
404 drive
->name
, drive
->id
->model
);
407 drive
->using_dma
= 1;
409 if (drive
->autodma
&& (speed
& XFER_MODE
) != XFER_PIO
)
415 static int auide_dma_test_irq(ide_drive_t
*drive
)
417 if (drive
->waiting_for_dma
== 0)
418 printk(KERN_WARNING
"%s: ide_dma_test_irq \
419 called while not waiting\n", drive
->name
);
421 /* If dbdma didn't execute the STOP command yet, the
422 * active bit is still set
424 drive
->waiting_for_dma
++;
425 if (drive
->waiting_for_dma
>= DMA_WAIT_TIMEOUT
) {
426 printk(KERN_WARNING
"%s: timeout waiting for ddma to \
427 complete\n", drive
->name
);
434 static void auide_dma_host_on(ide_drive_t
*drive
)
438 static int auide_dma_on(ide_drive_t
*drive
)
440 drive
->using_dma
= 1;
445 static void auide_dma_host_off(ide_drive_t
*drive
)
449 static void auide_dma_off_quietly(ide_drive_t
*drive
)
451 drive
->using_dma
= 0;
454 static void auide_dma_lost_irq(ide_drive_t
*drive
)
456 printk(KERN_ERR
"%s: IRQ lost\n", drive
->name
);
459 static void auide_ddma_tx_callback(int irq
, void *param
)
461 _auide_hwif
*ahwif
= (_auide_hwif
*)param
;
462 ahwif
->drive
->waiting_for_dma
= 0;
465 static void auide_ddma_rx_callback(int irq
, void *param
)
467 _auide_hwif
*ahwif
= (_auide_hwif
*)param
;
468 ahwif
->drive
->waiting_for_dma
= 0;
471 #endif /* end CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA */
473 static void auide_init_dbdma_dev(dbdev_tab_t
*dev
, u32 dev_id
, u32 tsize
, u32 devwidth
, u32 flags
)
475 dev
->dev_id
= dev_id
;
476 dev
->dev_physaddr
= (u32
)AU1XXX_ATA_PHYS_ADDR
;
477 dev
->dev_intlevel
= 0;
478 dev
->dev_intpolarity
= 0;
479 dev
->dev_tsize
= tsize
;
480 dev
->dev_devwidth
= devwidth
;
481 dev
->dev_flags
= flags
;
484 #if defined(CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA)
486 static void auide_dma_timeout(ide_drive_t
*drive
)
488 ide_hwif_t
*hwif
= HWIF(drive
);
490 printk(KERN_ERR
"%s: DMA timeout occurred: ", drive
->name
);
492 if (hwif
->ide_dma_test_irq(drive
))
495 hwif
->ide_dma_end(drive
);
499 static int auide_ddma_init(_auide_hwif
*auide
) {
501 dbdev_tab_t source_dev_tab
, target_dev_tab
;
502 u32 dev_id
, tsize
, devwidth
, flags
;
503 ide_hwif_t
*hwif
= auide
->hwif
;
505 dev_id
= AU1XXX_ATA_DDMA_REQ
;
507 if (auide
->white_list
|| auide
->black_list
) {
515 printk(KERN_ERR
"au1xxx-ide: %s is not on ide driver whitelist.\n",auide_hwif
.drive
->id
->model
);
516 printk(KERN_ERR
" please read 'Documentation/mips/AU1xxx_IDE.README'");
519 #ifdef IDE_AU1XXX_BURSTMODE
520 flags
= DEV_FLAGS_SYNC
| DEV_FLAGS_BURSTABLE
;
522 flags
= DEV_FLAGS_SYNC
;
525 /* setup dev_tab for tx channel */
526 auide_init_dbdma_dev( &source_dev_tab
,
528 tsize
, devwidth
, DEV_FLAGS_OUT
| flags
);
529 auide
->tx_dev_id
= au1xxx_ddma_add_device( &source_dev_tab
);
531 auide_init_dbdma_dev( &source_dev_tab
,
533 tsize
, devwidth
, DEV_FLAGS_IN
| flags
);
534 auide
->rx_dev_id
= au1xxx_ddma_add_device( &source_dev_tab
);
536 /* We also need to add a target device for the DMA */
537 auide_init_dbdma_dev( &target_dev_tab
,
538 (u32
)DSCR_CMD0_ALWAYS
,
539 tsize
, devwidth
, DEV_FLAGS_ANYUSE
);
540 auide
->target_dev_id
= au1xxx_ddma_add_device(&target_dev_tab
);
542 /* Get a channel for TX */
543 auide
->tx_chan
= au1xxx_dbdma_chan_alloc(auide
->target_dev_id
,
545 auide_ddma_tx_callback
,
548 /* Get a channel for RX */
549 auide
->rx_chan
= au1xxx_dbdma_chan_alloc(auide
->rx_dev_id
,
550 auide
->target_dev_id
,
551 auide_ddma_rx_callback
,
554 auide
->tx_desc_head
= (void*)au1xxx_dbdma_ring_alloc(auide
->tx_chan
,
556 auide
->rx_desc_head
= (void*)au1xxx_dbdma_ring_alloc(auide
->rx_chan
,
559 hwif
->dmatable_cpu
= dma_alloc_coherent(auide
->dev
,
560 PRD_ENTRIES
* PRD_BYTES
, /* 1 Page */
561 &hwif
->dmatable_dma
, GFP_KERNEL
);
563 au1xxx_dbdma_start( auide
->tx_chan
);
564 au1xxx_dbdma_start( auide
->rx_chan
);
570 static int auide_ddma_init( _auide_hwif
*auide
)
572 dbdev_tab_t source_dev_tab
;
575 #ifdef IDE_AU1XXX_BURSTMODE
576 flags
= DEV_FLAGS_SYNC
| DEV_FLAGS_BURSTABLE
;
578 flags
= DEV_FLAGS_SYNC
;
581 /* setup dev_tab for tx channel */
582 auide_init_dbdma_dev( &source_dev_tab
,
583 (u32
)DSCR_CMD0_ALWAYS
,
584 8, 32, DEV_FLAGS_OUT
| flags
);
585 auide
->tx_dev_id
= au1xxx_ddma_add_device( &source_dev_tab
);
587 auide_init_dbdma_dev( &source_dev_tab
,
588 (u32
)DSCR_CMD0_ALWAYS
,
589 8, 32, DEV_FLAGS_IN
| flags
);
590 auide
->rx_dev_id
= au1xxx_ddma_add_device( &source_dev_tab
);
592 /* Get a channel for TX */
593 auide
->tx_chan
= au1xxx_dbdma_chan_alloc(DSCR_CMD0_ALWAYS
,
598 /* Get a channel for RX */
599 auide
->rx_chan
= au1xxx_dbdma_chan_alloc(auide
->rx_dev_id
,
604 auide
->tx_desc_head
= (void*)au1xxx_dbdma_ring_alloc(auide
->tx_chan
,
606 auide
->rx_desc_head
= (void*)au1xxx_dbdma_ring_alloc(auide
->rx_chan
,
609 au1xxx_dbdma_start( auide
->tx_chan
);
610 au1xxx_dbdma_start( auide
->rx_chan
);
616 static void auide_setup_ports(hw_regs_t
*hw
, _auide_hwif
*ahwif
)
619 unsigned long *ata_regs
= hw
->io_ports
;
622 for (i
= 0; i
< IDE_CONTROL_OFFSET
; i
++) {
623 *ata_regs
++ = ahwif
->regbase
+ (i
<< AU1XXX_ATA_REG_OFFSET
);
626 /* set the Alternative Status register */
627 *ata_regs
= ahwif
->regbase
+ (14 << AU1XXX_ATA_REG_OFFSET
);
630 static int au_ide_probe(struct device
*dev
)
632 struct platform_device
*pdev
= to_platform_device(dev
);
633 _auide_hwif
*ahwif
= &auide_hwif
;
635 struct resource
*res
;
639 #if defined(CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA)
640 char *mode
= "MWDMA2";
641 #elif defined(CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA)
642 char *mode
= "PIO+DDMA(offload)";
645 memset(&auide_hwif
, 0, sizeof(_auide_hwif
));
649 ahwif
->irq
= platform_get_irq(pdev
, 0);
651 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
654 pr_debug("%s %d: no base address\n", DRV_NAME
, pdev
->id
);
658 if (ahwif
->irq
< 0) {
659 pr_debug("%s %d: no IRQ\n", DRV_NAME
, pdev
->id
);
664 if (!request_mem_region (res
->start
, res
->end
-res
->start
, pdev
->name
)) {
665 pr_debug("%s: request_mem_region failed\n", DRV_NAME
);
670 ahwif
->regbase
= (u32
)ioremap(res
->start
, res
->end
-res
->start
);
671 if (ahwif
->regbase
== 0) {
676 /* FIXME: This might possibly break PCMCIA IDE devices */
678 hwif
= &ide_hwifs
[pdev
->id
];
680 hwif
->irq
= hw
->irq
= ahwif
->irq
;
681 hwif
->chipset
= ide_au1xxx
;
683 auide_setup_ports(hw
, ahwif
);
684 memcpy(hwif
->io_ports
, hw
->io_ports
, sizeof(hwif
->io_ports
));
686 hwif
->ultra_mask
= 0x0; /* Disable Ultra DMA */
687 #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
688 hwif
->mwdma_mask
= 0x07; /* Multimode-2 DMA */
689 hwif
->swdma_mask
= 0x00;
691 hwif
->mwdma_mask
= 0x0;
692 hwif
->swdma_mask
= 0x0;
695 hwif
->pio_mask
= ATA_PIO4
;
698 hwif
->drives
[0].unmask
= 1;
699 hwif
->drives
[1].unmask
= 1;
701 /* hold should be on in all cases */
706 /* If the user has selected DDMA assisted copies,
707 then set up a few local I/O function entry points
710 #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA
711 hwif
->INSW
= auide_insw
;
712 hwif
->OUTSW
= auide_outsw
;
715 hwif
->tuneproc
= &auide_tune_drive
;
716 hwif
->speedproc
= &auide_tune_chipset
;
718 #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
719 hwif
->dma_off_quietly
= &auide_dma_off_quietly
;
720 hwif
->dma_timeout
= &auide_dma_timeout
;
722 hwif
->ide_dma_check
= &auide_dma_check
;
723 hwif
->dma_exec_cmd
= &auide_dma_exec_cmd
;
724 hwif
->dma_start
= &auide_dma_start
;
725 hwif
->ide_dma_end
= &auide_dma_end
;
726 hwif
->dma_setup
= &auide_dma_setup
;
727 hwif
->ide_dma_test_irq
= &auide_dma_test_irq
;
728 hwif
->dma_host_off
= &auide_dma_host_off
;
729 hwif
->dma_host_on
= &auide_dma_host_on
;
730 hwif
->dma_lost_irq
= &auide_dma_lost_irq
;
731 hwif
->ide_dma_on
= &auide_dma_on
;
734 hwif
->drives
[0].autodma
= hwif
->autodma
;
735 hwif
->drives
[1].autodma
= hwif
->autodma
;
738 #else /* !CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA */
742 hwif
->select_data
= 0; /* no chipset-specific code */
743 hwif
->config_data
= 0; /* no chipset-specific code */
745 hwif
->drives
[0].autodma
= 0;
746 hwif
->drives
[0].autotune
= 1; /* 1=autotune, 2=noautotune, 0=default */
748 hwif
->drives
[0].no_io_32bit
= 1;
750 auide_hwif
.hwif
= hwif
;
751 hwif
->hwif_data
= &auide_hwif
;
753 #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA
754 auide_ddma_init(&auide_hwif
);
758 probe_hwif_init(hwif
);
760 ide_proc_register_port(hwif
);
762 dev_set_drvdata(dev
, hwif
);
764 printk(KERN_INFO
"Au1xxx IDE(builtin) configured for %s\n", mode
);
770 static int au_ide_remove(struct device
*dev
)
772 struct platform_device
*pdev
= to_platform_device(dev
);
773 struct resource
*res
;
774 ide_hwif_t
*hwif
= dev_get_drvdata(dev
);
775 _auide_hwif
*ahwif
= &auide_hwif
;
777 ide_unregister(hwif
- ide_hwifs
);
779 iounmap((void *)ahwif
->regbase
);
781 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
782 release_mem_region(res
->start
, res
->end
- res
->start
);
787 static struct device_driver au1200_ide_driver
= {
788 .name
= "au1200-ide",
789 .bus
= &platform_bus_type
,
790 .probe
= au_ide_probe
,
791 .remove
= au_ide_remove
,
794 static int __init
au_ide_init(void)
796 return driver_register(&au1200_ide_driver
);
799 static void __exit
au_ide_exit(void)
801 driver_unregister(&au1200_ide_driver
);
804 MODULE_LICENSE("GPL");
805 MODULE_DESCRIPTION("AU1200 IDE driver");
807 module_init(au_ide_init
);
808 module_exit(au_ide_exit
);