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Linux-2.6.12-rc2
[mirror_ubuntu-artful-kernel.git] / drivers / ide / pci / alim15x3.c
1 /*
2 * linux/drivers/ide/pci/alim15x3.c Version 0.17 2003/01/02
3 *
4 * Copyright (C) 1998-2000 Michel Aubry, Maintainer
5 * Copyright (C) 1998-2000 Andrzej Krzysztofowicz, Maintainer
6 * Copyright (C) 1999-2000 CJ, cjtsai@ali.com.tw, Maintainer
7 *
8 * Copyright (C) 1998-2000 Andre Hedrick (andre@linux-ide.org)
9 * May be copied or modified under the terms of the GNU General Public License
10 * Copyright (C) 2002 Alan Cox <alan@redhat.com>
11 * ALi (now ULi M5228) support by Clear Zhang <Clear.Zhang@ali.com.tw>
12 *
13 * (U)DMA capable version of ali 1533/1543(C), 1535(D)
14 *
15 **********************************************************************
16 * 9/7/99 --Parts from the above author are included and need to be
17 * converted into standard interface, once I finish the thought.
18 *
19 * Recent changes
20 * Don't use LBA48 mode on ALi <= 0xC4
21 * Don't poke 0x79 with a non ALi northbridge
22 * Don't flip undefined bits on newer chipsets (fix Fujitsu laptop hang)
23 * Allow UDMA6 on revisions > 0xC4
24 *
25 * Documentation
26 * Chipset documentation available under NDA only
27 *
28 */
29
30 #include <linux/config.h>
31 #include <linux/module.h>
32 #include <linux/types.h>
33 #include <linux/kernel.h>
34 #include <linux/pci.h>
35 #include <linux/delay.h>
36 #include <linux/hdreg.h>
37 #include <linux/ide.h>
38 #include <linux/init.h>
39
40 #include <asm/io.h>
41
42 #define DISPLAY_ALI_TIMINGS
43
44 /*
45 * ALi devices are not plug in. Otherwise these static values would
46 * need to go. They ought to go away anyway
47 */
48
49 static u8 m5229_revision;
50 static u8 chip_is_1543c_e;
51 static struct pci_dev *isa_dev;
52
53 #if defined(DISPLAY_ALI_TIMINGS) && defined(CONFIG_PROC_FS)
54 #include <linux/stat.h>
55 #include <linux/proc_fs.h>
56
57 static u8 ali_proc = 0;
58
59 static struct pci_dev *bmide_dev;
60
61 static char *fifo[4] = {
62 "FIFO Off",
63 "FIFO On ",
64 "DMA mode",
65 "PIO mode" };
66
67 static char *udmaT[8] = {
68 "1.5T",
69 " 2T",
70 "2.5T",
71 " 3T",
72 "3.5T",
73 " 4T",
74 " 6T",
75 " 8T"
76 };
77
78 static char *channel_status[8] = {
79 "OK ",
80 "busy ",
81 "DRQ ",
82 "DRQ busy ",
83 "error ",
84 "error busy ",
85 "error DRQ ",
86 "error DRQ busy"
87 };
88
89 /**
90 * ali_get_info - generate proc file for ALi IDE
91 * @buffer: buffer to fill
92 * @addr: address of user start in buffer
93 * @offset: offset into 'file'
94 * @count: buffer count
95 *
96 * Walks the Ali devices and outputs summary data on the tuning and
97 * anything else that will help with debugging
98 */
99
100 static int ali_get_info (char *buffer, char **addr, off_t offset, int count)
101 {
102 unsigned long bibma;
103 u8 reg53h, reg5xh, reg5yh, reg5xh1, reg5yh1, c0, c1, rev, tmp;
104 char *q, *p = buffer;
105
106 /* fetch rev. */
107 pci_read_config_byte(bmide_dev, 0x08, &rev);
108 if (rev >= 0xc1) /* M1543C or newer */
109 udmaT[7] = " ???";
110 else
111 fifo[3] = " ??? ";
112
113 /* first fetch bibma: */
114
115 bibma = pci_resource_start(bmide_dev, 4);
116
117 /*
118 * at that point bibma+0x2 et bibma+0xa are byte
119 * registers to investigate:
120 */
121 c0 = inb(bibma + 0x02);
122 c1 = inb(bibma + 0x0a);
123
124 p += sprintf(p,
125 "\n Ali M15x3 Chipset.\n");
126 p += sprintf(p,
127 " ------------------\n");
128 pci_read_config_byte(bmide_dev, 0x78, &reg53h);
129 p += sprintf(p, "PCI Clock: %d.\n", reg53h);
130
131 pci_read_config_byte(bmide_dev, 0x53, &reg53h);
132 p += sprintf(p,
133 "CD_ROM FIFO:%s, CD_ROM DMA:%s\n",
134 (reg53h & 0x02) ? "Yes" : "No ",
135 (reg53h & 0x01) ? "Yes" : "No " );
136 pci_read_config_byte(bmide_dev, 0x74, &reg53h);
137 p += sprintf(p,
138 "FIFO Status: contains %d Words, runs%s%s\n\n",
139 (reg53h & 0x3f),
140 (reg53h & 0x40) ? " OVERWR" : "",
141 (reg53h & 0x80) ? " OVERRD." : "." );
142
143 p += sprintf(p,
144 "-------------------primary channel"
145 "-------------------secondary channel"
146 "---------\n\n");
147
148 pci_read_config_byte(bmide_dev, 0x09, &reg53h);
149 p += sprintf(p,
150 "channel status: %s"
151 " %s\n",
152 (reg53h & 0x20) ? "On " : "Off",
153 (reg53h & 0x10) ? "On " : "Off" );
154
155 p += sprintf(p,
156 "both channels togth: %s"
157 " %s\n",
158 (c0&0x80) ? "No " : "Yes",
159 (c1&0x80) ? "No " : "Yes" );
160
161 pci_read_config_byte(bmide_dev, 0x76, &reg53h);
162 p += sprintf(p,
163 "Channel state: %s %s\n",
164 channel_status[reg53h & 0x07],
165 channel_status[(reg53h & 0x70) >> 4] );
166
167 pci_read_config_byte(bmide_dev, 0x58, &reg5xh);
168 pci_read_config_byte(bmide_dev, 0x5c, &reg5yh);
169 p += sprintf(p,
170 "Add. Setup Timing: %dT"
171 " %dT\n",
172 (reg5xh & 0x07) ? (reg5xh & 0x07) : 8,
173 (reg5yh & 0x07) ? (reg5yh & 0x07) : 8 );
174
175 pci_read_config_byte(bmide_dev, 0x59, &reg5xh);
176 pci_read_config_byte(bmide_dev, 0x5d, &reg5yh);
177 p += sprintf(p,
178 "Command Act. Count: %dT"
179 " %dT\n"
180 "Command Rec. Count: %dT"
181 " %dT\n\n",
182 (reg5xh & 0x70) ? ((reg5xh & 0x70) >> 4) : 8,
183 (reg5yh & 0x70) ? ((reg5yh & 0x70) >> 4) : 8,
184 (reg5xh & 0x0f) ? (reg5xh & 0x0f) : 16,
185 (reg5yh & 0x0f) ? (reg5yh & 0x0f) : 16 );
186
187 p += sprintf(p,
188 "----------------drive0-----------drive1"
189 "------------drive0-----------drive1------\n\n");
190 p += sprintf(p,
191 "DMA enabled: %s %s"
192 " %s %s\n",
193 (c0&0x20) ? "Yes" : "No ",
194 (c0&0x40) ? "Yes" : "No ",
195 (c1&0x20) ? "Yes" : "No ",
196 (c1&0x40) ? "Yes" : "No " );
197
198 pci_read_config_byte(bmide_dev, 0x54, &reg5xh);
199 pci_read_config_byte(bmide_dev, 0x55, &reg5yh);
200 q = "FIFO threshold: %2d Words %2d Words"
201 " %2d Words %2d Words\n";
202 if (rev < 0xc1) {
203 if ((rev == 0x20) &&
204 (pci_read_config_byte(bmide_dev, 0x4f, &tmp), (tmp &= 0x20))) {
205 p += sprintf(p, q, 8, 8, 8, 8);
206 } else {
207 p += sprintf(p, q,
208 (reg5xh & 0x03) + 12,
209 ((reg5xh & 0x30)>>4) + 12,
210 (reg5yh & 0x03) + 12,
211 ((reg5yh & 0x30)>>4) + 12 );
212 }
213 } else {
214 int t1 = (tmp = (reg5xh & 0x03)) ? (tmp << 3) : 4;
215 int t2 = (tmp = ((reg5xh & 0x30)>>4)) ? (tmp << 3) : 4;
216 int t3 = (tmp = (reg5yh & 0x03)) ? (tmp << 3) : 4;
217 int t4 = (tmp = ((reg5yh & 0x30)>>4)) ? (tmp << 3) : 4;
218 p += sprintf(p, q, t1, t2, t3, t4);
219 }
220
221 #if 0
222 p += sprintf(p,
223 "FIFO threshold: %2d Words %2d Words"
224 " %2d Words %2d Words\n",
225 (reg5xh & 0x03) + 12,
226 ((reg5xh & 0x30)>>4) + 12,
227 (reg5yh & 0x03) + 12,
228 ((reg5yh & 0x30)>>4) + 12 );
229 #endif
230
231 p += sprintf(p,
232 "FIFO mode: %s %s %s %s\n",
233 fifo[((reg5xh & 0x0c) >> 2)],
234 fifo[((reg5xh & 0xc0) >> 6)],
235 fifo[((reg5yh & 0x0c) >> 2)],
236 fifo[((reg5yh & 0xc0) >> 6)] );
237
238 pci_read_config_byte(bmide_dev, 0x5a, &reg5xh);
239 pci_read_config_byte(bmide_dev, 0x5b, &reg5xh1);
240 pci_read_config_byte(bmide_dev, 0x5e, &reg5yh);
241 pci_read_config_byte(bmide_dev, 0x5f, &reg5yh1);
242
243 p += sprintf(p,/*
244 "------------------drive0-----------drive1"
245 "------------drive0-----------drive1------\n")*/
246 "Dt RW act. Cnt %2dT %2dT"
247 " %2dT %2dT\n"
248 "Dt RW rec. Cnt %2dT %2dT"
249 " %2dT %2dT\n\n",
250 (reg5xh & 0x70) ? ((reg5xh & 0x70) >> 4) : 8,
251 (reg5xh1 & 0x70) ? ((reg5xh1 & 0x70) >> 4) : 8,
252 (reg5yh & 0x70) ? ((reg5yh & 0x70) >> 4) : 8,
253 (reg5yh1 & 0x70) ? ((reg5yh1 & 0x70) >> 4) : 8,
254 (reg5xh & 0x0f) ? (reg5xh & 0x0f) : 16,
255 (reg5xh1 & 0x0f) ? (reg5xh1 & 0x0f) : 16,
256 (reg5yh & 0x0f) ? (reg5yh & 0x0f) : 16,
257 (reg5yh1 & 0x0f) ? (reg5yh1 & 0x0f) : 16 );
258
259 p += sprintf(p,
260 "-----------------------------------UDMA Timings"
261 "--------------------------------\n\n");
262
263 pci_read_config_byte(bmide_dev, 0x56, &reg5xh);
264 pci_read_config_byte(bmide_dev, 0x57, &reg5yh);
265 p += sprintf(p,
266 "UDMA: %s %s"
267 " %s %s\n"
268 "UDMA timings: %s %s"
269 " %s %s\n\n",
270 (reg5xh & 0x08) ? "OK" : "No",
271 (reg5xh & 0x80) ? "OK" : "No",
272 (reg5yh & 0x08) ? "OK" : "No",
273 (reg5yh & 0x80) ? "OK" : "No",
274 udmaT[(reg5xh & 0x07)],
275 udmaT[(reg5xh & 0x70) >> 4],
276 udmaT[reg5yh & 0x07],
277 udmaT[(reg5yh & 0x70) >> 4] );
278
279 return p-buffer; /* => must be less than 4k! */
280 }
281 #endif /* defined(DISPLAY_ALI_TIMINGS) && defined(CONFIG_PROC_FS) */
282
283 /**
284 * ali15x3_tune_drive - set up a drive
285 * @drive: drive to tune
286 * @pio: unused
287 *
288 * Select the best PIO timing for the drive in question. Then
289 * program the controller for this drive set up
290 */
291
292 static void ali15x3_tune_drive (ide_drive_t *drive, u8 pio)
293 {
294 ide_pio_data_t d;
295 ide_hwif_t *hwif = HWIF(drive);
296 struct pci_dev *dev = hwif->pci_dev;
297 int s_time, a_time, c_time;
298 u8 s_clc, a_clc, r_clc;
299 unsigned long flags;
300 int bus_speed = system_bus_clock();
301 int port = hwif->channel ? 0x5c : 0x58;
302 int portFIFO = hwif->channel ? 0x55 : 0x54;
303 u8 cd_dma_fifo = 0;
304 int unit = drive->select.b.unit & 1;
305
306 pio = ide_get_best_pio_mode(drive, pio, 5, &d);
307 s_time = ide_pio_timings[pio].setup_time;
308 a_time = ide_pio_timings[pio].active_time;
309 if ((s_clc = (s_time * bus_speed + 999) / 1000) >= 8)
310 s_clc = 0;
311 if ((a_clc = (a_time * bus_speed + 999) / 1000) >= 8)
312 a_clc = 0;
313 c_time = ide_pio_timings[pio].cycle_time;
314
315 #if 0
316 if ((r_clc = ((c_time - s_time - a_time) * bus_speed + 999) / 1000) >= 16)
317 r_clc = 0;
318 #endif
319
320 if (!(r_clc = (c_time * bus_speed + 999) / 1000 - a_clc - s_clc)) {
321 r_clc = 1;
322 } else {
323 if (r_clc >= 16)
324 r_clc = 0;
325 }
326 local_irq_save(flags);
327
328 /*
329 * PIO mode => ATA FIFO on, ATAPI FIFO off
330 */
331 pci_read_config_byte(dev, portFIFO, &cd_dma_fifo);
332 if (drive->media==ide_disk) {
333 if (unit) {
334 pci_write_config_byte(dev, portFIFO, (cd_dma_fifo & 0x0F) | 0x50);
335 } else {
336 pci_write_config_byte(dev, portFIFO, (cd_dma_fifo & 0xF0) | 0x05);
337 }
338 } else {
339 if (unit) {
340 pci_write_config_byte(dev, portFIFO, cd_dma_fifo & 0x0F);
341 } else {
342 pci_write_config_byte(dev, portFIFO, cd_dma_fifo & 0xF0);
343 }
344 }
345
346 pci_write_config_byte(dev, port, s_clc);
347 pci_write_config_byte(dev, port+drive->select.b.unit+2, (a_clc << 4) | r_clc);
348 local_irq_restore(flags);
349
350 /*
351 * setup active rec
352 * { 70, 165, 365 }, PIO Mode 0
353 * { 50, 125, 208 }, PIO Mode 1
354 * { 30, 100, 110 }, PIO Mode 2
355 * { 30, 80, 70 }, PIO Mode 3 with IORDY
356 * { 25, 70, 25 }, PIO Mode 4 with IORDY ns
357 * { 20, 50, 30 } PIO Mode 5 with IORDY (nonstandard)
358 */
359
360 }
361
362 /**
363 * ali15x3_can_ultra - check for ultra DMA support
364 * @drive: drive to do the check
365 *
366 * Check the drive and controller revisions. Return 0 if UDMA is
367 * not available, or 1 if UDMA can be used. The actual rules for
368 * the ALi are
369 * No UDMA on revisions <= 0x20
370 * Disk only for revisions < 0xC2
371 * Not WDC drives for revisions < 0xC2
372 *
373 * FIXME: WDC ifdef needs to die
374 */
375
376 static u8 ali15x3_can_ultra (ide_drive_t *drive)
377 {
378 #ifndef CONFIG_WDC_ALI15X3
379 struct hd_driveid *id = drive->id;
380 #endif /* CONFIG_WDC_ALI15X3 */
381
382 if (m5229_revision <= 0x20) {
383 return 0;
384 } else if ((m5229_revision < 0xC2) &&
385 #ifndef CONFIG_WDC_ALI15X3
386 ((chip_is_1543c_e && strstr(id->model, "WDC ")) ||
387 (drive->media!=ide_disk))) {
388 #else /* CONFIG_WDC_ALI15X3 */
389 (drive->media!=ide_disk)) {
390 #endif /* CONFIG_WDC_ALI15X3 */
391 return 0;
392 } else {
393 return 1;
394 }
395 }
396
397 /**
398 * ali15x3_ratemask - generate DMA mode list
399 * @drive: drive to compute against
400 *
401 * Generate a list of the available DMA modes for the drive.
402 * FIXME: this function contains lots of bogus masking we can dump
403 *
404 * Return the highest available mode (UDMA33, UDMA66, UDMA100,..)
405 */
406
407 static u8 ali15x3_ratemask (ide_drive_t *drive)
408 {
409 u8 mode = 0, can_ultra = ali15x3_can_ultra(drive);
410
411 if (m5229_revision > 0xC4 && can_ultra) {
412 mode = 4;
413 } else if (m5229_revision == 0xC4 && can_ultra) {
414 mode = 3;
415 } else if (m5229_revision >= 0xC2 && can_ultra) {
416 mode = 2;
417 } else if (can_ultra) {
418 return 1;
419 } else {
420 return 0;
421 }
422
423 /*
424 * If the drive sees no suitable cable then UDMA 33
425 * is the highest permitted mode
426 */
427
428 if (!eighty_ninty_three(drive))
429 mode = min(mode, (u8)1);
430 return mode;
431 }
432
433 /**
434 * ali15x3_tune_chipset - set up chiset for new speed
435 * @drive: drive to configure for
436 * @xferspeed: desired speed
437 *
438 * Configure the hardware for the desired IDE transfer mode.
439 * We also do the needed drive configuration through helpers
440 */
441
442 static int ali15x3_tune_chipset (ide_drive_t *drive, u8 xferspeed)
443 {
444 ide_hwif_t *hwif = HWIF(drive);
445 struct pci_dev *dev = hwif->pci_dev;
446 u8 speed = ide_rate_filter(ali15x3_ratemask(drive), xferspeed);
447 u8 speed1 = speed;
448 u8 unit = (drive->select.b.unit & 0x01);
449 u8 tmpbyte = 0x00;
450 int m5229_udma = (hwif->channel) ? 0x57 : 0x56;
451
452 if (speed == XFER_UDMA_6)
453 speed1 = 0x47;
454
455 if (speed < XFER_UDMA_0) {
456 u8 ultra_enable = (unit) ? 0x7f : 0xf7;
457 /*
458 * clear "ultra enable" bit
459 */
460 pci_read_config_byte(dev, m5229_udma, &tmpbyte);
461 tmpbyte &= ultra_enable;
462 pci_write_config_byte(dev, m5229_udma, tmpbyte);
463
464 if (speed < XFER_SW_DMA_0)
465 ali15x3_tune_drive(drive, speed);
466 } else {
467 pci_read_config_byte(dev, m5229_udma, &tmpbyte);
468 tmpbyte &= (0x0f << ((1-unit) << 2));
469 /*
470 * enable ultra dma and set timing
471 */
472 tmpbyte |= ((0x08 | ((4-speed1)&0x07)) << (unit << 2));
473 pci_write_config_byte(dev, m5229_udma, tmpbyte);
474 if (speed >= XFER_UDMA_3) {
475 pci_read_config_byte(dev, 0x4b, &tmpbyte);
476 tmpbyte |= 1;
477 pci_write_config_byte(dev, 0x4b, tmpbyte);
478 }
479 }
480 return (ide_config_drive_speed(drive, speed));
481 }
482
483
484 /**
485 * config_chipset_for_dma - set up DMA mode
486 * @drive: drive to configure for
487 *
488 * Place a drive into DMA mode and tune the chipset for
489 * the selected speed.
490 *
491 * Returns true if DMA mode can be used
492 */
493
494 static int config_chipset_for_dma (ide_drive_t *drive)
495 {
496 u8 speed = ide_dma_speed(drive, ali15x3_ratemask(drive));
497
498 if (!(speed))
499 return 0;
500
501 (void) ali15x3_tune_chipset(drive, speed);
502 return ide_dma_enable(drive);
503 }
504
505 /**
506 * ali15x3_config_drive_for_dma - configure for DMA
507 * @drive: drive to configure
508 *
509 * Configure a drive for DMA operation. If DMA is not possible we
510 * drop the drive into PIO mode instead.
511 *
512 * FIXME: exactly what are we trying to return here
513 */
514
515 static int ali15x3_config_drive_for_dma(ide_drive_t *drive)
516 {
517 ide_hwif_t *hwif = HWIF(drive);
518 struct hd_driveid *id = drive->id;
519
520 if ((m5229_revision<=0x20) && (drive->media!=ide_disk))
521 return hwif->ide_dma_off_quietly(drive);
522
523 drive->init_speed = 0;
524
525 if ((id != NULL) && ((id->capability & 1) != 0) && drive->autodma) {
526 /* Consult the list of known "bad" drives */
527 if (__ide_dma_bad_drive(drive))
528 goto ata_pio;
529 if ((id->field_valid & 4) && (m5229_revision >= 0xC2)) {
530 if (id->dma_ultra & hwif->ultra_mask) {
531 /* Force if Capable UltraDMA */
532 int dma = config_chipset_for_dma(drive);
533 if ((id->field_valid & 2) && !dma)
534 goto try_dma_modes;
535 }
536 } else if (id->field_valid & 2) {
537 try_dma_modes:
538 if ((id->dma_mword & hwif->mwdma_mask) ||
539 (id->dma_1word & hwif->swdma_mask)) {
540 /* Force if Capable regular DMA modes */
541 if (!config_chipset_for_dma(drive))
542 goto no_dma_set;
543 }
544 } else if (__ide_dma_good_drive(drive) &&
545 (id->eide_dma_time < 150)) {
546 /* Consult the list of known "good" drives */
547 if (!config_chipset_for_dma(drive))
548 goto no_dma_set;
549 } else {
550 goto ata_pio;
551 }
552 } else {
553 ata_pio:
554 hwif->tuneproc(drive, 255);
555 no_dma_set:
556 return hwif->ide_dma_off_quietly(drive);
557 }
558 return hwif->ide_dma_on(drive);
559 }
560
561 /**
562 * ali15x3_dma_setup - begin a DMA phase
563 * @drive: target device
564 *
565 * Returns 1 if the DMA cannot be performed, zero on success.
566 */
567
568 static int ali15x3_dma_setup(ide_drive_t *drive)
569 {
570 if (m5229_revision < 0xC2 && drive->media != ide_disk) {
571 if (rq_data_dir(drive->hwif->hwgroup->rq))
572 return 1; /* try PIO instead of DMA */
573 }
574 return ide_dma_setup(drive);
575 }
576
577 /**
578 * init_chipset_ali15x3 - Initialise an ALi IDE controller
579 * @dev: PCI device
580 * @name: Name of the controller
581 *
582 * This function initializes the ALI IDE controller and where
583 * appropriate also sets up the 1533 southbridge.
584 */
585
586 static unsigned int __init init_chipset_ali15x3 (struct pci_dev *dev, const char *name)
587 {
588 unsigned long flags;
589 u8 tmpbyte;
590 struct pci_dev *north = pci_find_slot(0, PCI_DEVFN(0,0));
591
592 pci_read_config_byte(dev, PCI_REVISION_ID, &m5229_revision);
593
594 isa_dev = pci_find_device(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533, NULL);
595
596 #if defined(DISPLAY_ALI_TIMINGS) && defined(CONFIG_PROC_FS)
597 if (!ali_proc) {
598 ali_proc = 1;
599 bmide_dev = dev;
600 ide_pci_create_host_proc("ali", ali_get_info);
601 }
602 #endif /* defined(DISPLAY_ALI_TIMINGS) && defined(CONFIG_PROC_FS) */
603
604 local_irq_save(flags);
605
606 if (m5229_revision < 0xC2) {
607 /*
608 * revision 0x20 (1543-E, 1543-F)
609 * revision 0xC0, 0xC1 (1543C-C, 1543C-D, 1543C-E)
610 * clear CD-ROM DMA write bit, m5229, 0x4b, bit 7
611 */
612 pci_read_config_byte(dev, 0x4b, &tmpbyte);
613 /*
614 * clear bit 7
615 */
616 pci_write_config_byte(dev, 0x4b, tmpbyte & 0x7F);
617 local_irq_restore(flags);
618 return 0;
619 }
620
621 /*
622 * 1543C-B?, 1535, 1535D, 1553
623 * Note 1: not all "motherboard" support this detection
624 * Note 2: if no udma 66 device, the detection may "error".
625 * but in this case, we will not set the device to
626 * ultra 66, the detection result is not important
627 */
628
629 /*
630 * enable "Cable Detection", m5229, 0x4b, bit3
631 */
632 pci_read_config_byte(dev, 0x4b, &tmpbyte);
633 pci_write_config_byte(dev, 0x4b, tmpbyte | 0x08);
634
635 /*
636 * We should only tune the 1533 enable if we are using an ALi
637 * North bridge. We might have no north found on some zany
638 * box without a device at 0:0.0. The ALi bridge will be at
639 * 0:0.0 so if we didn't find one we know what is cooking.
640 */
641 if (north && north->vendor != PCI_VENDOR_ID_AL) {
642 local_irq_restore(flags);
643 return 0;
644 }
645
646 if (m5229_revision < 0xC5 && isa_dev)
647 {
648 /*
649 * set south-bridge's enable bit, m1533, 0x79
650 */
651
652 pci_read_config_byte(isa_dev, 0x79, &tmpbyte);
653 if (m5229_revision == 0xC2) {
654 /*
655 * 1543C-B0 (m1533, 0x79, bit 2)
656 */
657 pci_write_config_byte(isa_dev, 0x79, tmpbyte | 0x04);
658 } else if (m5229_revision >= 0xC3) {
659 /*
660 * 1553/1535 (m1533, 0x79, bit 1)
661 */
662 pci_write_config_byte(isa_dev, 0x79, tmpbyte | 0x02);
663 }
664 }
665 local_irq_restore(flags);
666 return 0;
667 }
668
669 /**
670 * ata66_ali15x3 - check for UDMA 66 support
671 * @hwif: IDE interface
672 *
673 * This checks if the controller and the cable are capable
674 * of UDMA66 transfers. It doesn't check the drives.
675 * But see note 2 below!
676 *
677 * FIXME: frobs bits that are not defined on newer ALi devicea
678 */
679
680 static unsigned int __init ata66_ali15x3 (ide_hwif_t *hwif)
681 {
682 struct pci_dev *dev = hwif->pci_dev;
683 unsigned int ata66 = 0;
684 u8 cable_80_pin[2] = { 0, 0 };
685
686 unsigned long flags;
687 u8 tmpbyte;
688
689 local_irq_save(flags);
690
691 if (m5229_revision >= 0xC2) {
692 /*
693 * Ultra66 cable detection (from Host View)
694 * m5229, 0x4a, bit0: primary, bit1: secondary 80 pin
695 */
696 pci_read_config_byte(dev, 0x4a, &tmpbyte);
697 /*
698 * 0x4a, bit0 is 0 => primary channel
699 * has 80-pin (from host view)
700 */
701 if (!(tmpbyte & 0x01)) cable_80_pin[0] = 1;
702 /*
703 * 0x4a, bit1 is 0 => secondary channel
704 * has 80-pin (from host view)
705 */
706 if (!(tmpbyte & 0x02)) cable_80_pin[1] = 1;
707 /*
708 * Allow ata66 if cable of current channel has 80 pins
709 */
710 ata66 = (hwif->channel)?cable_80_pin[1]:cable_80_pin[0];
711 } else {
712 /*
713 * check m1533, 0x5e, bit 1~4 == 1001 => & 00011110 = 00010010
714 */
715 pci_read_config_byte(isa_dev, 0x5e, &tmpbyte);
716 chip_is_1543c_e = ((tmpbyte & 0x1e) == 0x12) ? 1: 0;
717 }
718
719 /*
720 * CD_ROM DMA on (m5229, 0x53, bit0)
721 * Enable this bit even if we want to use PIO
722 * PIO FIFO off (m5229, 0x53, bit1)
723 * The hardware will use 0x54h and 0x55h to control PIO FIFO
724 * (Not on later devices it seems)
725 *
726 * 0x53 changes meaning on later revs - we must no touch
727 * bit 1 on them. Need to check if 0x20 is the right break
728 */
729
730 pci_read_config_byte(dev, 0x53, &tmpbyte);
731
732 if(m5229_revision <= 0x20)
733 tmpbyte = (tmpbyte & (~0x02)) | 0x01;
734 else
735 tmpbyte |= 0x01;
736
737 pci_write_config_byte(dev, 0x53, tmpbyte);
738
739 local_irq_restore(flags);
740
741 return(ata66);
742 }
743
744 /**
745 * init_hwif_common_ali15x3 - Set up ALI IDE hardware
746 * @hwif: IDE interface
747 *
748 * Initialize the IDE structure side of the ALi 15x3 driver.
749 */
750
751 static void __init init_hwif_common_ali15x3 (ide_hwif_t *hwif)
752 {
753 hwif->autodma = 0;
754 hwif->tuneproc = &ali15x3_tune_drive;
755 hwif->speedproc = &ali15x3_tune_chipset;
756
757 /* don't use LBA48 DMA on ALi devices before rev 0xC5 */
758 hwif->no_lba48_dma = (m5229_revision <= 0xC4) ? 1 : 0;
759
760 if (!hwif->dma_base) {
761 hwif->drives[0].autotune = 1;
762 hwif->drives[1].autotune = 1;
763 return;
764 }
765
766 hwif->atapi_dma = 1;
767
768 if (m5229_revision > 0x20)
769 hwif->ultra_mask = 0x7f;
770 hwif->mwdma_mask = 0x07;
771 hwif->swdma_mask = 0x07;
772
773 if (m5229_revision >= 0x20) {
774 /*
775 * M1543C or newer for DMAing
776 */
777 hwif->ide_dma_check = &ali15x3_config_drive_for_dma;
778 hwif->dma_setup = &ali15x3_dma_setup;
779 if (!noautodma)
780 hwif->autodma = 1;
781 if (!(hwif->udma_four))
782 hwif->udma_four = ata66_ali15x3(hwif);
783 }
784 hwif->drives[0].autodma = hwif->autodma;
785 hwif->drives[1].autodma = hwif->autodma;
786 }
787
788 /**
789 * init_hwif_ali15x3 - Initialize the ALI IDE x86 stuff
790 * @hwif: interface to configure
791 *
792 * Obtain the IRQ tables for an ALi based IDE solution on the PC
793 * class platforms. This part of the code isn't applicable to the
794 * Sparc systems
795 */
796
797 static void __init init_hwif_ali15x3 (ide_hwif_t *hwif)
798 {
799 u8 ideic, inmir;
800 s8 irq_routing_table[] = { -1, 9, 3, 10, 4, 5, 7, 6,
801 1, 11, 0, 12, 0, 14, 0, 15 };
802 int irq = -1;
803
804 if (hwif->pci_dev->device == PCI_DEVICE_ID_AL_M5229)
805 hwif->irq = hwif->channel ? 15 : 14;
806
807 if (isa_dev) {
808 /*
809 * read IDE interface control
810 */
811 pci_read_config_byte(isa_dev, 0x58, &ideic);
812
813 /* bit0, bit1 */
814 ideic = ideic & 0x03;
815
816 /* get IRQ for IDE Controller */
817 if ((hwif->channel && ideic == 0x03) ||
818 (!hwif->channel && !ideic)) {
819 /*
820 * get SIRQ1 routing table
821 */
822 pci_read_config_byte(isa_dev, 0x44, &inmir);
823 inmir = inmir & 0x0f;
824 irq = irq_routing_table[inmir];
825 } else if (hwif->channel && !(ideic & 0x01)) {
826 /*
827 * get SIRQ2 routing table
828 */
829 pci_read_config_byte(isa_dev, 0x75, &inmir);
830 inmir = inmir & 0x0f;
831 irq = irq_routing_table[inmir];
832 }
833 if(irq >= 0)
834 hwif->irq = irq;
835 }
836
837 init_hwif_common_ali15x3(hwif);
838 }
839
840 /**
841 * init_dma_ali15x3 - set up DMA on ALi15x3
842 * @hwif: IDE interface
843 * @dmabase: DMA interface base PCI address
844 *
845 * Set up the DMA functionality on the ALi 15x3. For the ALi
846 * controllers this is generic so we can let the generic code do
847 * the actual work.
848 */
849
850 static void __init init_dma_ali15x3 (ide_hwif_t *hwif, unsigned long dmabase)
851 {
852 if (m5229_revision < 0x20)
853 return;
854 if (!(hwif->channel))
855 hwif->OUTB(hwif->INB(dmabase+2) & 0x60, dmabase+2);
856 ide_setup_dma(hwif, dmabase, 8);
857 }
858
859 static ide_pci_device_t ali15x3_chipset __devinitdata = {
860 .name = "ALI15X3",
861 .init_chipset = init_chipset_ali15x3,
862 .init_hwif = init_hwif_ali15x3,
863 .init_dma = init_dma_ali15x3,
864 .channels = 2,
865 .autodma = AUTODMA,
866 .bootable = ON_BOARD,
867 };
868
869 /**
870 * alim15x3_init_one - set up an ALi15x3 IDE controller
871 * @dev: PCI device to set up
872 *
873 * Perform the actual set up for an ALi15x3 that has been found by the
874 * hot plug layer.
875 */
876
877 static int __devinit alim15x3_init_one(struct pci_dev *dev, const struct pci_device_id *id)
878 {
879 ide_pci_device_t *d = &ali15x3_chipset;
880
881 if(pci_find_device(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS100, NULL))
882 printk(KERN_ERR "Warning: ATI Radeon IGP Northbridge is not yet fully tested.\n");
883
884 #if defined(CONFIG_SPARC64)
885 d->init_hwif = init_hwif_common_ali15x3;
886 #endif /* CONFIG_SPARC64 */
887 return ide_setup_pci_device(dev, d);
888 }
889
890
891 static struct pci_device_id alim15x3_pci_tbl[] = {
892 { PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M5229, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
893 { PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M5228, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
894 { 0, },
895 };
896 MODULE_DEVICE_TABLE(pci, alim15x3_pci_tbl);
897
898 static struct pci_driver driver = {
899 .name = "ALI15x3_IDE",
900 .id_table = alim15x3_pci_tbl,
901 .probe = alim15x3_init_one,
902 };
903
904 static int ali15x3_ide_init(void)
905 {
906 return ide_pci_register_driver(&driver);
907 }
908
909 module_init(ali15x3_ide_init);
910
911 MODULE_AUTHOR("Michael Aubry, Andrzej Krzysztofowicz, CJ, Andre Hedrick, Alan Cox");
912 MODULE_DESCRIPTION("PCI driver module for ALi 15x3 IDE");
913 MODULE_LICENSE("GPL");
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