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ide: move ide_config_drive_speed() calls to upper layers (take 2)
[mirror_ubuntu-artful-kernel.git] / drivers / ide / pci / alim15x3.c
1 /*
2 * linux/drivers/ide/pci/alim15x3.c Version 0.26 Jul 14 2007
3 *
4 * Copyright (C) 1998-2000 Michel Aubry, Maintainer
5 * Copyright (C) 1998-2000 Andrzej Krzysztofowicz, Maintainer
6 * Copyright (C) 1999-2000 CJ, cjtsai@ali.com.tw, Maintainer
7 *
8 * Copyright (C) 1998-2000 Andre Hedrick (andre@linux-ide.org)
9 * May be copied or modified under the terms of the GNU General Public License
10 * Copyright (C) 2002 Alan Cox <alan@redhat.com>
11 * ALi (now ULi M5228) support by Clear Zhang <Clear.Zhang@ali.com.tw>
12 * Copyright (C) 2007 MontaVista Software, Inc. <source@mvista.com>
13 * Copyright (C) 2007 Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
14 *
15 * (U)DMA capable version of ali 1533/1543(C), 1535(D)
16 *
17 **********************************************************************
18 * 9/7/99 --Parts from the above author are included and need to be
19 * converted into standard interface, once I finish the thought.
20 *
21 * Recent changes
22 * Don't use LBA48 mode on ALi <= 0xC4
23 * Don't poke 0x79 with a non ALi northbridge
24 * Don't flip undefined bits on newer chipsets (fix Fujitsu laptop hang)
25 * Allow UDMA6 on revisions > 0xC4
26 *
27 * Documentation
28 * Chipset documentation available under NDA only
29 *
30 */
31
32 #include <linux/module.h>
33 #include <linux/types.h>
34 #include <linux/kernel.h>
35 #include <linux/pci.h>
36 #include <linux/delay.h>
37 #include <linux/hdreg.h>
38 #include <linux/ide.h>
39 #include <linux/init.h>
40 #include <linux/dmi.h>
41
42 #include <asm/io.h>
43
44 #define DISPLAY_ALI_TIMINGS
45
46 /*
47 * ALi devices are not plug in. Otherwise these static values would
48 * need to go. They ought to go away anyway
49 */
50
51 static u8 m5229_revision;
52 static u8 chip_is_1543c_e;
53 static struct pci_dev *isa_dev;
54
55 #if defined(DISPLAY_ALI_TIMINGS) && defined(CONFIG_IDE_PROC_FS)
56 #include <linux/stat.h>
57 #include <linux/proc_fs.h>
58
59 static u8 ali_proc = 0;
60
61 static struct pci_dev *bmide_dev;
62
63 static char *fifo[4] = {
64 "FIFO Off",
65 "FIFO On ",
66 "DMA mode",
67 "PIO mode" };
68
69 static char *udmaT[8] = {
70 "1.5T",
71 " 2T",
72 "2.5T",
73 " 3T",
74 "3.5T",
75 " 4T",
76 " 6T",
77 " 8T"
78 };
79
80 static char *channel_status[8] = {
81 "OK ",
82 "busy ",
83 "DRQ ",
84 "DRQ busy ",
85 "error ",
86 "error busy ",
87 "error DRQ ",
88 "error DRQ busy"
89 };
90
91 /**
92 * ali_get_info - generate proc file for ALi IDE
93 * @buffer: buffer to fill
94 * @addr: address of user start in buffer
95 * @offset: offset into 'file'
96 * @count: buffer count
97 *
98 * Walks the Ali devices and outputs summary data on the tuning and
99 * anything else that will help with debugging
100 */
101
102 static int ali_get_info (char *buffer, char **addr, off_t offset, int count)
103 {
104 unsigned long bibma;
105 u8 reg53h, reg5xh, reg5yh, reg5xh1, reg5yh1, c0, c1, rev, tmp;
106 char *q, *p = buffer;
107
108 /* fetch rev. */
109 pci_read_config_byte(bmide_dev, 0x08, &rev);
110 if (rev >= 0xc1) /* M1543C or newer */
111 udmaT[7] = " ???";
112 else
113 fifo[3] = " ??? ";
114
115 /* first fetch bibma: */
116
117 bibma = pci_resource_start(bmide_dev, 4);
118
119 /*
120 * at that point bibma+0x2 et bibma+0xa are byte
121 * registers to investigate:
122 */
123 c0 = inb(bibma + 0x02);
124 c1 = inb(bibma + 0x0a);
125
126 p += sprintf(p,
127 "\n Ali M15x3 Chipset.\n");
128 p += sprintf(p,
129 " ------------------\n");
130 pci_read_config_byte(bmide_dev, 0x78, &reg53h);
131 p += sprintf(p, "PCI Clock: %d.\n", reg53h);
132
133 pci_read_config_byte(bmide_dev, 0x53, &reg53h);
134 p += sprintf(p,
135 "CD_ROM FIFO:%s, CD_ROM DMA:%s\n",
136 (reg53h & 0x02) ? "Yes" : "No ",
137 (reg53h & 0x01) ? "Yes" : "No " );
138 pci_read_config_byte(bmide_dev, 0x74, &reg53h);
139 p += sprintf(p,
140 "FIFO Status: contains %d Words, runs%s%s\n\n",
141 (reg53h & 0x3f),
142 (reg53h & 0x40) ? " OVERWR" : "",
143 (reg53h & 0x80) ? " OVERRD." : "." );
144
145 p += sprintf(p,
146 "-------------------primary channel"
147 "-------------------secondary channel"
148 "---------\n\n");
149
150 pci_read_config_byte(bmide_dev, 0x09, &reg53h);
151 p += sprintf(p,
152 "channel status: %s"
153 " %s\n",
154 (reg53h & 0x20) ? "On " : "Off",
155 (reg53h & 0x10) ? "On " : "Off" );
156
157 p += sprintf(p,
158 "both channels togth: %s"
159 " %s\n",
160 (c0&0x80) ? "No " : "Yes",
161 (c1&0x80) ? "No " : "Yes" );
162
163 pci_read_config_byte(bmide_dev, 0x76, &reg53h);
164 p += sprintf(p,
165 "Channel state: %s %s\n",
166 channel_status[reg53h & 0x07],
167 channel_status[(reg53h & 0x70) >> 4] );
168
169 pci_read_config_byte(bmide_dev, 0x58, &reg5xh);
170 pci_read_config_byte(bmide_dev, 0x5c, &reg5yh);
171 p += sprintf(p,
172 "Add. Setup Timing: %dT"
173 " %dT\n",
174 (reg5xh & 0x07) ? (reg5xh & 0x07) : 8,
175 (reg5yh & 0x07) ? (reg5yh & 0x07) : 8 );
176
177 pci_read_config_byte(bmide_dev, 0x59, &reg5xh);
178 pci_read_config_byte(bmide_dev, 0x5d, &reg5yh);
179 p += sprintf(p,
180 "Command Act. Count: %dT"
181 " %dT\n"
182 "Command Rec. Count: %dT"
183 " %dT\n\n",
184 (reg5xh & 0x70) ? ((reg5xh & 0x70) >> 4) : 8,
185 (reg5yh & 0x70) ? ((reg5yh & 0x70) >> 4) : 8,
186 (reg5xh & 0x0f) ? (reg5xh & 0x0f) : 16,
187 (reg5yh & 0x0f) ? (reg5yh & 0x0f) : 16 );
188
189 p += sprintf(p,
190 "----------------drive0-----------drive1"
191 "------------drive0-----------drive1------\n\n");
192 p += sprintf(p,
193 "DMA enabled: %s %s"
194 " %s %s\n",
195 (c0&0x20) ? "Yes" : "No ",
196 (c0&0x40) ? "Yes" : "No ",
197 (c1&0x20) ? "Yes" : "No ",
198 (c1&0x40) ? "Yes" : "No " );
199
200 pci_read_config_byte(bmide_dev, 0x54, &reg5xh);
201 pci_read_config_byte(bmide_dev, 0x55, &reg5yh);
202 q = "FIFO threshold: %2d Words %2d Words"
203 " %2d Words %2d Words\n";
204 if (rev < 0xc1) {
205 if ((rev == 0x20) &&
206 (pci_read_config_byte(bmide_dev, 0x4f, &tmp), (tmp &= 0x20))) {
207 p += sprintf(p, q, 8, 8, 8, 8);
208 } else {
209 p += sprintf(p, q,
210 (reg5xh & 0x03) + 12,
211 ((reg5xh & 0x30)>>4) + 12,
212 (reg5yh & 0x03) + 12,
213 ((reg5yh & 0x30)>>4) + 12 );
214 }
215 } else {
216 int t1 = (tmp = (reg5xh & 0x03)) ? (tmp << 3) : 4;
217 int t2 = (tmp = ((reg5xh & 0x30)>>4)) ? (tmp << 3) : 4;
218 int t3 = (tmp = (reg5yh & 0x03)) ? (tmp << 3) : 4;
219 int t4 = (tmp = ((reg5yh & 0x30)>>4)) ? (tmp << 3) : 4;
220 p += sprintf(p, q, t1, t2, t3, t4);
221 }
222
223 #if 0
224 p += sprintf(p,
225 "FIFO threshold: %2d Words %2d Words"
226 " %2d Words %2d Words\n",
227 (reg5xh & 0x03) + 12,
228 ((reg5xh & 0x30)>>4) + 12,
229 (reg5yh & 0x03) + 12,
230 ((reg5yh & 0x30)>>4) + 12 );
231 #endif
232
233 p += sprintf(p,
234 "FIFO mode: %s %s %s %s\n",
235 fifo[((reg5xh & 0x0c) >> 2)],
236 fifo[((reg5xh & 0xc0) >> 6)],
237 fifo[((reg5yh & 0x0c) >> 2)],
238 fifo[((reg5yh & 0xc0) >> 6)] );
239
240 pci_read_config_byte(bmide_dev, 0x5a, &reg5xh);
241 pci_read_config_byte(bmide_dev, 0x5b, &reg5xh1);
242 pci_read_config_byte(bmide_dev, 0x5e, &reg5yh);
243 pci_read_config_byte(bmide_dev, 0x5f, &reg5yh1);
244
245 p += sprintf(p,/*
246 "------------------drive0-----------drive1"
247 "------------drive0-----------drive1------\n")*/
248 "Dt RW act. Cnt %2dT %2dT"
249 " %2dT %2dT\n"
250 "Dt RW rec. Cnt %2dT %2dT"
251 " %2dT %2dT\n\n",
252 (reg5xh & 0x70) ? ((reg5xh & 0x70) >> 4) : 8,
253 (reg5xh1 & 0x70) ? ((reg5xh1 & 0x70) >> 4) : 8,
254 (reg5yh & 0x70) ? ((reg5yh & 0x70) >> 4) : 8,
255 (reg5yh1 & 0x70) ? ((reg5yh1 & 0x70) >> 4) : 8,
256 (reg5xh & 0x0f) ? (reg5xh & 0x0f) : 16,
257 (reg5xh1 & 0x0f) ? (reg5xh1 & 0x0f) : 16,
258 (reg5yh & 0x0f) ? (reg5yh & 0x0f) : 16,
259 (reg5yh1 & 0x0f) ? (reg5yh1 & 0x0f) : 16 );
260
261 p += sprintf(p,
262 "-----------------------------------UDMA Timings"
263 "--------------------------------\n\n");
264
265 pci_read_config_byte(bmide_dev, 0x56, &reg5xh);
266 pci_read_config_byte(bmide_dev, 0x57, &reg5yh);
267 p += sprintf(p,
268 "UDMA: %s %s"
269 " %s %s\n"
270 "UDMA timings: %s %s"
271 " %s %s\n\n",
272 (reg5xh & 0x08) ? "OK" : "No",
273 (reg5xh & 0x80) ? "OK" : "No",
274 (reg5yh & 0x08) ? "OK" : "No",
275 (reg5yh & 0x80) ? "OK" : "No",
276 udmaT[(reg5xh & 0x07)],
277 udmaT[(reg5xh & 0x70) >> 4],
278 udmaT[reg5yh & 0x07],
279 udmaT[(reg5yh & 0x70) >> 4] );
280
281 return p-buffer; /* => must be less than 4k! */
282 }
283 #endif /* defined(DISPLAY_ALI_TIMINGS) && defined(CONFIG_IDE_PROC_FS) */
284
285 /**
286 * ali_set_pio_mode - set host controller for PIO mode
287 * @drive: drive
288 * @pio: PIO mode number
289 *
290 * Program the controller for the given PIO mode.
291 */
292
293 static void ali_set_pio_mode(ide_drive_t *drive, const u8 pio)
294 {
295 ide_hwif_t *hwif = HWIF(drive);
296 struct pci_dev *dev = hwif->pci_dev;
297 int s_time, a_time, c_time;
298 u8 s_clc, a_clc, r_clc;
299 unsigned long flags;
300 int bus_speed = system_bus_clock();
301 int port = hwif->channel ? 0x5c : 0x58;
302 int portFIFO = hwif->channel ? 0x55 : 0x54;
303 u8 cd_dma_fifo = 0;
304 int unit = drive->select.b.unit & 1;
305
306 s_time = ide_pio_timings[pio].setup_time;
307 a_time = ide_pio_timings[pio].active_time;
308 if ((s_clc = (s_time * bus_speed + 999) / 1000) >= 8)
309 s_clc = 0;
310 if ((a_clc = (a_time * bus_speed + 999) / 1000) >= 8)
311 a_clc = 0;
312 c_time = ide_pio_timings[pio].cycle_time;
313
314 #if 0
315 if ((r_clc = ((c_time - s_time - a_time) * bus_speed + 999) / 1000) >= 16)
316 r_clc = 0;
317 #endif
318
319 if (!(r_clc = (c_time * bus_speed + 999) / 1000 - a_clc - s_clc)) {
320 r_clc = 1;
321 } else {
322 if (r_clc >= 16)
323 r_clc = 0;
324 }
325 local_irq_save(flags);
326
327 /*
328 * PIO mode => ATA FIFO on, ATAPI FIFO off
329 */
330 pci_read_config_byte(dev, portFIFO, &cd_dma_fifo);
331 if (drive->media==ide_disk) {
332 if (unit) {
333 pci_write_config_byte(dev, portFIFO, (cd_dma_fifo & 0x0F) | 0x50);
334 } else {
335 pci_write_config_byte(dev, portFIFO, (cd_dma_fifo & 0xF0) | 0x05);
336 }
337 } else {
338 if (unit) {
339 pci_write_config_byte(dev, portFIFO, cd_dma_fifo & 0x0F);
340 } else {
341 pci_write_config_byte(dev, portFIFO, cd_dma_fifo & 0xF0);
342 }
343 }
344
345 pci_write_config_byte(dev, port, s_clc);
346 pci_write_config_byte(dev, port+drive->select.b.unit+2, (a_clc << 4) | r_clc);
347 local_irq_restore(flags);
348
349 /*
350 * setup active rec
351 * { 70, 165, 365 }, PIO Mode 0
352 * { 50, 125, 208 }, PIO Mode 1
353 * { 30, 100, 110 }, PIO Mode 2
354 * { 30, 80, 70 }, PIO Mode 3 with IORDY
355 * { 25, 70, 25 }, PIO Mode 4 with IORDY ns
356 * { 20, 50, 30 } PIO Mode 5 with IORDY (nonstandard)
357 */
358 }
359
360 /**
361 * ali_udma_filter - compute UDMA mask
362 * @drive: IDE device
363 *
364 * Return available UDMA modes.
365 *
366 * The actual rules for the ALi are:
367 * No UDMA on revisions <= 0x20
368 * Disk only for revisions < 0xC2
369 * Not WDC drives for revisions < 0xC2
370 *
371 * FIXME: WDC ifdef needs to die
372 */
373
374 static u8 ali_udma_filter(ide_drive_t *drive)
375 {
376 if (m5229_revision > 0x20 && m5229_revision < 0xC2) {
377 if (drive->media != ide_disk)
378 return 0;
379 #ifndef CONFIG_WDC_ALI15X3
380 if (chip_is_1543c_e && strstr(drive->id->model, "WDC "))
381 return 0;
382 #endif
383 }
384
385 return drive->hwif->ultra_mask;
386 }
387
388 /**
389 * ali_set_dma_mode - set host controller for DMA mode
390 * @drive: drive
391 * @speed: DMA mode
392 *
393 * Configure the hardware for the desired IDE transfer mode.
394 */
395
396 static void ali_set_dma_mode(ide_drive_t *drive, const u8 speed)
397 {
398 ide_hwif_t *hwif = HWIF(drive);
399 struct pci_dev *dev = hwif->pci_dev;
400 u8 speed1 = speed;
401 u8 unit = (drive->select.b.unit & 0x01);
402 u8 tmpbyte = 0x00;
403 int m5229_udma = (hwif->channel) ? 0x57 : 0x56;
404
405 if (speed < XFER_PIO_0)
406 return;
407
408 if (speed == XFER_UDMA_6)
409 speed1 = 0x47;
410
411 if (speed < XFER_UDMA_0) {
412 u8 ultra_enable = (unit) ? 0x7f : 0xf7;
413 /*
414 * clear "ultra enable" bit
415 */
416 pci_read_config_byte(dev, m5229_udma, &tmpbyte);
417 tmpbyte &= ultra_enable;
418 pci_write_config_byte(dev, m5229_udma, tmpbyte);
419
420 /*
421 * FIXME: Oh, my... DMA timings are never set.
422 */
423 } else {
424 pci_read_config_byte(dev, m5229_udma, &tmpbyte);
425 tmpbyte &= (0x0f << ((1-unit) << 2));
426 /*
427 * enable ultra dma and set timing
428 */
429 tmpbyte |= ((0x08 | ((4-speed1)&0x07)) << (unit << 2));
430 pci_write_config_byte(dev, m5229_udma, tmpbyte);
431 if (speed >= XFER_UDMA_3) {
432 pci_read_config_byte(dev, 0x4b, &tmpbyte);
433 tmpbyte |= 1;
434 pci_write_config_byte(dev, 0x4b, tmpbyte);
435 }
436 }
437 }
438
439 /**
440 * ali15x3_config_drive_for_dma - configure for DMA
441 * @drive: drive to configure
442 *
443 * Configure a drive for DMA operation. If DMA is not possible we
444 * drop the drive into PIO mode instead.
445 */
446
447 static int ali15x3_config_drive_for_dma(ide_drive_t *drive)
448 {
449 drive->init_speed = 0;
450
451 if (ide_tune_dma(drive))
452 return 0;
453
454 ide_set_max_pio(drive);
455
456 return -1;
457 }
458
459 /**
460 * ali15x3_dma_setup - begin a DMA phase
461 * @drive: target device
462 *
463 * Returns 1 if the DMA cannot be performed, zero on success.
464 */
465
466 static int ali15x3_dma_setup(ide_drive_t *drive)
467 {
468 if (m5229_revision < 0xC2 && drive->media != ide_disk) {
469 if (rq_data_dir(drive->hwif->hwgroup->rq))
470 return 1; /* try PIO instead of DMA */
471 }
472 return ide_dma_setup(drive);
473 }
474
475 /**
476 * init_chipset_ali15x3 - Initialise an ALi IDE controller
477 * @dev: PCI device
478 * @name: Name of the controller
479 *
480 * This function initializes the ALI IDE controller and where
481 * appropriate also sets up the 1533 southbridge.
482 */
483
484 static unsigned int __devinit init_chipset_ali15x3 (struct pci_dev *dev, const char *name)
485 {
486 unsigned long flags;
487 u8 tmpbyte;
488 struct pci_dev *north = pci_get_slot(dev->bus, PCI_DEVFN(0,0));
489
490 m5229_revision = dev->revision;
491
492 isa_dev = pci_get_device(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533, NULL);
493
494 #if defined(DISPLAY_ALI_TIMINGS) && defined(CONFIG_IDE_PROC_FS)
495 if (!ali_proc) {
496 ali_proc = 1;
497 bmide_dev = dev;
498 ide_pci_create_host_proc("ali", ali_get_info);
499 }
500 #endif /* defined(DISPLAY_ALI_TIMINGS) && defined(CONFIG_IDE_PROC_FS) */
501
502 local_irq_save(flags);
503
504 if (m5229_revision < 0xC2) {
505 /*
506 * revision 0x20 (1543-E, 1543-F)
507 * revision 0xC0, 0xC1 (1543C-C, 1543C-D, 1543C-E)
508 * clear CD-ROM DMA write bit, m5229, 0x4b, bit 7
509 */
510 pci_read_config_byte(dev, 0x4b, &tmpbyte);
511 /*
512 * clear bit 7
513 */
514 pci_write_config_byte(dev, 0x4b, tmpbyte & 0x7F);
515 goto out;
516 }
517
518 /*
519 * 1543C-B?, 1535, 1535D, 1553
520 * Note 1: not all "motherboard" support this detection
521 * Note 2: if no udma 66 device, the detection may "error".
522 * but in this case, we will not set the device to
523 * ultra 66, the detection result is not important
524 */
525
526 /*
527 * enable "Cable Detection", m5229, 0x4b, bit3
528 */
529 pci_read_config_byte(dev, 0x4b, &tmpbyte);
530 pci_write_config_byte(dev, 0x4b, tmpbyte | 0x08);
531
532 /*
533 * We should only tune the 1533 enable if we are using an ALi
534 * North bridge. We might have no north found on some zany
535 * box without a device at 0:0.0. The ALi bridge will be at
536 * 0:0.0 so if we didn't find one we know what is cooking.
537 */
538 if (north && north->vendor != PCI_VENDOR_ID_AL)
539 goto out;
540
541 if (m5229_revision < 0xC5 && isa_dev)
542 {
543 /*
544 * set south-bridge's enable bit, m1533, 0x79
545 */
546
547 pci_read_config_byte(isa_dev, 0x79, &tmpbyte);
548 if (m5229_revision == 0xC2) {
549 /*
550 * 1543C-B0 (m1533, 0x79, bit 2)
551 */
552 pci_write_config_byte(isa_dev, 0x79, tmpbyte | 0x04);
553 } else if (m5229_revision >= 0xC3) {
554 /*
555 * 1553/1535 (m1533, 0x79, bit 1)
556 */
557 pci_write_config_byte(isa_dev, 0x79, tmpbyte | 0x02);
558 }
559 }
560 out:
561 pci_dev_put(north);
562 pci_dev_put(isa_dev);
563 local_irq_restore(flags);
564 return 0;
565 }
566
567 /*
568 * Cable special cases
569 */
570
571 static const struct dmi_system_id cable_dmi_table[] = {
572 {
573 .ident = "HP Pavilion N5430",
574 .matches = {
575 DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"),
576 DMI_MATCH(DMI_BOARD_VERSION, "OmniBook N32N-736"),
577 },
578 },
579 {
580 .ident = "Toshiba Satellite S1800-814",
581 .matches = {
582 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
583 DMI_MATCH(DMI_PRODUCT_NAME, "S1800-814"),
584 },
585 },
586 { }
587 };
588
589 static int ali_cable_override(struct pci_dev *pdev)
590 {
591 /* Fujitsu P2000 */
592 if (pdev->subsystem_vendor == 0x10CF &&
593 pdev->subsystem_device == 0x10AF)
594 return 1;
595
596 /* Systems by DMI */
597 if (dmi_check_system(cable_dmi_table))
598 return 1;
599
600 return 0;
601 }
602
603 /**
604 * ata66_ali15x3 - check for UDMA 66 support
605 * @hwif: IDE interface
606 *
607 * This checks if the controller and the cable are capable
608 * of UDMA66 transfers. It doesn't check the drives.
609 * But see note 2 below!
610 *
611 * FIXME: frobs bits that are not defined on newer ALi devicea
612 */
613
614 static u8 __devinit ata66_ali15x3(ide_hwif_t *hwif)
615 {
616 struct pci_dev *dev = hwif->pci_dev;
617 unsigned long flags;
618 u8 cbl = ATA_CBL_PATA40, tmpbyte;
619
620 local_irq_save(flags);
621
622 if (m5229_revision >= 0xC2) {
623 /*
624 * m5229 80-pin cable detection (from Host View)
625 *
626 * 0x4a bit0 is 0 => primary channel has 80-pin
627 * 0x4a bit1 is 0 => secondary channel has 80-pin
628 *
629 * Certain laptops use short but suitable cables
630 * and don't implement the detect logic.
631 */
632 if (ali_cable_override(dev))
633 cbl = ATA_CBL_PATA40_SHORT;
634 else {
635 pci_read_config_byte(dev, 0x4a, &tmpbyte);
636 if ((tmpbyte & (1 << hwif->channel)) == 0)
637 cbl = ATA_CBL_PATA80;
638 }
639 } else {
640 /*
641 * check m1533, 0x5e, bit 1~4 == 1001 => & 00011110 = 00010010
642 */
643 pci_read_config_byte(isa_dev, 0x5e, &tmpbyte);
644 chip_is_1543c_e = ((tmpbyte & 0x1e) == 0x12) ? 1: 0;
645 }
646
647 /*
648 * CD_ROM DMA on (m5229, 0x53, bit0)
649 * Enable this bit even if we want to use PIO
650 * PIO FIFO off (m5229, 0x53, bit1)
651 * The hardware will use 0x54h and 0x55h to control PIO FIFO
652 * (Not on later devices it seems)
653 *
654 * 0x53 changes meaning on later revs - we must no touch
655 * bit 1 on them. Need to check if 0x20 is the right break
656 */
657
658 pci_read_config_byte(dev, 0x53, &tmpbyte);
659
660 if(m5229_revision <= 0x20)
661 tmpbyte = (tmpbyte & (~0x02)) | 0x01;
662 else if (m5229_revision == 0xc7 || m5229_revision == 0xc8)
663 tmpbyte |= 0x03;
664 else
665 tmpbyte |= 0x01;
666
667 pci_write_config_byte(dev, 0x53, tmpbyte);
668
669 local_irq_restore(flags);
670
671 return cbl;
672 }
673
674 /**
675 * init_hwif_common_ali15x3 - Set up ALI IDE hardware
676 * @hwif: IDE interface
677 *
678 * Initialize the IDE structure side of the ALi 15x3 driver.
679 */
680
681 static void __devinit init_hwif_common_ali15x3 (ide_hwif_t *hwif)
682 {
683 hwif->autodma = 0;
684 hwif->set_pio_mode = &ali_set_pio_mode;
685 hwif->set_dma_mode = &ali_set_dma_mode;
686 hwif->udma_filter = &ali_udma_filter;
687
688 /* don't use LBA48 DMA on ALi devices before rev 0xC5 */
689 hwif->no_lba48_dma = (m5229_revision <= 0xC4) ? 1 : 0;
690
691 if (!hwif->dma_base) {
692 hwif->drives[0].autotune = 1;
693 hwif->drives[1].autotune = 1;
694 return;
695 }
696
697 if (m5229_revision > 0x20)
698 hwif->atapi_dma = 1;
699
700 if (m5229_revision <= 0x20)
701 hwif->ultra_mask = 0x00; /* no udma */
702 else if (m5229_revision < 0xC2)
703 hwif->ultra_mask = 0x07; /* udma0-2 */
704 else if (m5229_revision == 0xC2 || m5229_revision == 0xC3)
705 hwif->ultra_mask = 0x1f; /* udma0-4 */
706 else if (m5229_revision == 0xC4)
707 hwif->ultra_mask = 0x3f; /* udma0-5 */
708 else
709 hwif->ultra_mask = 0x7f; /* udma0-6 */
710
711 hwif->mwdma_mask = 0x07;
712 hwif->swdma_mask = 0x07;
713
714 if (m5229_revision >= 0x20) {
715 /*
716 * M1543C or newer for DMAing
717 */
718 hwif->ide_dma_check = &ali15x3_config_drive_for_dma;
719 hwif->dma_setup = &ali15x3_dma_setup;
720 if (!noautodma)
721 hwif->autodma = 1;
722
723 if (hwif->cbl != ATA_CBL_PATA40_SHORT)
724 hwif->cbl = ata66_ali15x3(hwif);
725 }
726 hwif->drives[0].autodma = hwif->autodma;
727 hwif->drives[1].autodma = hwif->autodma;
728 }
729
730 /**
731 * init_hwif_ali15x3 - Initialize the ALI IDE x86 stuff
732 * @hwif: interface to configure
733 *
734 * Obtain the IRQ tables for an ALi based IDE solution on the PC
735 * class platforms. This part of the code isn't applicable to the
736 * Sparc systems
737 */
738
739 static void __devinit init_hwif_ali15x3 (ide_hwif_t *hwif)
740 {
741 u8 ideic, inmir;
742 s8 irq_routing_table[] = { -1, 9, 3, 10, 4, 5, 7, 6,
743 1, 11, 0, 12, 0, 14, 0, 15 };
744 int irq = -1;
745
746 if (hwif->pci_dev->device == PCI_DEVICE_ID_AL_M5229)
747 hwif->irq = hwif->channel ? 15 : 14;
748
749 if (isa_dev) {
750 /*
751 * read IDE interface control
752 */
753 pci_read_config_byte(isa_dev, 0x58, &ideic);
754
755 /* bit0, bit1 */
756 ideic = ideic & 0x03;
757
758 /* get IRQ for IDE Controller */
759 if ((hwif->channel && ideic == 0x03) ||
760 (!hwif->channel && !ideic)) {
761 /*
762 * get SIRQ1 routing table
763 */
764 pci_read_config_byte(isa_dev, 0x44, &inmir);
765 inmir = inmir & 0x0f;
766 irq = irq_routing_table[inmir];
767 } else if (hwif->channel && !(ideic & 0x01)) {
768 /*
769 * get SIRQ2 routing table
770 */
771 pci_read_config_byte(isa_dev, 0x75, &inmir);
772 inmir = inmir & 0x0f;
773 irq = irq_routing_table[inmir];
774 }
775 if(irq >= 0)
776 hwif->irq = irq;
777 }
778
779 init_hwif_common_ali15x3(hwif);
780 }
781
782 /**
783 * init_dma_ali15x3 - set up DMA on ALi15x3
784 * @hwif: IDE interface
785 * @dmabase: DMA interface base PCI address
786 *
787 * Set up the DMA functionality on the ALi 15x3. For the ALi
788 * controllers this is generic so we can let the generic code do
789 * the actual work.
790 */
791
792 static void __devinit init_dma_ali15x3 (ide_hwif_t *hwif, unsigned long dmabase)
793 {
794 if (m5229_revision < 0x20)
795 return;
796 if (!hwif->channel)
797 outb(inb(dmabase + 2) & 0x60, dmabase + 2);
798 ide_setup_dma(hwif, dmabase, 8);
799 }
800
801 static ide_pci_device_t ali15x3_chipset __devinitdata = {
802 .name = "ALI15X3",
803 .init_chipset = init_chipset_ali15x3,
804 .init_hwif = init_hwif_ali15x3,
805 .init_dma = init_dma_ali15x3,
806 .autodma = AUTODMA,
807 .bootable = ON_BOARD,
808 .pio_mask = ATA_PIO5,
809 };
810
811 /**
812 * alim15x3_init_one - set up an ALi15x3 IDE controller
813 * @dev: PCI device to set up
814 *
815 * Perform the actual set up for an ALi15x3 that has been found by the
816 * hot plug layer.
817 */
818
819 static int __devinit alim15x3_init_one(struct pci_dev *dev, const struct pci_device_id *id)
820 {
821 static struct pci_device_id ati_rs100[] = {
822 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS100) },
823 { },
824 };
825
826 ide_pci_device_t *d = &ali15x3_chipset;
827
828 if (pci_dev_present(ati_rs100))
829 printk(KERN_WARNING "alim15x3: ATI Radeon IGP Northbridge is not yet fully tested.\n");
830
831 #if defined(CONFIG_SPARC64)
832 d->init_hwif = init_hwif_common_ali15x3;
833 #endif /* CONFIG_SPARC64 */
834 return ide_setup_pci_device(dev, d);
835 }
836
837
838 static struct pci_device_id alim15x3_pci_tbl[] = {
839 { PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M5229, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
840 { PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M5228, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
841 { 0, },
842 };
843 MODULE_DEVICE_TABLE(pci, alim15x3_pci_tbl);
844
845 static struct pci_driver driver = {
846 .name = "ALI15x3_IDE",
847 .id_table = alim15x3_pci_tbl,
848 .probe = alim15x3_init_one,
849 };
850
851 static int __init ali15x3_ide_init(void)
852 {
853 return ide_pci_register_driver(&driver);
854 }
855
856 module_init(ali15x3_ide_init);
857
858 MODULE_AUTHOR("Michael Aubry, Andrzej Krzysztofowicz, CJ, Andre Hedrick, Alan Cox");
859 MODULE_DESCRIPTION("PCI driver module for ALi 15x3 IDE");
860 MODULE_LICENSE("GPL");
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