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alim15x3: PIO mode setup fixes
[mirror_ubuntu-zesty-kernel.git] / drivers / ide / pci / alim15x3.c
1 /*
2 * linux/drivers/ide/pci/alim15x3.c Version 0.26 Jul 14 2007
3 *
4 * Copyright (C) 1998-2000 Michel Aubry, Maintainer
5 * Copyright (C) 1998-2000 Andrzej Krzysztofowicz, Maintainer
6 * Copyright (C) 1999-2000 CJ, cjtsai@ali.com.tw, Maintainer
7 *
8 * Copyright (C) 1998-2000 Andre Hedrick (andre@linux-ide.org)
9 * May be copied or modified under the terms of the GNU General Public License
10 * Copyright (C) 2002 Alan Cox <alan@redhat.com>
11 * ALi (now ULi M5228) support by Clear Zhang <Clear.Zhang@ali.com.tw>
12 * Copyright (C) 2007 MontaVista Software, Inc. <source@mvista.com>
13 * Copyright (C) 2007 Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
14 *
15 * (U)DMA capable version of ali 1533/1543(C), 1535(D)
16 *
17 **********************************************************************
18 * 9/7/99 --Parts from the above author are included and need to be
19 * converted into standard interface, once I finish the thought.
20 *
21 * Recent changes
22 * Don't use LBA48 mode on ALi <= 0xC4
23 * Don't poke 0x79 with a non ALi northbridge
24 * Don't flip undefined bits on newer chipsets (fix Fujitsu laptop hang)
25 * Allow UDMA6 on revisions > 0xC4
26 *
27 * Documentation
28 * Chipset documentation available under NDA only
29 *
30 */
31
32 #include <linux/module.h>
33 #include <linux/types.h>
34 #include <linux/kernel.h>
35 #include <linux/pci.h>
36 #include <linux/delay.h>
37 #include <linux/hdreg.h>
38 #include <linux/ide.h>
39 #include <linux/init.h>
40 #include <linux/dmi.h>
41
42 #include <asm/io.h>
43
44 #define DISPLAY_ALI_TIMINGS
45
46 /*
47 * ALi devices are not plug in. Otherwise these static values would
48 * need to go. They ought to go away anyway
49 */
50
51 static u8 m5229_revision;
52 static u8 chip_is_1543c_e;
53 static struct pci_dev *isa_dev;
54
55 #if defined(DISPLAY_ALI_TIMINGS) && defined(CONFIG_IDE_PROC_FS)
56 #include <linux/stat.h>
57 #include <linux/proc_fs.h>
58
59 static u8 ali_proc = 0;
60
61 static struct pci_dev *bmide_dev;
62
63 static char *fifo[4] = {
64 "FIFO Off",
65 "FIFO On ",
66 "DMA mode",
67 "PIO mode" };
68
69 static char *udmaT[8] = {
70 "1.5T",
71 " 2T",
72 "2.5T",
73 " 3T",
74 "3.5T",
75 " 4T",
76 " 6T",
77 " 8T"
78 };
79
80 static char *channel_status[8] = {
81 "OK ",
82 "busy ",
83 "DRQ ",
84 "DRQ busy ",
85 "error ",
86 "error busy ",
87 "error DRQ ",
88 "error DRQ busy"
89 };
90
91 /**
92 * ali_get_info - generate proc file for ALi IDE
93 * @buffer: buffer to fill
94 * @addr: address of user start in buffer
95 * @offset: offset into 'file'
96 * @count: buffer count
97 *
98 * Walks the Ali devices and outputs summary data on the tuning and
99 * anything else that will help with debugging
100 */
101
102 static int ali_get_info (char *buffer, char **addr, off_t offset, int count)
103 {
104 unsigned long bibma;
105 u8 reg53h, reg5xh, reg5yh, reg5xh1, reg5yh1, c0, c1, rev, tmp;
106 char *q, *p = buffer;
107
108 /* fetch rev. */
109 pci_read_config_byte(bmide_dev, 0x08, &rev);
110 if (rev >= 0xc1) /* M1543C or newer */
111 udmaT[7] = " ???";
112 else
113 fifo[3] = " ??? ";
114
115 /* first fetch bibma: */
116
117 bibma = pci_resource_start(bmide_dev, 4);
118
119 /*
120 * at that point bibma+0x2 et bibma+0xa are byte
121 * registers to investigate:
122 */
123 c0 = inb(bibma + 0x02);
124 c1 = inb(bibma + 0x0a);
125
126 p += sprintf(p,
127 "\n Ali M15x3 Chipset.\n");
128 p += sprintf(p,
129 " ------------------\n");
130 pci_read_config_byte(bmide_dev, 0x78, &reg53h);
131 p += sprintf(p, "PCI Clock: %d.\n", reg53h);
132
133 pci_read_config_byte(bmide_dev, 0x53, &reg53h);
134 p += sprintf(p,
135 "CD_ROM FIFO:%s, CD_ROM DMA:%s\n",
136 (reg53h & 0x02) ? "Yes" : "No ",
137 (reg53h & 0x01) ? "Yes" : "No " );
138 pci_read_config_byte(bmide_dev, 0x74, &reg53h);
139 p += sprintf(p,
140 "FIFO Status: contains %d Words, runs%s%s\n\n",
141 (reg53h & 0x3f),
142 (reg53h & 0x40) ? " OVERWR" : "",
143 (reg53h & 0x80) ? " OVERRD." : "." );
144
145 p += sprintf(p,
146 "-------------------primary channel"
147 "-------------------secondary channel"
148 "---------\n\n");
149
150 pci_read_config_byte(bmide_dev, 0x09, &reg53h);
151 p += sprintf(p,
152 "channel status: %s"
153 " %s\n",
154 (reg53h & 0x20) ? "On " : "Off",
155 (reg53h & 0x10) ? "On " : "Off" );
156
157 p += sprintf(p,
158 "both channels togth: %s"
159 " %s\n",
160 (c0&0x80) ? "No " : "Yes",
161 (c1&0x80) ? "No " : "Yes" );
162
163 pci_read_config_byte(bmide_dev, 0x76, &reg53h);
164 p += sprintf(p,
165 "Channel state: %s %s\n",
166 channel_status[reg53h & 0x07],
167 channel_status[(reg53h & 0x70) >> 4] );
168
169 pci_read_config_byte(bmide_dev, 0x58, &reg5xh);
170 pci_read_config_byte(bmide_dev, 0x5c, &reg5yh);
171 p += sprintf(p,
172 "Add. Setup Timing: %dT"
173 " %dT\n",
174 (reg5xh & 0x07) ? (reg5xh & 0x07) : 8,
175 (reg5yh & 0x07) ? (reg5yh & 0x07) : 8 );
176
177 pci_read_config_byte(bmide_dev, 0x59, &reg5xh);
178 pci_read_config_byte(bmide_dev, 0x5d, &reg5yh);
179 p += sprintf(p,
180 "Command Act. Count: %dT"
181 " %dT\n"
182 "Command Rec. Count: %dT"
183 " %dT\n\n",
184 (reg5xh & 0x70) ? ((reg5xh & 0x70) >> 4) : 8,
185 (reg5yh & 0x70) ? ((reg5yh & 0x70) >> 4) : 8,
186 (reg5xh & 0x0f) ? (reg5xh & 0x0f) : 16,
187 (reg5yh & 0x0f) ? (reg5yh & 0x0f) : 16 );
188
189 p += sprintf(p,
190 "----------------drive0-----------drive1"
191 "------------drive0-----------drive1------\n\n");
192 p += sprintf(p,
193 "DMA enabled: %s %s"
194 " %s %s\n",
195 (c0&0x20) ? "Yes" : "No ",
196 (c0&0x40) ? "Yes" : "No ",
197 (c1&0x20) ? "Yes" : "No ",
198 (c1&0x40) ? "Yes" : "No " );
199
200 pci_read_config_byte(bmide_dev, 0x54, &reg5xh);
201 pci_read_config_byte(bmide_dev, 0x55, &reg5yh);
202 q = "FIFO threshold: %2d Words %2d Words"
203 " %2d Words %2d Words\n";
204 if (rev < 0xc1) {
205 if ((rev == 0x20) &&
206 (pci_read_config_byte(bmide_dev, 0x4f, &tmp), (tmp &= 0x20))) {
207 p += sprintf(p, q, 8, 8, 8, 8);
208 } else {
209 p += sprintf(p, q,
210 (reg5xh & 0x03) + 12,
211 ((reg5xh & 0x30)>>4) + 12,
212 (reg5yh & 0x03) + 12,
213 ((reg5yh & 0x30)>>4) + 12 );
214 }
215 } else {
216 int t1 = (tmp = (reg5xh & 0x03)) ? (tmp << 3) : 4;
217 int t2 = (tmp = ((reg5xh & 0x30)>>4)) ? (tmp << 3) : 4;
218 int t3 = (tmp = (reg5yh & 0x03)) ? (tmp << 3) : 4;
219 int t4 = (tmp = ((reg5yh & 0x30)>>4)) ? (tmp << 3) : 4;
220 p += sprintf(p, q, t1, t2, t3, t4);
221 }
222
223 #if 0
224 p += sprintf(p,
225 "FIFO threshold: %2d Words %2d Words"
226 " %2d Words %2d Words\n",
227 (reg5xh & 0x03) + 12,
228 ((reg5xh & 0x30)>>4) + 12,
229 (reg5yh & 0x03) + 12,
230 ((reg5yh & 0x30)>>4) + 12 );
231 #endif
232
233 p += sprintf(p,
234 "FIFO mode: %s %s %s %s\n",
235 fifo[((reg5xh & 0x0c) >> 2)],
236 fifo[((reg5xh & 0xc0) >> 6)],
237 fifo[((reg5yh & 0x0c) >> 2)],
238 fifo[((reg5yh & 0xc0) >> 6)] );
239
240 pci_read_config_byte(bmide_dev, 0x5a, &reg5xh);
241 pci_read_config_byte(bmide_dev, 0x5b, &reg5xh1);
242 pci_read_config_byte(bmide_dev, 0x5e, &reg5yh);
243 pci_read_config_byte(bmide_dev, 0x5f, &reg5yh1);
244
245 p += sprintf(p,/*
246 "------------------drive0-----------drive1"
247 "------------drive0-----------drive1------\n")*/
248 "Dt RW act. Cnt %2dT %2dT"
249 " %2dT %2dT\n"
250 "Dt RW rec. Cnt %2dT %2dT"
251 " %2dT %2dT\n\n",
252 (reg5xh & 0x70) ? ((reg5xh & 0x70) >> 4) : 8,
253 (reg5xh1 & 0x70) ? ((reg5xh1 & 0x70) >> 4) : 8,
254 (reg5yh & 0x70) ? ((reg5yh & 0x70) >> 4) : 8,
255 (reg5yh1 & 0x70) ? ((reg5yh1 & 0x70) >> 4) : 8,
256 (reg5xh & 0x0f) ? (reg5xh & 0x0f) : 16,
257 (reg5xh1 & 0x0f) ? (reg5xh1 & 0x0f) : 16,
258 (reg5yh & 0x0f) ? (reg5yh & 0x0f) : 16,
259 (reg5yh1 & 0x0f) ? (reg5yh1 & 0x0f) : 16 );
260
261 p += sprintf(p,
262 "-----------------------------------UDMA Timings"
263 "--------------------------------\n\n");
264
265 pci_read_config_byte(bmide_dev, 0x56, &reg5xh);
266 pci_read_config_byte(bmide_dev, 0x57, &reg5yh);
267 p += sprintf(p,
268 "UDMA: %s %s"
269 " %s %s\n"
270 "UDMA timings: %s %s"
271 " %s %s\n\n",
272 (reg5xh & 0x08) ? "OK" : "No",
273 (reg5xh & 0x80) ? "OK" : "No",
274 (reg5yh & 0x08) ? "OK" : "No",
275 (reg5yh & 0x80) ? "OK" : "No",
276 udmaT[(reg5xh & 0x07)],
277 udmaT[(reg5xh & 0x70) >> 4],
278 udmaT[reg5yh & 0x07],
279 udmaT[(reg5yh & 0x70) >> 4] );
280
281 return p-buffer; /* => must be less than 4k! */
282 }
283 #endif /* defined(DISPLAY_ALI_TIMINGS) && defined(CONFIG_IDE_PROC_FS) */
284
285 /**
286 * ali_tune_pio - set host controller for PIO mode
287 * @drive: drive
288 * @pio: PIO mode number
289 *
290 * Program the controller for the given PIO mode.
291 */
292
293 static void ali_tune_pio(ide_drive_t *drive, const u8 pio)
294 {
295 ide_hwif_t *hwif = HWIF(drive);
296 struct pci_dev *dev = hwif->pci_dev;
297 int s_time, a_time, c_time;
298 u8 s_clc, a_clc, r_clc;
299 unsigned long flags;
300 int bus_speed = system_bus_clock();
301 int port = hwif->channel ? 0x5c : 0x58;
302 int portFIFO = hwif->channel ? 0x55 : 0x54;
303 u8 cd_dma_fifo = 0;
304 int unit = drive->select.b.unit & 1;
305
306 s_time = ide_pio_timings[pio].setup_time;
307 a_time = ide_pio_timings[pio].active_time;
308 if ((s_clc = (s_time * bus_speed + 999) / 1000) >= 8)
309 s_clc = 0;
310 if ((a_clc = (a_time * bus_speed + 999) / 1000) >= 8)
311 a_clc = 0;
312 c_time = ide_pio_timings[pio].cycle_time;
313
314 #if 0
315 if ((r_clc = ((c_time - s_time - a_time) * bus_speed + 999) / 1000) >= 16)
316 r_clc = 0;
317 #endif
318
319 if (!(r_clc = (c_time * bus_speed + 999) / 1000 - a_clc - s_clc)) {
320 r_clc = 1;
321 } else {
322 if (r_clc >= 16)
323 r_clc = 0;
324 }
325 local_irq_save(flags);
326
327 /*
328 * PIO mode => ATA FIFO on, ATAPI FIFO off
329 */
330 pci_read_config_byte(dev, portFIFO, &cd_dma_fifo);
331 if (drive->media==ide_disk) {
332 if (unit) {
333 pci_write_config_byte(dev, portFIFO, (cd_dma_fifo & 0x0F) | 0x50);
334 } else {
335 pci_write_config_byte(dev, portFIFO, (cd_dma_fifo & 0xF0) | 0x05);
336 }
337 } else {
338 if (unit) {
339 pci_write_config_byte(dev, portFIFO, cd_dma_fifo & 0x0F);
340 } else {
341 pci_write_config_byte(dev, portFIFO, cd_dma_fifo & 0xF0);
342 }
343 }
344
345 pci_write_config_byte(dev, port, s_clc);
346 pci_write_config_byte(dev, port+drive->select.b.unit+2, (a_clc << 4) | r_clc);
347 local_irq_restore(flags);
348
349 /*
350 * setup active rec
351 * { 70, 165, 365 }, PIO Mode 0
352 * { 50, 125, 208 }, PIO Mode 1
353 * { 30, 100, 110 }, PIO Mode 2
354 * { 30, 80, 70 }, PIO Mode 3 with IORDY
355 * { 25, 70, 25 }, PIO Mode 4 with IORDY ns
356 * { 20, 50, 30 } PIO Mode 5 with IORDY (nonstandard)
357 */
358 }
359
360 /**
361 * ali_set_pio_mode - set up drive for PIO mode
362 * @drive: drive to tune
363 * @pio: desired mode
364 *
365 * Program the controller with the desired PIO timing for the given drive.
366 * Then set up the drive itself.
367 */
368
369 static void ali_set_pio_mode(ide_drive_t *drive, const u8 pio)
370 {
371 ali_tune_pio(drive, pio);
372 (void) ide_config_drive_speed(drive, XFER_PIO_0 + pio);
373 }
374
375 /**
376 * ali_udma_filter - compute UDMA mask
377 * @drive: IDE device
378 *
379 * Return available UDMA modes.
380 *
381 * The actual rules for the ALi are:
382 * No UDMA on revisions <= 0x20
383 * Disk only for revisions < 0xC2
384 * Not WDC drives for revisions < 0xC2
385 *
386 * FIXME: WDC ifdef needs to die
387 */
388
389 static u8 ali_udma_filter(ide_drive_t *drive)
390 {
391 if (m5229_revision > 0x20 && m5229_revision < 0xC2) {
392 if (drive->media != ide_disk)
393 return 0;
394 #ifndef CONFIG_WDC_ALI15X3
395 if (chip_is_1543c_e && strstr(drive->id->model, "WDC "))
396 return 0;
397 #endif
398 }
399
400 return drive->hwif->ultra_mask;
401 }
402
403 /**
404 * ali15x3_tune_chipset - set up chipset/drive for new speed
405 * @drive: drive to configure for
406 * @speed: desired speed
407 *
408 * Configure the hardware for the desired IDE transfer mode.
409 * We also do the needed drive configuration through helpers
410 */
411
412 static int ali15x3_tune_chipset(ide_drive_t *drive, const u8 speed)
413 {
414 ide_hwif_t *hwif = HWIF(drive);
415 struct pci_dev *dev = hwif->pci_dev;
416 u8 speed1 = speed;
417 u8 unit = (drive->select.b.unit & 0x01);
418 u8 tmpbyte = 0x00;
419 int m5229_udma = (hwif->channel) ? 0x57 : 0x56;
420
421 if (speed < XFER_PIO_0)
422 return 1;
423
424 if (speed >= XFER_PIO_0 && speed <= XFER_PIO_5) {
425 ali_tune_pio(drive, speed - XFER_PIO_0);
426 return ide_config_drive_speed(drive, speed);
427 }
428
429 if (speed == XFER_UDMA_6)
430 speed1 = 0x47;
431
432 if (speed < XFER_UDMA_0) {
433 u8 ultra_enable = (unit) ? 0x7f : 0xf7;
434 /*
435 * clear "ultra enable" bit
436 */
437 pci_read_config_byte(dev, m5229_udma, &tmpbyte);
438 tmpbyte &= ultra_enable;
439 pci_write_config_byte(dev, m5229_udma, tmpbyte);
440
441 /*
442 * FIXME: Oh, my... DMA timings are never set.
443 */
444 } else {
445 pci_read_config_byte(dev, m5229_udma, &tmpbyte);
446 tmpbyte &= (0x0f << ((1-unit) << 2));
447 /*
448 * enable ultra dma and set timing
449 */
450 tmpbyte |= ((0x08 | ((4-speed1)&0x07)) << (unit << 2));
451 pci_write_config_byte(dev, m5229_udma, tmpbyte);
452 if (speed >= XFER_UDMA_3) {
453 pci_read_config_byte(dev, 0x4b, &tmpbyte);
454 tmpbyte |= 1;
455 pci_write_config_byte(dev, 0x4b, tmpbyte);
456 }
457 }
458 return (ide_config_drive_speed(drive, speed));
459 }
460
461 /**
462 * ali15x3_config_drive_for_dma - configure for DMA
463 * @drive: drive to configure
464 *
465 * Configure a drive for DMA operation. If DMA is not possible we
466 * drop the drive into PIO mode instead.
467 */
468
469 static int ali15x3_config_drive_for_dma(ide_drive_t *drive)
470 {
471 drive->init_speed = 0;
472
473 if (ide_tune_dma(drive))
474 return 0;
475
476 ide_set_max_pio(drive);
477
478 return -1;
479 }
480
481 /**
482 * ali15x3_dma_setup - begin a DMA phase
483 * @drive: target device
484 *
485 * Returns 1 if the DMA cannot be performed, zero on success.
486 */
487
488 static int ali15x3_dma_setup(ide_drive_t *drive)
489 {
490 if (m5229_revision < 0xC2 && drive->media != ide_disk) {
491 if (rq_data_dir(drive->hwif->hwgroup->rq))
492 return 1; /* try PIO instead of DMA */
493 }
494 return ide_dma_setup(drive);
495 }
496
497 /**
498 * init_chipset_ali15x3 - Initialise an ALi IDE controller
499 * @dev: PCI device
500 * @name: Name of the controller
501 *
502 * This function initializes the ALI IDE controller and where
503 * appropriate also sets up the 1533 southbridge.
504 */
505
506 static unsigned int __devinit init_chipset_ali15x3 (struct pci_dev *dev, const char *name)
507 {
508 unsigned long flags;
509 u8 tmpbyte;
510 struct pci_dev *north = pci_get_slot(dev->bus, PCI_DEVFN(0,0));
511
512 m5229_revision = dev->revision;
513
514 isa_dev = pci_get_device(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533, NULL);
515
516 #if defined(DISPLAY_ALI_TIMINGS) && defined(CONFIG_IDE_PROC_FS)
517 if (!ali_proc) {
518 ali_proc = 1;
519 bmide_dev = dev;
520 ide_pci_create_host_proc("ali", ali_get_info);
521 }
522 #endif /* defined(DISPLAY_ALI_TIMINGS) && defined(CONFIG_IDE_PROC_FS) */
523
524 local_irq_save(flags);
525
526 if (m5229_revision < 0xC2) {
527 /*
528 * revision 0x20 (1543-E, 1543-F)
529 * revision 0xC0, 0xC1 (1543C-C, 1543C-D, 1543C-E)
530 * clear CD-ROM DMA write bit, m5229, 0x4b, bit 7
531 */
532 pci_read_config_byte(dev, 0x4b, &tmpbyte);
533 /*
534 * clear bit 7
535 */
536 pci_write_config_byte(dev, 0x4b, tmpbyte & 0x7F);
537 goto out;
538 }
539
540 /*
541 * 1543C-B?, 1535, 1535D, 1553
542 * Note 1: not all "motherboard" support this detection
543 * Note 2: if no udma 66 device, the detection may "error".
544 * but in this case, we will not set the device to
545 * ultra 66, the detection result is not important
546 */
547
548 /*
549 * enable "Cable Detection", m5229, 0x4b, bit3
550 */
551 pci_read_config_byte(dev, 0x4b, &tmpbyte);
552 pci_write_config_byte(dev, 0x4b, tmpbyte | 0x08);
553
554 /*
555 * We should only tune the 1533 enable if we are using an ALi
556 * North bridge. We might have no north found on some zany
557 * box without a device at 0:0.0. The ALi bridge will be at
558 * 0:0.0 so if we didn't find one we know what is cooking.
559 */
560 if (north && north->vendor != PCI_VENDOR_ID_AL)
561 goto out;
562
563 if (m5229_revision < 0xC5 && isa_dev)
564 {
565 /*
566 * set south-bridge's enable bit, m1533, 0x79
567 */
568
569 pci_read_config_byte(isa_dev, 0x79, &tmpbyte);
570 if (m5229_revision == 0xC2) {
571 /*
572 * 1543C-B0 (m1533, 0x79, bit 2)
573 */
574 pci_write_config_byte(isa_dev, 0x79, tmpbyte | 0x04);
575 } else if (m5229_revision >= 0xC3) {
576 /*
577 * 1553/1535 (m1533, 0x79, bit 1)
578 */
579 pci_write_config_byte(isa_dev, 0x79, tmpbyte | 0x02);
580 }
581 }
582 out:
583 pci_dev_put(north);
584 pci_dev_put(isa_dev);
585 local_irq_restore(flags);
586 return 0;
587 }
588
589 /*
590 * Cable special cases
591 */
592
593 static struct dmi_system_id cable_dmi_table[] = {
594 {
595 .ident = "HP Pavilion N5430",
596 .matches = {
597 DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"),
598 DMI_MATCH(DMI_BOARD_VERSION, "OmniBook N32N-736"),
599 },
600 },
601 {
602 .ident = "Toshiba Satellite S1800-814",
603 .matches = {
604 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
605 DMI_MATCH(DMI_PRODUCT_NAME, "S1800-814"),
606 },
607 },
608 { }
609 };
610
611 static int ali_cable_override(struct pci_dev *pdev)
612 {
613 /* Fujitsu P2000 */
614 if (pdev->subsystem_vendor == 0x10CF &&
615 pdev->subsystem_device == 0x10AF)
616 return 1;
617
618 /* Systems by DMI */
619 if (dmi_check_system(cable_dmi_table))
620 return 1;
621
622 return 0;
623 }
624
625 /**
626 * ata66_ali15x3 - check for UDMA 66 support
627 * @hwif: IDE interface
628 *
629 * This checks if the controller and the cable are capable
630 * of UDMA66 transfers. It doesn't check the drives.
631 * But see note 2 below!
632 *
633 * FIXME: frobs bits that are not defined on newer ALi devicea
634 */
635
636 static u8 __devinit ata66_ali15x3(ide_hwif_t *hwif)
637 {
638 struct pci_dev *dev = hwif->pci_dev;
639 unsigned long flags;
640 u8 cbl = ATA_CBL_PATA40, tmpbyte;
641
642 local_irq_save(flags);
643
644 if (m5229_revision >= 0xC2) {
645 /*
646 * m5229 80-pin cable detection (from Host View)
647 *
648 * 0x4a bit0 is 0 => primary channel has 80-pin
649 * 0x4a bit1 is 0 => secondary channel has 80-pin
650 *
651 * Certain laptops use short but suitable cables
652 * and don't implement the detect logic.
653 */
654 if (ali_cable_override(dev))
655 cbl = ATA_CBL_PATA40_SHORT;
656 else {
657 pci_read_config_byte(dev, 0x4a, &tmpbyte);
658 if ((tmpbyte & (1 << hwif->channel)) == 0)
659 cbl = ATA_CBL_PATA80;
660 }
661 } else {
662 /*
663 * check m1533, 0x5e, bit 1~4 == 1001 => & 00011110 = 00010010
664 */
665 pci_read_config_byte(isa_dev, 0x5e, &tmpbyte);
666 chip_is_1543c_e = ((tmpbyte & 0x1e) == 0x12) ? 1: 0;
667 }
668
669 /*
670 * CD_ROM DMA on (m5229, 0x53, bit0)
671 * Enable this bit even if we want to use PIO
672 * PIO FIFO off (m5229, 0x53, bit1)
673 * The hardware will use 0x54h and 0x55h to control PIO FIFO
674 * (Not on later devices it seems)
675 *
676 * 0x53 changes meaning on later revs - we must no touch
677 * bit 1 on them. Need to check if 0x20 is the right break
678 */
679
680 pci_read_config_byte(dev, 0x53, &tmpbyte);
681
682 if(m5229_revision <= 0x20)
683 tmpbyte = (tmpbyte & (~0x02)) | 0x01;
684 else if (m5229_revision == 0xc7 || m5229_revision == 0xc8)
685 tmpbyte |= 0x03;
686 else
687 tmpbyte |= 0x01;
688
689 pci_write_config_byte(dev, 0x53, tmpbyte);
690
691 local_irq_restore(flags);
692
693 return cbl;
694 }
695
696 /**
697 * init_hwif_common_ali15x3 - Set up ALI IDE hardware
698 * @hwif: IDE interface
699 *
700 * Initialize the IDE structure side of the ALi 15x3 driver.
701 */
702
703 static void __devinit init_hwif_common_ali15x3 (ide_hwif_t *hwif)
704 {
705 hwif->autodma = 0;
706 hwif->set_pio_mode = &ali_set_pio_mode;
707 hwif->speedproc = &ali15x3_tune_chipset;
708 hwif->udma_filter = &ali_udma_filter;
709
710 /* don't use LBA48 DMA on ALi devices before rev 0xC5 */
711 hwif->no_lba48_dma = (m5229_revision <= 0xC4) ? 1 : 0;
712
713 if (!hwif->dma_base) {
714 hwif->drives[0].autotune = 1;
715 hwif->drives[1].autotune = 1;
716 return;
717 }
718
719 if (m5229_revision > 0x20)
720 hwif->atapi_dma = 1;
721
722 if (m5229_revision <= 0x20)
723 hwif->ultra_mask = 0x00; /* no udma */
724 else if (m5229_revision < 0xC2)
725 hwif->ultra_mask = 0x07; /* udma0-2 */
726 else if (m5229_revision == 0xC2 || m5229_revision == 0xC3)
727 hwif->ultra_mask = 0x1f; /* udma0-4 */
728 else if (m5229_revision == 0xC4)
729 hwif->ultra_mask = 0x3f; /* udma0-5 */
730 else
731 hwif->ultra_mask = 0x7f; /* udma0-6 */
732
733 hwif->mwdma_mask = 0x07;
734 hwif->swdma_mask = 0x07;
735
736 if (m5229_revision >= 0x20) {
737 /*
738 * M1543C or newer for DMAing
739 */
740 hwif->ide_dma_check = &ali15x3_config_drive_for_dma;
741 hwif->dma_setup = &ali15x3_dma_setup;
742 if (!noautodma)
743 hwif->autodma = 1;
744
745 if (hwif->cbl != ATA_CBL_PATA40_SHORT)
746 hwif->cbl = ata66_ali15x3(hwif);
747 }
748 hwif->drives[0].autodma = hwif->autodma;
749 hwif->drives[1].autodma = hwif->autodma;
750 }
751
752 /**
753 * init_hwif_ali15x3 - Initialize the ALI IDE x86 stuff
754 * @hwif: interface to configure
755 *
756 * Obtain the IRQ tables for an ALi based IDE solution on the PC
757 * class platforms. This part of the code isn't applicable to the
758 * Sparc systems
759 */
760
761 static void __devinit init_hwif_ali15x3 (ide_hwif_t *hwif)
762 {
763 u8 ideic, inmir;
764 s8 irq_routing_table[] = { -1, 9, 3, 10, 4, 5, 7, 6,
765 1, 11, 0, 12, 0, 14, 0, 15 };
766 int irq = -1;
767
768 if (hwif->pci_dev->device == PCI_DEVICE_ID_AL_M5229)
769 hwif->irq = hwif->channel ? 15 : 14;
770
771 if (isa_dev) {
772 /*
773 * read IDE interface control
774 */
775 pci_read_config_byte(isa_dev, 0x58, &ideic);
776
777 /* bit0, bit1 */
778 ideic = ideic & 0x03;
779
780 /* get IRQ for IDE Controller */
781 if ((hwif->channel && ideic == 0x03) ||
782 (!hwif->channel && !ideic)) {
783 /*
784 * get SIRQ1 routing table
785 */
786 pci_read_config_byte(isa_dev, 0x44, &inmir);
787 inmir = inmir & 0x0f;
788 irq = irq_routing_table[inmir];
789 } else if (hwif->channel && !(ideic & 0x01)) {
790 /*
791 * get SIRQ2 routing table
792 */
793 pci_read_config_byte(isa_dev, 0x75, &inmir);
794 inmir = inmir & 0x0f;
795 irq = irq_routing_table[inmir];
796 }
797 if(irq >= 0)
798 hwif->irq = irq;
799 }
800
801 init_hwif_common_ali15x3(hwif);
802 }
803
804 /**
805 * init_dma_ali15x3 - set up DMA on ALi15x3
806 * @hwif: IDE interface
807 * @dmabase: DMA interface base PCI address
808 *
809 * Set up the DMA functionality on the ALi 15x3. For the ALi
810 * controllers this is generic so we can let the generic code do
811 * the actual work.
812 */
813
814 static void __devinit init_dma_ali15x3 (ide_hwif_t *hwif, unsigned long dmabase)
815 {
816 if (m5229_revision < 0x20)
817 return;
818 if (!hwif->channel)
819 outb(inb(dmabase + 2) & 0x60, dmabase + 2);
820 ide_setup_dma(hwif, dmabase, 8);
821 }
822
823 static ide_pci_device_t ali15x3_chipset __devinitdata = {
824 .name = "ALI15X3",
825 .init_chipset = init_chipset_ali15x3,
826 .init_hwif = init_hwif_ali15x3,
827 .init_dma = init_dma_ali15x3,
828 .autodma = AUTODMA,
829 .bootable = ON_BOARD,
830 .pio_mask = ATA_PIO5,
831 };
832
833 /**
834 * alim15x3_init_one - set up an ALi15x3 IDE controller
835 * @dev: PCI device to set up
836 *
837 * Perform the actual set up for an ALi15x3 that has been found by the
838 * hot plug layer.
839 */
840
841 static int __devinit alim15x3_init_one(struct pci_dev *dev, const struct pci_device_id *id)
842 {
843 static struct pci_device_id ati_rs100[] = {
844 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS100) },
845 { },
846 };
847
848 ide_pci_device_t *d = &ali15x3_chipset;
849
850 if (pci_dev_present(ati_rs100))
851 printk(KERN_WARNING "alim15x3: ATI Radeon IGP Northbridge is not yet fully tested.\n");
852
853 #if defined(CONFIG_SPARC64)
854 d->init_hwif = init_hwif_common_ali15x3;
855 #endif /* CONFIG_SPARC64 */
856 return ide_setup_pci_device(dev, d);
857 }
858
859
860 static struct pci_device_id alim15x3_pci_tbl[] = {
861 { PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M5229, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
862 { PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M5228, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
863 { 0, },
864 };
865 MODULE_DEVICE_TABLE(pci, alim15x3_pci_tbl);
866
867 static struct pci_driver driver = {
868 .name = "ALI15x3_IDE",
869 .id_table = alim15x3_pci_tbl,
870 .probe = alim15x3_init_one,
871 };
872
873 static int __init ali15x3_ide_init(void)
874 {
875 return ide_pci_register_driver(&driver);
876 }
877
878 module_init(ali15x3_ide_init);
879
880 MODULE_AUTHOR("Michael Aubry, Andrzej Krzysztofowicz, CJ, Andre Hedrick, Alan Cox");
881 MODULE_DESCRIPTION("PCI driver module for ALi 15x3 IDE");
882 MODULE_LICENSE("GPL");
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