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1 /*
2 * Copyright (C) 1995-1996 Linus Torvalds & authors (see below)
3 */
4
5 /*
6 * Original authors: abramov@cecmow.enet.dec.com (Igor Abramov)
7 * mlord@pobox.com (Mark Lord)
8 *
9 * See linux/MAINTAINERS for address of current maintainer.
10 *
11 * This file provides support for the advanced features and bugs
12 * of IDE interfaces using the CMD Technologies 0640 IDE interface chip.
13 *
14 * These chips are basically fucked by design, and getting this driver
15 * to work on every motherboard design that uses this screwed chip seems
16 * bloody well impossible. However, we're still trying.
17 *
18 * Version 0.97 worked for everybody.
19 *
20 * User feedback is essential. Many thanks to the beta test team:
21 *
22 * A.Hartgers@stud.tue.nl, JZDQC@CUNYVM.CUNY.edu, abramov@cecmow.enet.dec.com,
23 * bardj@utopia.ppp.sn.no, bart@gaga.tue.nl, bbol001@cs.auckland.ac.nz,
24 * chrisc@dbass.demon.co.uk, dalecki@namu26.Num.Math.Uni-Goettingen.de,
25 * derekn@vw.ece.cmu.edu, florian@btp2x3.phy.uni-bayreuth.de,
26 * flynn@dei.unipd.it, gadio@netvision.net.il, godzilla@futuris.net,
27 * j@pobox.com, jkemp1@mises.uni-paderborn.de, jtoppe@hiwaay.net,
28 * kerouac@ssnet.com, meskes@informatik.rwth-aachen.de, hzoli@cs.elte.hu,
29 * peter@udgaard.isgtec.com, phil@tazenda.demon.co.uk, roadcapw@cfw.com,
30 * s0033las@sun10.vsz.bme.hu, schaffer@tam.cornell.edu, sjd@slip.net,
31 * steve@ei.org, ulrpeg@bigcomm.gun.de, ism@tardis.ed.ac.uk, mack@cray.com
32 * liug@mama.indstate.edu, and others.
33 *
34 * Version 0.01 Initial version, hacked out of ide.c,
35 * and #include'd rather than compiled separately.
36 * This will get cleaned up in a subsequent release.
37 *
38 * Version 0.02 Fixes for vlb initialization code, enable prefetch
39 * for versions 'B' and 'C' of chip by default,
40 * some code cleanup.
41 *
42 * Version 0.03 Added reset of secondary interface,
43 * and black list for devices which are not compatible
44 * with prefetch mode. Separate function for setting
45 * prefetch is added, possibly it will be called some
46 * day from ioctl processing code.
47 *
48 * Version 0.04 Now configs/compiles separate from ide.c
49 *
50 * Version 0.05 Major rewrite of interface timing code.
51 * Added new function cmd640_set_mode to set PIO mode
52 * from ioctl call. New drives added to black list.
53 *
54 * Version 0.06 More code cleanup. Prefetch is enabled only for
55 * detected hard drives, not included in prefetch
56 * black list.
57 *
58 * Version 0.07 Changed to more conservative drive tuning policy.
59 * Unknown drives, which report PIO < 4 are set to
60 * (reported_PIO - 1) if it is supported, or to PIO0.
61 * List of known drives extended by info provided by
62 * CMD at their ftp site.
63 *
64 * Version 0.08 Added autotune/noautotune support.
65 *
66 * Version 0.09 Try to be smarter about 2nd port enabling.
67 * Version 0.10 Be nice and don't reset 2nd port.
68 * Version 0.11 Try to handle more weird situations.
69 *
70 * Version 0.12 Lots of bug fixes from Laszlo Peter
71 * irq unmasking disabled for reliability.
72 * try to be even smarter about the second port.
73 * tidy up source code formatting.
74 * Version 0.13 permit irq unmasking again.
75 * Version 0.90 massive code cleanup, some bugs fixed.
76 * defaults all drives to PIO mode0, prefetch off.
77 * autotune is OFF by default, with compile time flag.
78 * prefetch can be turned OFF/ON using "hdparm -p8/-p9"
79 * (requires hdparm-3.1 or newer)
80 * Version 0.91 first release to linux-kernel list.
81 * Version 0.92 move initial reg dump to separate callable function
82 * change "readahead" to "prefetch" to avoid confusion
83 * Version 0.95 respect original BIOS timings unless autotuning.
84 * tons of code cleanup and rearrangement.
85 * added CONFIG_BLK_DEV_CMD640_ENHANCED option
86 * prevent use of unmask when prefetch is on
87 * Version 0.96 prevent use of io_32bit when prefetch is off
88 * Version 0.97 fix VLB secondary interface for sjd@slip.net
89 * other minor tune-ups: 0.96 was very good.
90 * Version 0.98 ignore PCI version when disabled by BIOS
91 * Version 0.99 display setup/active/recovery clocks with PIO mode
92 * Version 1.00 Mmm.. cannot depend on PCMD_ENA in all systems
93 * Version 1.01 slow/fast devsel can be selected with "hdparm -p6/-p7"
94 * ("fast" is necessary for 32bit I/O in some systems)
95 * Version 1.02 fix bug that resulted in slow "setup times"
96 * (patch courtesy of Zoltan Hidvegi)
97 */
98
99 #define CMD640_PREFETCH_MASKS 1
100
101 /*#define CMD640_DUMP_REGS */
102
103 #include <linux/types.h>
104 #include <linux/kernel.h>
105 #include <linux/delay.h>
106 #include <linux/hdreg.h>
107 #include <linux/ide.h>
108 #include <linux/init.h>
109
110 #include <asm/io.h>
111
112 #define DRV_NAME "cmd640"
113
114 static int cmd640_vlb;
115
116 /*
117 * CMD640 specific registers definition.
118 */
119
120 #define VID 0x00
121 #define DID 0x02
122 #define PCMD 0x04
123 #define PCMD_ENA 0x01
124 #define PSTTS 0x06
125 #define REVID 0x08
126 #define PROGIF 0x09
127 #define SUBCL 0x0a
128 #define BASCL 0x0b
129 #define BaseA0 0x10
130 #define BaseA1 0x14
131 #define BaseA2 0x18
132 #define BaseA3 0x1c
133 #define INTLINE 0x3c
134 #define INPINE 0x3d
135
136 #define CFR 0x50
137 #define CFR_DEVREV 0x03
138 #define CFR_IDE01INTR 0x04
139 #define CFR_DEVID 0x18
140 #define CFR_AT_VESA_078h 0x20
141 #define CFR_DSA1 0x40
142 #define CFR_DSA0 0x80
143
144 #define CNTRL 0x51
145 #define CNTRL_DIS_RA0 0x40
146 #define CNTRL_DIS_RA1 0x80
147 #define CNTRL_ENA_2ND 0x08
148
149 #define CMDTIM 0x52
150 #define ARTTIM0 0x53
151 #define DRWTIM0 0x54
152 #define ARTTIM1 0x55
153 #define DRWTIM1 0x56
154 #define ARTTIM23 0x57
155 #define ARTTIM23_DIS_RA2 0x04
156 #define ARTTIM23_DIS_RA3 0x08
157 #define DRWTIM23 0x58
158 #define BRST 0x59
159
160 /*
161 * Registers and masks for easy access by drive index:
162 */
163 static u8 prefetch_regs[4] = {CNTRL, CNTRL, ARTTIM23, ARTTIM23};
164 static u8 prefetch_masks[4] = {CNTRL_DIS_RA0, CNTRL_DIS_RA1, ARTTIM23_DIS_RA2, ARTTIM23_DIS_RA3};
165
166 #ifdef CONFIG_BLK_DEV_CMD640_ENHANCED
167
168 static u8 arttim_regs[4] = {ARTTIM0, ARTTIM1, ARTTIM23, ARTTIM23};
169 static u8 drwtim_regs[4] = {DRWTIM0, DRWTIM1, DRWTIM23, DRWTIM23};
170
171 /*
172 * Current cmd640 timing values for each drive.
173 * The defaults for each are the slowest possible timings.
174 */
175 static u8 setup_counts[4] = {4, 4, 4, 4}; /* Address setup count (in clocks) */
176 static u8 active_counts[4] = {16, 16, 16, 16}; /* Active count (encoded) */
177 static u8 recovery_counts[4] = {16, 16, 16, 16}; /* Recovery count (encoded) */
178
179 #endif /* CONFIG_BLK_DEV_CMD640_ENHANCED */
180
181 static DEFINE_SPINLOCK(cmd640_lock);
182
183 /*
184 * These are initialized to point at the devices we control
185 */
186 static ide_hwif_t *cmd_hwif0, *cmd_hwif1;
187
188 /*
189 * Interface to access cmd640x registers
190 */
191 static unsigned int cmd640_key;
192 static void (*__put_cmd640_reg)(u16 reg, u8 val);
193 static u8 (*__get_cmd640_reg)(u16 reg);
194
195 /*
196 * This is read from the CFR reg, and is used in several places.
197 */
198 static unsigned int cmd640_chip_version;
199
200 /*
201 * The CMD640x chip does not support DWORD config write cycles, but some
202 * of the BIOSes use them to implement the config services.
203 * Therefore, we must use direct IO instead.
204 */
205
206 /* PCI method 1 access */
207
208 static void put_cmd640_reg_pci1(u16 reg, u8 val)
209 {
210 outl_p((reg & 0xfc) | cmd640_key, 0xcf8);
211 outb_p(val, (reg & 3) | 0xcfc);
212 }
213
214 static u8 get_cmd640_reg_pci1(u16 reg)
215 {
216 outl_p((reg & 0xfc) | cmd640_key, 0xcf8);
217 return inb_p((reg & 3) | 0xcfc);
218 }
219
220 /* PCI method 2 access (from CMD datasheet) */
221
222 static void put_cmd640_reg_pci2(u16 reg, u8 val)
223 {
224 outb_p(0x10, 0xcf8);
225 outb_p(val, cmd640_key + reg);
226 outb_p(0, 0xcf8);
227 }
228
229 static u8 get_cmd640_reg_pci2(u16 reg)
230 {
231 u8 b;
232
233 outb_p(0x10, 0xcf8);
234 b = inb_p(cmd640_key + reg);
235 outb_p(0, 0xcf8);
236 return b;
237 }
238
239 /* VLB access */
240
241 static void put_cmd640_reg_vlb(u16 reg, u8 val)
242 {
243 outb_p(reg, cmd640_key);
244 outb_p(val, cmd640_key + 4);
245 }
246
247 static u8 get_cmd640_reg_vlb(u16 reg)
248 {
249 outb_p(reg, cmd640_key);
250 return inb_p(cmd640_key + 4);
251 }
252
253 static u8 get_cmd640_reg(u16 reg)
254 {
255 unsigned long flags;
256 u8 b;
257
258 spin_lock_irqsave(&cmd640_lock, flags);
259 b = __get_cmd640_reg(reg);
260 spin_unlock_irqrestore(&cmd640_lock, flags);
261 return b;
262 }
263
264 static void put_cmd640_reg(u16 reg, u8 val)
265 {
266 unsigned long flags;
267
268 spin_lock_irqsave(&cmd640_lock, flags);
269 __put_cmd640_reg(reg, val);
270 spin_unlock_irqrestore(&cmd640_lock, flags);
271 }
272
273 static int __init match_pci_cmd640_device(void)
274 {
275 const u8 ven_dev[4] = {0x95, 0x10, 0x40, 0x06};
276 unsigned int i;
277 for (i = 0; i < 4; i++) {
278 if (get_cmd640_reg(i) != ven_dev[i])
279 return 0;
280 }
281 #ifdef STUPIDLY_TRUST_BROKEN_PCMD_ENA_BIT
282 if ((get_cmd640_reg(PCMD) & PCMD_ENA) == 0) {
283 printk("ide: cmd640 on PCI disabled by BIOS\n");
284 return 0;
285 }
286 #endif /* STUPIDLY_TRUST_BROKEN_PCMD_ENA_BIT */
287 return 1; /* success */
288 }
289
290 /*
291 * Probe for CMD640x -- pci method 1
292 */
293 static int __init probe_for_cmd640_pci1(void)
294 {
295 __get_cmd640_reg = get_cmd640_reg_pci1;
296 __put_cmd640_reg = put_cmd640_reg_pci1;
297 for (cmd640_key = 0x80000000;
298 cmd640_key <= 0x8000f800;
299 cmd640_key += 0x800) {
300 if (match_pci_cmd640_device())
301 return 1; /* success */
302 }
303 return 0;
304 }
305
306 /*
307 * Probe for CMD640x -- pci method 2
308 */
309 static int __init probe_for_cmd640_pci2(void)
310 {
311 __get_cmd640_reg = get_cmd640_reg_pci2;
312 __put_cmd640_reg = put_cmd640_reg_pci2;
313 for (cmd640_key = 0xc000; cmd640_key <= 0xcf00; cmd640_key += 0x100) {
314 if (match_pci_cmd640_device())
315 return 1; /* success */
316 }
317 return 0;
318 }
319
320 /*
321 * Probe for CMD640x -- vlb
322 */
323 static int __init probe_for_cmd640_vlb(void)
324 {
325 u8 b;
326
327 __get_cmd640_reg = get_cmd640_reg_vlb;
328 __put_cmd640_reg = put_cmd640_reg_vlb;
329 cmd640_key = 0x178;
330 b = get_cmd640_reg(CFR);
331 if (b == 0xff || b == 0x00 || (b & CFR_AT_VESA_078h)) {
332 cmd640_key = 0x78;
333 b = get_cmd640_reg(CFR);
334 if (b == 0xff || b == 0x00 || !(b & CFR_AT_VESA_078h))
335 return 0;
336 }
337 return 1; /* success */
338 }
339
340 /*
341 * Returns 1 if an IDE interface/drive exists at 0x170,
342 * Returns 0 otherwise.
343 */
344 static int __init secondary_port_responding(void)
345 {
346 unsigned long flags;
347
348 spin_lock_irqsave(&cmd640_lock, flags);
349
350 outb_p(0x0a, 0x176); /* select drive0 */
351 udelay(100);
352 if ((inb_p(0x176) & 0x1f) != 0x0a) {
353 outb_p(0x1a, 0x176); /* select drive1 */
354 udelay(100);
355 if ((inb_p(0x176) & 0x1f) != 0x1a) {
356 spin_unlock_irqrestore(&cmd640_lock, flags);
357 return 0; /* nothing responded */
358 }
359 }
360 spin_unlock_irqrestore(&cmd640_lock, flags);
361 return 1; /* success */
362 }
363
364 #ifdef CMD640_DUMP_REGS
365 /*
366 * Dump out all cmd640 registers. May be called from ide.c
367 */
368 static void cmd640_dump_regs(void)
369 {
370 unsigned int reg = cmd640_vlb ? 0x50 : 0x00;
371
372 /* Dump current state of chip registers */
373 printk("ide: cmd640 internal register dump:");
374 for (; reg <= 0x59; reg++) {
375 if (!(reg & 0x0f))
376 printk("\n%04x:", reg);
377 printk(" %02x", get_cmd640_reg(reg));
378 }
379 printk("\n");
380 }
381 #endif
382
383 #ifndef CONFIG_BLK_DEV_CMD640_ENHANCED
384 /*
385 * Check whether prefetch is on for a drive,
386 * and initialize the unmask flags for safe operation.
387 */
388 static void __init check_prefetch(ide_drive_t *drive, unsigned int index)
389 {
390 u8 b = get_cmd640_reg(prefetch_regs[index]);
391
392 if (b & prefetch_masks[index]) { /* is prefetch off? */
393 drive->no_unmask = 0;
394 drive->no_io_32bit = 1;
395 drive->io_32bit = 0;
396 } else {
397 #if CMD640_PREFETCH_MASKS
398 drive->no_unmask = 1;
399 drive->unmask = 0;
400 #endif
401 drive->no_io_32bit = 0;
402 }
403 }
404 #else
405 /*
406 * Sets prefetch mode for a drive.
407 */
408 static void set_prefetch_mode(ide_drive_t *drive, unsigned int index, int mode)
409 {
410 unsigned long flags;
411 int reg = prefetch_regs[index];
412 u8 b;
413
414 spin_lock_irqsave(&cmd640_lock, flags);
415 b = __get_cmd640_reg(reg);
416 if (mode) { /* want prefetch on? */
417 #if CMD640_PREFETCH_MASKS
418 drive->no_unmask = 1;
419 drive->unmask = 0;
420 #endif
421 drive->no_io_32bit = 0;
422 b &= ~prefetch_masks[index]; /* enable prefetch */
423 } else {
424 drive->no_unmask = 0;
425 drive->no_io_32bit = 1;
426 drive->io_32bit = 0;
427 b |= prefetch_masks[index]; /* disable prefetch */
428 }
429 __put_cmd640_reg(reg, b);
430 spin_unlock_irqrestore(&cmd640_lock, flags);
431 }
432
433 /*
434 * Dump out current drive clocks settings
435 */
436 static void display_clocks(unsigned int index)
437 {
438 u8 active_count, recovery_count;
439
440 active_count = active_counts[index];
441 if (active_count == 1)
442 ++active_count;
443 recovery_count = recovery_counts[index];
444 if (active_count > 3 && recovery_count == 1)
445 ++recovery_count;
446 if (cmd640_chip_version > 1)
447 recovery_count += 1; /* cmd640b uses (count + 1)*/
448 printk(", clocks=%d/%d/%d\n", setup_counts[index], active_count, recovery_count);
449 }
450
451 /*
452 * Pack active and recovery counts into single byte representation
453 * used by controller
454 */
455 static inline u8 pack_nibbles(u8 upper, u8 lower)
456 {
457 return ((upper & 0x0f) << 4) | (lower & 0x0f);
458 }
459
460 /*
461 * This routine writes the prepared setup/active/recovery counts
462 * for a drive into the cmd640 chipset registers to active them.
463 */
464 static void program_drive_counts(ide_drive_t *drive, unsigned int index)
465 {
466 unsigned long flags;
467 u8 setup_count = setup_counts[index];
468 u8 active_count = active_counts[index];
469 u8 recovery_count = recovery_counts[index];
470
471 /*
472 * Set up address setup count and drive read/write timing registers.
473 * Primary interface has individual count/timing registers for
474 * each drive. Secondary interface has one common set of registers,
475 * so we merge the timings, using the slowest value for each timing.
476 */
477 if (index > 1) {
478 ide_hwif_t *hwif = drive->hwif;
479 ide_drive_t *peer = &hwif->drives[!drive->select.b.unit];
480 unsigned int mate = index ^ 1;
481
482 if (peer->present) {
483 if (setup_count < setup_counts[mate])
484 setup_count = setup_counts[mate];
485 if (active_count < active_counts[mate])
486 active_count = active_counts[mate];
487 if (recovery_count < recovery_counts[mate])
488 recovery_count = recovery_counts[mate];
489 }
490 }
491
492 /*
493 * Convert setup_count to internal chipset representation
494 */
495 switch (setup_count) {
496 case 4: setup_count = 0x00; break;
497 case 3: setup_count = 0x80; break;
498 case 1:
499 case 2: setup_count = 0x40; break;
500 default: setup_count = 0xc0; /* case 5 */
501 }
502
503 /*
504 * Now that everything is ready, program the new timings
505 */
506 spin_lock_irqsave(&cmd640_lock, flags);
507 /*
508 * Program the address_setup clocks into ARTTIM reg,
509 * and then the active/recovery counts into the DRWTIM reg
510 * (this converts counts of 16 into counts of zero -- okay).
511 */
512 setup_count |= __get_cmd640_reg(arttim_regs[index]) & 0x3f;
513 __put_cmd640_reg(arttim_regs[index], setup_count);
514 __put_cmd640_reg(drwtim_regs[index], pack_nibbles(active_count, recovery_count));
515 spin_unlock_irqrestore(&cmd640_lock, flags);
516 }
517
518 /*
519 * Set a specific pio_mode for a drive
520 */
521 static void cmd640_set_mode(ide_drive_t *drive, unsigned int index,
522 u8 pio_mode, unsigned int cycle_time)
523 {
524 int setup_time, active_time, recovery_time, clock_time;
525 u8 setup_count, active_count, recovery_count, recovery_count2, cycle_count;
526 int bus_speed;
527
528 if (cmd640_vlb && ide_vlb_clk)
529 bus_speed = ide_vlb_clk;
530 else if (!cmd640_vlb && ide_pci_clk)
531 bus_speed = ide_pci_clk;
532 else
533 bus_speed = system_bus_clock();
534
535 if (pio_mode > 5)
536 pio_mode = 5;
537 setup_time = ide_pio_timings[pio_mode].setup_time;
538 active_time = ide_pio_timings[pio_mode].active_time;
539 recovery_time = cycle_time - (setup_time + active_time);
540 clock_time = 1000 / bus_speed;
541 cycle_count = DIV_ROUND_UP(cycle_time, clock_time);
542
543 setup_count = DIV_ROUND_UP(setup_time, clock_time);
544
545 active_count = DIV_ROUND_UP(active_time, clock_time);
546 if (active_count < 2)
547 active_count = 2; /* minimum allowed by cmd640 */
548
549 recovery_count = DIV_ROUND_UP(recovery_time, clock_time);
550 recovery_count2 = cycle_count - (setup_count + active_count);
551 if (recovery_count2 > recovery_count)
552 recovery_count = recovery_count2;
553 if (recovery_count < 2)
554 recovery_count = 2; /* minimum allowed by cmd640 */
555 if (recovery_count > 17) {
556 active_count += recovery_count - 17;
557 recovery_count = 17;
558 }
559 if (active_count > 16)
560 active_count = 16; /* maximum allowed by cmd640 */
561 if (cmd640_chip_version > 1)
562 recovery_count -= 1; /* cmd640b uses (count + 1)*/
563 if (recovery_count > 16)
564 recovery_count = 16; /* maximum allowed by cmd640 */
565
566 setup_counts[index] = setup_count;
567 active_counts[index] = active_count;
568 recovery_counts[index] = recovery_count;
569
570 /*
571 * In a perfect world, we might set the drive pio mode here
572 * (using WIN_SETFEATURE) before continuing.
573 *
574 * But we do not, because:
575 * 1) this is the wrong place to do it (proper is do_special() in ide.c)
576 * 2) in practice this is rarely, if ever, necessary
577 */
578 program_drive_counts(drive, index);
579 }
580
581 static void cmd640_set_pio_mode(ide_drive_t *drive, const u8 pio)
582 {
583 unsigned int index = 0, cycle_time;
584 u8 b;
585
586 switch (pio) {
587 case 6: /* set fast-devsel off */
588 case 7: /* set fast-devsel on */
589 b = get_cmd640_reg(CNTRL) & ~0x27;
590 if (pio & 1)
591 b |= 0x27;
592 put_cmd640_reg(CNTRL, b);
593 printk("%s: %sabled cmd640 fast host timing (devsel)\n",
594 drive->name, (pio & 1) ? "en" : "dis");
595 return;
596 case 8: /* set prefetch off */
597 case 9: /* set prefetch on */
598 set_prefetch_mode(drive, index, pio & 1);
599 printk("%s: %sabled cmd640 prefetch\n",
600 drive->name, (pio & 1) ? "en" : "dis");
601 return;
602 }
603
604 cycle_time = ide_pio_cycle_time(drive, pio);
605 cmd640_set_mode(drive, index, pio, cycle_time);
606
607 printk("%s: selected cmd640 PIO mode%d (%dns)",
608 drive->name, pio, cycle_time);
609
610 display_clocks(index);
611 }
612
613 static const struct ide_port_ops cmd640_port_ops = {
614 .set_pio_mode = cmd640_set_pio_mode,
615 };
616 #endif /* CONFIG_BLK_DEV_CMD640_ENHANCED */
617
618 static int pci_conf1(void)
619 {
620 unsigned long flags;
621 u32 tmp;
622
623 spin_lock_irqsave(&cmd640_lock, flags);
624 outb(0x01, 0xCFB);
625 tmp = inl(0xCF8);
626 outl(0x80000000, 0xCF8);
627 if (inl(0xCF8) == 0x80000000) {
628 outl(tmp, 0xCF8);
629 spin_unlock_irqrestore(&cmd640_lock, flags);
630 return 1;
631 }
632 outl(tmp, 0xCF8);
633 spin_unlock_irqrestore(&cmd640_lock, flags);
634 return 0;
635 }
636
637 static int pci_conf2(void)
638 {
639 unsigned long flags;
640
641 spin_lock_irqsave(&cmd640_lock, flags);
642 outb(0x00, 0xCFB);
643 outb(0x00, 0xCF8);
644 outb(0x00, 0xCFA);
645 if (inb(0xCF8) == 0x00 && inb(0xCF8) == 0x00) {
646 spin_unlock_irqrestore(&cmd640_lock, flags);
647 return 1;
648 }
649 spin_unlock_irqrestore(&cmd640_lock, flags);
650 return 0;
651 }
652
653 static const struct ide_port_info cmd640_port_info __initdata = {
654 .chipset = ide_cmd640,
655 .host_flags = IDE_HFLAG_SERIALIZE |
656 IDE_HFLAG_NO_DMA |
657 IDE_HFLAG_ABUSE_PREFETCH |
658 IDE_HFLAG_ABUSE_FAST_DEVSEL,
659 #ifdef CONFIG_BLK_DEV_CMD640_ENHANCED
660 .port_ops = &cmd640_port_ops,
661 .pio_mask = ATA_PIO5,
662 #endif
663 };
664
665 static int cmd640x_init_one(unsigned long base, unsigned long ctl)
666 {
667 if (!request_region(base, 8, DRV_NAME)) {
668 printk(KERN_ERR "%s: I/O resource 0x%lX-0x%lX not free.\n",
669 DRV_NAME, base, base + 7);
670 return -EBUSY;
671 }
672
673 if (!request_region(ctl, 1, DRV_NAME)) {
674 printk(KERN_ERR "%s: I/O resource 0x%lX not free.\n",
675 DRV_NAME, ctl);
676 release_region(base, 8);
677 return -EBUSY;
678 }
679
680 return 0;
681 }
682
683 /*
684 * Probe for a cmd640 chipset, and initialize it if found.
685 */
686 static int __init cmd640x_init(void)
687 {
688 #ifdef CONFIG_BLK_DEV_CMD640_ENHANCED
689 int second_port_toggled = 0;
690 #endif /* CONFIG_BLK_DEV_CMD640_ENHANCED */
691 int second_port_cmd640 = 0, rc;
692 const char *bus_type, *port2;
693 unsigned int index;
694 u8 b, cfr;
695 u8 idx[4] = { 0xff, 0xff, 0xff, 0xff };
696 hw_regs_t hw[2];
697
698 if (cmd640_vlb && probe_for_cmd640_vlb()) {
699 bus_type = "VLB";
700 } else {
701 cmd640_vlb = 0;
702 /* Find out what kind of PCI probing is supported otherwise
703 Justin Gibbs will sulk.. */
704 if (pci_conf1() && probe_for_cmd640_pci1())
705 bus_type = "PCI (type1)";
706 else if (pci_conf2() && probe_for_cmd640_pci2())
707 bus_type = "PCI (type2)";
708 else
709 return 0;
710 }
711 /*
712 * Undocumented magic (there is no 0x5b reg in specs)
713 */
714 put_cmd640_reg(0x5b, 0xbd);
715 if (get_cmd640_reg(0x5b) != 0xbd) {
716 printk(KERN_ERR "ide: cmd640 init failed: wrong value in reg 0x5b\n");
717 return 0;
718 }
719 put_cmd640_reg(0x5b, 0);
720
721 #ifdef CMD640_DUMP_REGS
722 cmd640_dump_regs();
723 #endif
724
725 /*
726 * Documented magic begins here
727 */
728 cfr = get_cmd640_reg(CFR);
729 cmd640_chip_version = cfr & CFR_DEVREV;
730 if (cmd640_chip_version == 0) {
731 printk("ide: bad cmd640 revision: %d\n", cmd640_chip_version);
732 return 0;
733 }
734
735 rc = cmd640x_init_one(0x1f0, 0x3f6);
736 if (rc)
737 return rc;
738
739 rc = cmd640x_init_one(0x170, 0x376);
740 if (rc) {
741 release_region(0x3f6, 1);
742 release_region(0x1f0, 8);
743 return rc;
744 }
745
746 memset(&hw, 0, sizeof(hw));
747
748 ide_std_init_ports(&hw[0], 0x1f0, 0x3f6);
749 hw[0].irq = 14;
750
751 ide_std_init_ports(&hw[1], 0x170, 0x376);
752 hw[1].irq = 15;
753
754 printk(KERN_INFO "cmd640: buggy cmd640%c interface on %s, config=0x%02x"
755 "\n", 'a' + cmd640_chip_version - 1, bus_type, cfr);
756
757 cmd_hwif0 = ide_find_port();
758
759 /*
760 * Initialize data for primary port
761 */
762 if (cmd_hwif0) {
763 ide_init_port_hw(cmd_hwif0, &hw[0]);
764 idx[0] = cmd_hwif0->index;
765 }
766
767 /*
768 * Ensure compatibility by always using the slowest timings
769 * for access to the drive's command register block,
770 * and reset the prefetch burstsize to default (512 bytes).
771 *
772 * Maybe we need a way to NOT do these on *some* systems?
773 */
774 put_cmd640_reg(CMDTIM, 0);
775 put_cmd640_reg(BRST, 0x40);
776
777 cmd_hwif1 = ide_find_port();
778
779 /*
780 * Try to enable the secondary interface, if not already enabled
781 */
782 if (cmd_hwif1 &&
783 cmd_hwif1->drives[0].noprobe && cmd_hwif1->drives[1].noprobe) {
784 port2 = "not probed";
785 } else {
786 b = get_cmd640_reg(CNTRL);
787 if (secondary_port_responding()) {
788 if ((b & CNTRL_ENA_2ND)) {
789 second_port_cmd640 = 1;
790 port2 = "okay";
791 } else if (cmd640_vlb) {
792 second_port_cmd640 = 1;
793 port2 = "alive";
794 } else
795 port2 = "not cmd640";
796 } else {
797 put_cmd640_reg(CNTRL, b ^ CNTRL_ENA_2ND); /* toggle the bit */
798 if (secondary_port_responding()) {
799 second_port_cmd640 = 1;
800 #ifdef CONFIG_BLK_DEV_CMD640_ENHANCED
801 second_port_toggled = 1;
802 #endif /* CONFIG_BLK_DEV_CMD640_ENHANCED */
803 port2 = "enabled";
804 } else {
805 put_cmd640_reg(CNTRL, b); /* restore original setting */
806 port2 = "not responding";
807 }
808 }
809 }
810
811 /*
812 * Initialize data for secondary cmd640 port, if enabled
813 */
814 if (second_port_cmd640 && cmd_hwif1) {
815 ide_init_port_hw(cmd_hwif1, &hw[1]);
816 idx[1] = cmd_hwif1->index;
817 }
818 printk(KERN_INFO "cmd640: %sserialized, secondary interface %s\n",
819 second_port_cmd640 ? "" : "not ", port2);
820
821 /*
822 * Establish initial timings/prefetch for all drives.
823 * Do not unnecessarily disturb any prior BIOS setup of these.
824 */
825 for (index = 0; index < (2 + (second_port_cmd640 << 1)); index++) {
826 ide_drive_t *drive;
827
828 if (index > 1) {
829 if (cmd_hwif1 == NULL)
830 continue;
831 drive = &cmd_hwif1->drives[index & 1];
832 } else {
833 if (cmd_hwif0 == NULL)
834 continue;
835 drive = &cmd_hwif0->drives[index & 1];
836 }
837
838 #ifdef CONFIG_BLK_DEV_CMD640_ENHANCED
839 /*
840 * Reset timing to the slowest speed and turn off prefetch.
841 * This way, the drive identify code has a better chance.
842 */
843 setup_counts [index] = 4; /* max possible */
844 active_counts [index] = 16; /* max possible */
845 recovery_counts [index] = 16; /* max possible */
846 program_drive_counts(drive, index);
847 set_prefetch_mode(drive, index, 0);
848 printk("cmd640: drive%d timings/prefetch cleared\n", index);
849 #else
850 /*
851 * Set the drive unmask flags to match the prefetch setting
852 */
853 check_prefetch(drive, index);
854 printk("cmd640: drive%d timings/prefetch(%s) preserved\n",
855 index, drive->no_io_32bit ? "off" : "on");
856 #endif /* CONFIG_BLK_DEV_CMD640_ENHANCED */
857 }
858
859 #ifdef CMD640_DUMP_REGS
860 cmd640_dump_regs();
861 #endif
862
863 ide_device_add(idx, &cmd640_port_info);
864
865 return 1;
866 }
867
868 module_param_named(probe_vlb, cmd640_vlb, bool, 0);
869 MODULE_PARM_DESC(probe_vlb, "probe for VLB version of CMD640 chipset");
870
871 module_init(cmd640x_init);
872
873 MODULE_LICENSE("GPL");