2 * linux/drivers/ide/pci/cs5535.c
4 * Copyright (C) 2004-2005 Advanced Micro Devices, Inc.
7 * 09/20/2005 - Jaya Kumar <jayakumar.ide@gmail.com>
8 * - Reworked tuneproc, set_drive, misc mods to prep for mainline
9 * - Work was sponsored by CIS (M) Sdn Bhd.
10 * Ported to Kernel 2.6.11 on June 26, 2005 by
11 * Wolfgang Zuleger <wolfgang.zuleger@gmx.de>
12 * Alexander Kiausch <alex.kiausch@t-online.de>
13 * Originally developed by AMD for 2.4/2.6
15 * Development of this chipset driver was funded
16 * by the nice folks at National Semiconductor/AMD.
18 * This program is free software; you can redistribute it and/or modify it
19 * under the terms of the GNU General Public License version 2 as published by
20 * the Free Software Foundation.
23 * CS5535 documentation available from AMD
26 #include <linux/module.h>
27 #include <linux/pci.h>
28 #include <linux/ide.h>
30 #include "ide-timing.h"
32 #define MSR_ATAC_BASE 0x51300000
33 #define ATAC_GLD_MSR_CAP (MSR_ATAC_BASE+0)
34 #define ATAC_GLD_MSR_CONFIG (MSR_ATAC_BASE+0x01)
35 #define ATAC_GLD_MSR_SMI (MSR_ATAC_BASE+0x02)
36 #define ATAC_GLD_MSR_ERROR (MSR_ATAC_BASE+0x03)
37 #define ATAC_GLD_MSR_PM (MSR_ATAC_BASE+0x04)
38 #define ATAC_GLD_MSR_DIAG (MSR_ATAC_BASE+0x05)
39 #define ATAC_IO_BAR (MSR_ATAC_BASE+0x08)
40 #define ATAC_RESET (MSR_ATAC_BASE+0x10)
41 #define ATAC_CH0D0_PIO (MSR_ATAC_BASE+0x20)
42 #define ATAC_CH0D0_DMA (MSR_ATAC_BASE+0x21)
43 #define ATAC_CH0D1_PIO (MSR_ATAC_BASE+0x22)
44 #define ATAC_CH0D1_DMA (MSR_ATAC_BASE+0x23)
45 #define ATAC_PCI_ABRTERR (MSR_ATAC_BASE+0x24)
46 #define ATAC_BM0_CMD_PRIM 0x00
47 #define ATAC_BM0_STS_PRIM 0x02
48 #define ATAC_BM0_PRD 0x04
49 #define CS5535_CABLE_DETECT 0x48
51 /* Format I PIO settings. We seperate out cmd and data for safer timings */
53 static unsigned int cs5535_pio_cmd_timings
[5] =
54 { 0xF7F4, 0x53F3, 0x13F1, 0x5131, 0x1131 };
55 static unsigned int cs5535_pio_dta_timings
[5] =
56 { 0xF7F4, 0xF173, 0x8141, 0x5131, 0x1131 };
58 static unsigned int cs5535_mwdma_timings
[3] =
59 { 0x7F0FFFF3, 0x7F035352, 0x7f024241 };
61 static unsigned int cs5535_udma_timings
[5] =
62 { 0x7F7436A1, 0x7F733481, 0x7F723261, 0x7F713161, 0x7F703061 };
64 /* Macros to check if the register is the reset value - reset value is an
65 invalid timing and indicates the register has not been set previously */
67 #define CS5535_BAD_PIO(timings) ( (timings&~0x80000000UL) == 0x00009172 )
68 #define CS5535_BAD_DMA(timings) ( (timings & 0x000FFFFF) == 0x00077771 )
71 * cs5535_set_speed - Configure the chipset to the new speed
72 * @drive: Drive to set up
73 * @speed: desired speed
75 * cs5535_set_speed() configures the chipset to a new speed.
77 static void cs5535_set_speed(ide_drive_t
*drive
, u8 speed
)
81 int unit
= drive
->select
.b
.unit
;
84 /* Set the PIO timings */
85 if ((speed
& XFER_MODE
) == XFER_PIO
) {
90 pioa
= speed
- XFER_PIO_0
;
91 piob
= ide_get_best_pio_mode(&(drive
->hwif
->drives
[!unit
]),
93 cmd
= pioa
< piob
? pioa
: piob
;
95 /* Write the speed of the current drive */
96 reg
= (cs5535_pio_cmd_timings
[cmd
] << 16) |
97 cs5535_pio_dta_timings
[pioa
];
98 wrmsr(unit
? ATAC_CH0D1_PIO
: ATAC_CH0D0_PIO
, reg
, 0);
100 /* And if nessesary - change the speed of the other drive */
101 rdmsr(unit
? ATAC_CH0D0_PIO
: ATAC_CH0D1_PIO
, reg
, dummy
);
103 if (((reg
>> 16) & cs5535_pio_cmd_timings
[cmd
]) !=
104 cs5535_pio_cmd_timings
[cmd
]) {
106 reg
|= cs5535_pio_cmd_timings
[cmd
] << 16;
107 wrmsr(unit
? ATAC_CH0D0_PIO
: ATAC_CH0D1_PIO
, reg
, 0);
110 /* Set bit 31 of the DMA register for PIO format 1 timings */
111 rdmsr(unit
? ATAC_CH0D1_DMA
: ATAC_CH0D0_DMA
, reg
, dummy
);
112 wrmsr(unit
? ATAC_CH0D1_DMA
: ATAC_CH0D0_DMA
,
113 reg
| 0x80000000UL
, 0);
115 rdmsr(unit
? ATAC_CH0D1_DMA
: ATAC_CH0D0_DMA
, reg
, dummy
);
117 reg
&= 0x80000000UL
; /* Preserve the PIO format bit */
119 if (speed
>= XFER_UDMA_0
&& speed
<= XFER_UDMA_7
)
120 reg
|= cs5535_udma_timings
[speed
- XFER_UDMA_0
];
121 else if (speed
>= XFER_MW_DMA_0
&& speed
<= XFER_MW_DMA_2
)
122 reg
|= cs5535_mwdma_timings
[speed
- XFER_MW_DMA_0
];
126 wrmsr(unit
? ATAC_CH0D1_DMA
: ATAC_CH0D0_DMA
, reg
, 0);
131 * cs5535_set_drive - Configure the drive to the new speed
132 * @drive: Drive to set up
133 * @speed: desired speed
135 * cs5535_set_drive() configures the drive and the chipset to a
136 * new speed. It also can be called by upper layers.
138 static int cs5535_set_drive(ide_drive_t
*drive
, u8 speed
)
140 speed
= ide_rate_filter(drive
, speed
);
141 ide_config_drive_speed(drive
, speed
);
142 cs5535_set_speed(drive
, speed
);
148 * cs5535_tuneproc - PIO setup
149 * @drive: drive to set up
150 * @pio: mode to use (255 for 'best possible')
152 * A callback from the upper layers for PIO-only tuning.
154 static void cs5535_tuneproc(ide_drive_t
*drive
, u8 xferspeed
)
156 u8 modes
[] = { XFER_PIO_0
, XFER_PIO_1
, XFER_PIO_2
, XFER_PIO_3
,
159 /* cs5535 max pio is pio 4, best_pio will check the blacklist.
160 i think we don't need to rate_filter the incoming xferspeed
161 since we know we're only going to choose pio */
162 xferspeed
= ide_get_best_pio_mode(drive
, xferspeed
, 4, NULL
);
163 ide_config_drive_speed(drive
, modes
[xferspeed
]);
164 cs5535_set_speed(drive
, xferspeed
);
167 static int cs5535_dma_check(ide_drive_t
*drive
)
171 drive
->init_speed
= 0;
173 if (ide_tune_dma(drive
))
176 if (ide_use_fast_pio(drive
)) {
177 speed
= ide_get_best_pio_mode(drive
, 255, 4, NULL
);
178 cs5535_set_drive(drive
, speed
);
184 static u8 __devinit
cs5535_cable_detect(struct pci_dev
*dev
)
188 /* if a 80 wire cable was detected */
189 pci_read_config_byte(dev
, CS5535_CABLE_DETECT
, &bit
);
191 return (bit
& 1) ? ATA_CBL_PATA80
: ATA_CBL_PATA40
;
195 * init_hwif_cs5535 - Initialize one ide cannel
196 * @hwif: Channel descriptor
198 * This gets invoked by the IDE driver once for each channel. It
199 * performs channel-specific pre-initialization before drive probing.
202 static void __devinit
init_hwif_cs5535(ide_hwif_t
*hwif
)
208 hwif
->tuneproc
= &cs5535_tuneproc
;
209 hwif
->speedproc
= &cs5535_set_drive
;
210 hwif
->ide_dma_check
= &cs5535_dma_check
;
213 hwif
->ultra_mask
= 0x1F;
214 hwif
->mwdma_mask
= 0x07;
216 hwif
->cbl
= cs5535_cable_detect(hwif
->pci_dev
);
221 /* just setting autotune and not worrying about bios timings */
222 for (i
= 0; i
< 2; i
++) {
223 hwif
->drives
[i
].autotune
= 1;
224 hwif
->drives
[i
].autodma
= hwif
->autodma
;
228 static ide_pci_device_t cs5535_chipset __devinitdata
= {
230 .init_hwif
= init_hwif_cs5535
,
233 .bootable
= ON_BOARD
,
236 static int __devinit
cs5535_init_one(struct pci_dev
*dev
,
237 const struct pci_device_id
*id
)
239 return ide_setup_pci_device(dev
, &cs5535_chipset
);
242 static struct pci_device_id cs5535_pci_tbl
[] =
244 { PCI_VENDOR_ID_NS
, PCI_DEVICE_ID_NS_CS5535_IDE
, PCI_ANY_ID
,
245 PCI_ANY_ID
, 0, 0, 0},
249 MODULE_DEVICE_TABLE(pci
, cs5535_pci_tbl
);
251 static struct pci_driver driver
= {
252 .name
= "CS5535_IDE",
253 .id_table
= cs5535_pci_tbl
,
254 .probe
= cs5535_init_one
,
257 static int __init
cs5535_ide_init(void)
259 return ide_pci_register_driver(&driver
);
262 module_init(cs5535_ide_init
);
264 MODULE_AUTHOR("AMD");
265 MODULE_DESCRIPTION("PCI driver module for AMD/NS CS5535 IDE");
266 MODULE_LICENSE("GPL");