drivers/ide/pci/pdc202xx_new.c

   1 /*
   2  *  Promise TX2/TX4/TX2000/133 IDE driver
   3  *
   4  *  This program is free software; you can redistribute it and/or
   5  *  modify it under the terms of the GNU General Public License
   6  *  as published by the Free Software Foundation; either version
   7  *  2 of the License, or (at your option) any later version.
   8  *
   9  *  Split from:
  10  *  linux/drivers/ide/pdc202xx.c        Version 0.35    Mar. 30, 2002
  11  *  Copyright (C) 1998-2002             Andre Hedrick <andre@linux-ide.org>
  12  *  Copyright (C) 2005-2007             MontaVista Software, Inc.
  13  *  Portions Copyright (C) 1999 Promise Technology, Inc.
  14  *  Author: Frank Tiernan (frankt@promise.com)
  15  *  Released under terms of General Public License
  16  */
  17
  18 #include <linux/module.h>
  19 #include <linux/types.h>
  20 #include <linux/kernel.h>
  21 #include <linux/delay.h>
  22 #include <linux/timer.h>
  23 #include <linux/mm.h>
  24 #include <linux/ioport.h>
  25 #include <linux/blkdev.h>
  26 #include <linux/hdreg.h>
  27 #include <linux/interrupt.h>
  28 #include <linux/pci.h>
  29 #include <linux/init.h>
  30 #include <linux/ide.h>
  31
  32 #include <asm/io.h>
  33 #include <asm/irq.h>
  34
  35 #ifdef CONFIG_PPC_PMAC
  36 #include <asm/prom.h>
  37 #include <asm/pci-bridge.h>
  38 #endif
  39
  40 #undef DEBUG
  41
  42 #ifdef DEBUG
  43 #define DBG(fmt, args...) printk("%s: " fmt, __FUNCTION__, ## args)
  44 #else
  45 #define DBG(fmt, args...)
  46 #endif
  47
  48 static const char *pdc_quirk_drives[] = {
  49         "QUANTUM FIREBALLlct08 08",
  50         "QUANTUM FIREBALLP KA6.4",
  51         "QUANTUM FIREBALLP KA9.1",
  52         "QUANTUM FIREBALLP LM20.4",
  53         "QUANTUM FIREBALLP KX13.6",
  54         "QUANTUM FIREBALLP KX20.5",
  55         "QUANTUM FIREBALLP KX27.3",
  56         "QUANTUM FIREBALLP LM20.5",
  57         NULL
  58 };
  59
  60 static u8 max_dma_rate(struct pci_dev *pdev)
  61 {
  62         u8 mode;
  63
  64         switch(pdev->device) {
  65                 case PCI_DEVICE_ID_PROMISE_20277:
  66                 case PCI_DEVICE_ID_PROMISE_20276:
  67                 case PCI_DEVICE_ID_PROMISE_20275:
  68                 case PCI_DEVICE_ID_PROMISE_20271:
  69                 case PCI_DEVICE_ID_PROMISE_20269:
  70                         mode = 4;
  71                         break;
  72                 case PCI_DEVICE_ID_PROMISE_20270:
  73                 case PCI_DEVICE_ID_PROMISE_20268:
  74                         mode = 3;
  75                         break;
  76                 default:
  77                         return 0;
  78         }
  79
  80         return mode;
  81 }
  82
  83 /**
  84  * get_indexed_reg - Get indexed register
  85  * @hwif: for the port address
  86  * @index: index of the indexed register
  87  */
  88 static u8 get_indexed_reg(ide_hwif_t *hwif, u8 index)
  89 {
  90         u8 value;
  91
  92         outb(index, hwif->dma_vendor1);
  93         value = inb(hwif->dma_vendor3);
  94
  95         DBG("index[%02X] value[%02X]\n", index, value);
  96         return value;
  97 }
  98
  99 /**
 100  * set_indexed_reg - Set indexed register
 101  * @hwif: for the port address
 102  * @index: index of the indexed register
 103  */
 104 static void set_indexed_reg(ide_hwif_t *hwif, u8 index, u8 value)
 105 {
 106         outb(index, hwif->dma_vendor1);
 107         outb(value, hwif->dma_vendor3);
 108         DBG("index[%02X] value[%02X]\n", index, value);
 109 }
 110
 111 /*
 112  * ATA Timing Tables based on 133 MHz PLL output clock.
 113  *
 114  * If the PLL outputs 100 MHz clock, the ASIC hardware will set
 115  * the timing registers automatically when "set features" command is
 116  * issued to the device. However, if the PLL output clock is 133 MHz,
 117  * the following tables must be used.
 118  */
 119 static struct pio_timing {
 120         u8 reg0c, reg0d, reg13;
 121 } pio_timings [] = {
 122         { 0xfb, 0x2b, 0xac },   /* PIO mode 0, IORDY off, Prefetch off */
 123         { 0x46, 0x29, 0xa4 },   /* PIO mode 1, IORDY off, Prefetch off */
 124         { 0x23, 0x26, 0x64 },   /* PIO mode 2, IORDY off, Prefetch off */
 125         { 0x27, 0x0d, 0x35 },   /* PIO mode 3, IORDY on,  Prefetch off */
 126         { 0x23, 0x09, 0x25 },   /* PIO mode 4, IORDY on,  Prefetch off */
 127 };
 128
 129 static struct mwdma_timing {
 130         u8 reg0e, reg0f;
 131 } mwdma_timings [] = {
 132         { 0xdf, 0x5f },         /* MWDMA mode 0 */
 133         { 0x6b, 0x27 },         /* MWDMA mode 1 */
 134         { 0x69, 0x25 },         /* MWDMA mode 2 */
 135 };
 136
 137 static struct udma_timing {
 138         u8 reg10, reg11, reg12;
 139 } udma_timings [] = {
 140         { 0x4a, 0x0f, 0xd5 },   /* UDMA mode 0 */
 141         { 0x3a, 0x0a, 0xd0 },   /* UDMA mode 1 */
 142         { 0x2a, 0x07, 0xcd },   /* UDMA mode 2 */
 143         { 0x1a, 0x05, 0xcd },   /* UDMA mode 3 */
 144         { 0x1a, 0x03, 0xcd },   /* UDMA mode 4 */
 145         { 0x1a, 0x02, 0xcb },   /* UDMA mode 5 */
 146         { 0x1a, 0x01, 0xcb },   /* UDMA mode 6 */
 147 };
 148
 149 static void pdcnew_set_dma_mode(ide_drive_t *drive, const u8 speed)
 150 {
 151         ide_hwif_t *hwif        = HWIF(drive);
 152         u8 adj                  = (drive->dn & 1) ? 0x08 : 0x00;
 153
 154         /*
 155          * IDE core issues SETFEATURES_XFER to the drive first (thanks to
 156          * IDE_HFLAG_POST_SET_MODE in ->host_flags).  PDC202xx hardware will
 157          * automatically set the timing registers based on 100 MHz PLL output.
 158          *
 159          * As we set up the PLL to output 133 MHz for UltraDMA/133 capable
 160          * chips, we must override the default register settings...
 161          */
 162         if (max_dma_rate(hwif->pci_dev) == 4) {
 163                 u8 mode = speed & 0x07;
 164
 165                 switch (speed) {
 166                         case XFER_UDMA_6:
 167                         case XFER_UDMA_5:
 168                         case XFER_UDMA_4:
 169                         case XFER_UDMA_3:
 170                         case XFER_UDMA_2:
 171                         case XFER_UDMA_1:
 172                         case XFER_UDMA_0:
 173                                 set_indexed_reg(hwif, 0x10 + adj,
 174                                                 udma_timings[mode].reg10);
 175                                 set_indexed_reg(hwif, 0x11 + adj,
 176                                                 udma_timings[mode].reg11);
 177                                 set_indexed_reg(hwif, 0x12 + adj,
 178                                                 udma_timings[mode].reg12);
 179                                 break;
 180                         case XFER_MW_DMA_2:
 181                         case XFER_MW_DMA_1:
 182                         case XFER_MW_DMA_0:
 183                                 set_indexed_reg(hwif, 0x0e + adj,
 184                                                 mwdma_timings[mode].reg0e);
 185                                 set_indexed_reg(hwif, 0x0f + adj,
 186                                                 mwdma_timings[mode].reg0f);
 187                                 break;
 188                         default:
 189                                 printk(KERN_ERR "pdc202xx_new: "
 190                                        "Unknown speed %d ignored\n", speed);
 191                 }
 192         } else if (speed == XFER_UDMA_2) {
 193                 /* Set tHOLD bit to 0 if using UDMA mode 2 */
 194                 u8 tmp = get_indexed_reg(hwif, 0x10 + adj);
 195
 196                 set_indexed_reg(hwif, 0x10 + adj, tmp & 0x7f);
 197         }
 198 }
 199
 200 static void pdcnew_set_pio_mode(ide_drive_t *drive, const u8 pio)
 201 {
 202         ide_hwif_t *hwif = drive->hwif;
 203         u8 adj = (drive->dn & 1) ? 0x08 : 0x00;
 204
 205         if (max_dma_rate(hwif->pci_dev) == 4) {
 206                 set_indexed_reg(hwif, 0x0c + adj, pio_timings[pio].reg0c);
 207                 set_indexed_reg(hwif, 0x0d + adj, pio_timings[pio].reg0d);
 208                 set_indexed_reg(hwif, 0x13 + adj, pio_timings[pio].reg13);
 209         }
 210 }
 211
 212 static u8 pdcnew_cable_detect(ide_hwif_t *hwif)
 213 {
 214         if (get_indexed_reg(hwif, 0x0b) & 0x04)
 215                 return ATA_CBL_PATA40;
 216         else
 217                 return ATA_CBL_PATA80;
 218 }
 219
 220 static int pdcnew_quirkproc(ide_drive_t *drive)
 221 {
 222         const char **list, *model = drive->id->model;
 223
 224         for (list = pdc_quirk_drives; *list != NULL; list++)
 225                 if (strstr(model, *list) != NULL)
 226                         return 2;
 227         return 0;
 228 }
 229
 230 static void pdcnew_reset(ide_drive_t *drive)
 231 {
 232         /*
 233          * Deleted this because it is redundant from the caller.
 234          */
 235         printk(KERN_WARNING "pdc202xx_new: %s channel reset.\n",
 236                 HWIF(drive)->channel ? "Secondary" : "Primary");
 237 }
 238
 239 /**
 240  * read_counter - Read the byte count registers
 241  * @dma_base: for the port address
 242  */
 243 static long __devinit read_counter(u32 dma_base)
 244 {
 245         u32  pri_dma_base = dma_base, sec_dma_base = dma_base + 0x08;
 246         u8   cnt0, cnt1, cnt2, cnt3;
 247         long count = 0, last;
 248         int  retry = 3;
 249
 250         do {
 251                 last = count;
 252
 253                 /* Read the current count */
 254                 outb(0x20, pri_dma_base + 0x01);
 255                 cnt0 = inb(pri_dma_base + 0x03);
 256                 outb(0x21, pri_dma_base + 0x01);
 257                 cnt1 = inb(pri_dma_base + 0x03);
 258                 outb(0x20, sec_dma_base + 0x01);
 259                 cnt2 = inb(sec_dma_base + 0x03);
 260                 outb(0x21, sec_dma_base + 0x01);
 261                 cnt3 = inb(sec_dma_base + 0x03);
 262
 263                 count = (cnt3 << 23) | (cnt2 << 15) | (cnt1 << 8) | cnt0;
 264
 265                 /*
 266                  * The 30-bit decrementing counter is read in 4 pieces.
 267                  * Incorrect value may be read when the most significant bytes
 268                  * are changing...
 269                  */
 270         } while (retry-- && (((last ^ count) & 0x3fff8000) || last < count));
 271
 272         DBG("cnt0[%02X] cnt1[%02X] cnt2[%02X] cnt3[%02X]\n",
 273                   cnt0, cnt1, cnt2, cnt3);
 274
 275         return count;
 276 }
 277
 278 /**
 279  * detect_pll_input_clock - Detect the PLL input clock in Hz.
 280  * @dma_base: for the port address
 281  * E.g. 16949000 on 33 MHz PCI bus, i.e. half of the PCI clock.
 282  */
 283 static long __devinit detect_pll_input_clock(unsigned long dma_base)
 284 {
 285         struct timeval start_time, end_time;
 286         long start_count, end_count;
 287         long pll_input, usec_elapsed;
 288         u8 scr1;
 289
 290         start_count = read_counter(dma_base);
 291         do_gettimeofday(&start_time);
 292
 293         /* Start the test mode */
 294         outb(0x01, dma_base + 0x01);
 295         scr1 = inb(dma_base + 0x03);
 296         DBG("scr1[%02X]\n", scr1);
 297         outb(scr1 | 0x40, dma_base + 0x03);
 298
 299         /* Let the counter run for 10 ms. */
 300         mdelay(10);
 301
 302         end_count = read_counter(dma_base);
 303         do_gettimeofday(&end_time);
 304
 305         /* Stop the test mode */
 306         outb(0x01, dma_base + 0x01);
 307         scr1 = inb(dma_base + 0x03);
 308         DBG("scr1[%02X]\n", scr1);
 309         outb(scr1 & ~0x40, dma_base + 0x03);
 310
 311         /*
 312          * Calculate the input clock in Hz
 313          * (the clock counter is 30 bit wide and counts down)
 314          */
 315         usec_elapsed = (end_time.tv_sec - start_time.tv_sec) * 1000000 +
 316                 (end_time.tv_usec - start_time.tv_usec);
 317         pll_input = ((start_count - end_count) & 0x3fffffff) / 10 *
 318                 (10000000 / usec_elapsed);
 319
 320         DBG("start[%ld] end[%ld]\n", start_count, end_count);
 321
 322         return pll_input;
 323 }
 324
 325 #ifdef CONFIG_PPC_PMAC
 326 static void __devinit apple_kiwi_init(struct pci_dev *pdev)
 327 {
 328         struct device_node *np = pci_device_to_OF_node(pdev);
 329         u8 conf;
 330
 331         if (np == NULL || !of_device_is_compatible(np, "kiwi-root"))
 332                 return;
 333
 334         if (pdev->revision >= 0x03) {
 335                 /* Setup chip magic config stuff (from darwin) */
 336                 pci_read_config_byte (pdev, 0x40, &conf);
 337                 pci_write_config_byte(pdev, 0x40, (conf | 0x01));
 338         }
 339 }
 340 #endif /* CONFIG_PPC_PMAC */
 341
 342 static unsigned int __devinit init_chipset_pdcnew(struct pci_dev *dev, const char *name)
 343 {
 344         unsigned long dma_base = pci_resource_start(dev, 4);
 345         unsigned long sec_dma_base = dma_base + 0x08;
 346         long pll_input, pll_output, ratio;
 347         int f, r;
 348         u8 pll_ctl0, pll_ctl1;
 349
 350         if (dma_base == 0)
 351                 return -EFAULT;
 352
 353 #ifdef CONFIG_PPC_PMAC
 354         apple_kiwi_init(dev);
 355 #endif
 356
 357         /* Calculate the required PLL output frequency */
 358         switch(max_dma_rate(dev)) {
 359                 case 4: /* it's 133 MHz for Ultra133 chips */
 360                         pll_output = 133333333;
 361                         break;
 362                 case 3: /* and  100 MHz for Ultra100 chips */
 363                 default:
 364                         pll_output = 100000000;
 365                         break;
 366         }
 367
 368         /*
 369          * Detect PLL input clock.
 370          * On some systems, where PCI bus is running at non-standard clock rate
 371          * (e.g. 25 or 40 MHz), we have to adjust the cycle time.
 372          * PDC20268 and newer chips employ PLL circuit to help correct timing
 373          * registers setting.
 374          */
 375         pll_input = detect_pll_input_clock(dma_base);
 376         printk("%s: PLL input clock is %ld kHz\n", name, pll_input / 1000);
 377
 378         /* Sanity check */
 379         if (unlikely(pll_input < 5000000L || pll_input > 70000000L)) {
 380                 printk(KERN_ERR "%s: Bad PLL input clock %ld Hz, giving up!\n",
 381                        name, pll_input);
 382                 goto out;
 383         }
 384
 385 #ifdef DEBUG
 386         DBG("pll_output is %ld Hz\n", pll_output);
 387
 388         /* Show the current clock value of PLL control register
 389          * (maybe already configured by the BIOS)
 390          */
 391         outb(0x02, sec_dma_base + 0x01);
 392         pll_ctl0 = inb(sec_dma_base + 0x03);
 393         outb(0x03, sec_dma_base + 0x01);
 394         pll_ctl1 = inb(sec_dma_base + 0x03);
 395
 396         DBG("pll_ctl[%02X][%02X]\n", pll_ctl0, pll_ctl1);
 397 #endif
 398
 399         /*
 400          * Calculate the ratio of F, R and NO
 401          * POUT = (F + 2) / (( R + 2) * NO)
 402          */
 403         ratio = pll_output / (pll_input / 1000);
 404         if (ratio < 8600L) { /* 8.6x */
 405                 /* Using NO = 0x01, R = 0x0d */
 406                 r = 0x0d;
 407         } else if (ratio < 12900L) { /* 12.9x */
 408                 /* Using NO = 0x01, R = 0x08 */
 409                 r = 0x08;
 410         } else if (ratio < 16100L) { /* 16.1x */
 411                 /* Using NO = 0x01, R = 0x06 */
 412                 r = 0x06;
 413         } else if (ratio < 64000L) { /* 64x */
 414                 r = 0x00;
 415         } else {
 416                 /* Invalid ratio */
 417                 printk(KERN_ERR "%s: Bad ratio %ld, giving up!\n", name, ratio);
 418                 goto out;
 419         }
 420
 421         f = (ratio * (r + 2)) / 1000 - 2;
 422
 423         DBG("F[%d] R[%d] ratio*1000[%ld]\n", f, r, ratio);
 424
 425         if (unlikely(f < 0 || f > 127)) {
 426                 /* Invalid F */
 427                 printk(KERN_ERR "%s: F[%d] invalid!\n", name, f);
 428                 goto out;
 429         }
 430
 431         pll_ctl0 = (u8) f;
 432         pll_ctl1 = (u8) r;
 433
 434         DBG("Writing pll_ctl[%02X][%02X]\n", pll_ctl0, pll_ctl1);
 435
 436         outb(0x02,     sec_dma_base + 0x01);
 437         outb(pll_ctl0, sec_dma_base + 0x03);
 438         outb(0x03,     sec_dma_base + 0x01);
 439         outb(pll_ctl1, sec_dma_base + 0x03);
 440
 441         /* Wait the PLL circuit to be stable */
 442         mdelay(30);
 443
 444 #ifdef DEBUG
 445         /*
 446          *  Show the current clock value of PLL control register
 447          */
 448         outb(0x02, sec_dma_base + 0x01);
 449         pll_ctl0 = inb(sec_dma_base + 0x03);
 450         outb(0x03, sec_dma_base + 0x01);
 451         pll_ctl1 = inb(sec_dma_base + 0x03);
 452
 453         DBG("pll_ctl[%02X][%02X]\n", pll_ctl0, pll_ctl1);
 454 #endif
 455
 456  out:
 457         return dev->irq;
 458 }
 459
 460 static void __devinit init_hwif_pdc202new(ide_hwif_t *hwif)
 461 {
 462         hwif->set_pio_mode = &pdcnew_set_pio_mode;
 463         hwif->set_dma_mode = &pdcnew_set_dma_mode;
 464
 465         hwif->quirkproc = &pdcnew_quirkproc;
 466         hwif->resetproc = &pdcnew_reset;
 467
 468         if (hwif->dma_base == 0)
 469                 return;
 470
 471         if (hwif->cbl != ATA_CBL_PATA40_SHORT)
 472                 hwif->cbl = pdcnew_cable_detect(hwif);
 473 }
 474
 475 static struct pci_dev * __devinit pdc20270_get_dev2(struct pci_dev *dev)
 476 {
 477         struct pci_dev *dev2;
 478
 479         dev2 = pci_get_slot(dev->bus, PCI_DEVFN(PCI_SLOT(dev->devfn) + 1,
 480                                                 PCI_FUNC(dev->devfn)));
 481
 482         if (dev2 &&
 483             dev2->vendor == dev->vendor &&
 484             dev2->device == dev->device) {
 485
 486                 if (dev2->irq != dev->irq) {
 487                         dev2->irq = dev->irq;
 488                         printk(KERN_INFO "PDC20270: PCI config space "
 489                                          "interrupt fixed\n");
 490                 }
 491
 492                 return dev2;
 493         }
 494
 495         return NULL;
 496 }
 497
 498 #define DECLARE_PDCNEW_DEV(name_str, udma) \
 499         { \
 500                 .name           = name_str, \
 501                 .init_chipset   = init_chipset_pdcnew, \
 502                 .init_hwif      = init_hwif_pdc202new, \
 503                 .host_flags     = IDE_HFLAG_POST_SET_MODE | \
 504                                   IDE_HFLAG_ERROR_STOPS_FIFO | \
 505                                   IDE_HFLAG_OFF_BOARD, \
 506                 .pio_mask       = ATA_PIO4, \
 507                 .mwdma_mask     = ATA_MWDMA2, \
 508                 .udma_mask      = udma, \
 509         }
 510
 511 static const struct ide_port_info pdcnew_chipsets[] __devinitdata = {
 512         /* 0 */ DECLARE_PDCNEW_DEV("PDC20268", ATA_UDMA5),
 513         /* 1 */ DECLARE_PDCNEW_DEV("PDC20269", ATA_UDMA6),
 514         /* 2 */ DECLARE_PDCNEW_DEV("PDC20270", ATA_UDMA5),
 515         /* 3 */ DECLARE_PDCNEW_DEV("PDC20271", ATA_UDMA6),
 516         /* 4 */ DECLARE_PDCNEW_DEV("PDC20275", ATA_UDMA6),
 517         /* 5 */ DECLARE_PDCNEW_DEV("PDC20276", ATA_UDMA6),
 518         /* 6 */ DECLARE_PDCNEW_DEV("PDC20277", ATA_UDMA6),
 519 };
 520
 521 /**
 522  *      pdc202new_init_one      -       called when a pdc202xx is found
 523  *      @dev: the pdc202new device
 524  *      @id: the matching pci id
 525  *
 526  *      Called when the PCI registration layer (or the IDE initialization)
 527  *      finds a device matching our IDE device tables.
 528  */
 529
 530 static int __devinit pdc202new_init_one(struct pci_dev *dev, const struct pci_device_id *id)
 531 {
 532         const struct ide_port_info *d;
 533         struct pci_dev *bridge = dev->bus->self;
 534         u8 idx = id->driver_data;
 535
 536         d = &pdcnew_chipsets[idx];
 537
 538         if (idx == 2 && bridge &&
 539             bridge->vendor == PCI_VENDOR_ID_DEC &&
 540             bridge->device == PCI_DEVICE_ID_DEC_21150) {
 541                 struct pci_dev *dev2;
 542
 543                 if (PCI_SLOT(dev->devfn) & 2)
 544                         return -ENODEV;
 545
 546                 dev2 = pdc20270_get_dev2(dev);
 547
 548                 if (dev2) {
 549                         int ret = ide_setup_pci_devices(dev, dev2, d);
 550                         if (ret < 0)
 551                                 pci_dev_put(dev2);
 552                         return ret;
 553                 }
 554         }
 555
 556         if (idx == 5 && bridge &&
 557             bridge->vendor == PCI_VENDOR_ID_INTEL &&
 558             (bridge->device == PCI_DEVICE_ID_INTEL_I960 ||
 559              bridge->device == PCI_DEVICE_ID_INTEL_I960RM)) {
 560                 printk(KERN_INFO "PDC20276: attached to I2O RAID controller, "
 561                                  "skipping\n");
 562                 return -ENODEV;
 563         }
 564
 565         return ide_setup_pci_device(dev, d);
 566 }
 567
 568 static const struct pci_device_id pdc202new_pci_tbl[] = {
 569         { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20268), 0 },
 570         { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20269), 1 },
 571         { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20270), 2 },
 572         { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20271), 3 },
 573         { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20275), 4 },
 574         { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20276), 5 },
 575         { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20277), 6 },
 576         { 0, },
 577 };
 578 MODULE_DEVICE_TABLE(pci, pdc202new_pci_tbl);
 579
 580 static struct pci_driver driver = {
 581         .name           = "Promise_IDE",
 582         .id_table       = pdc202new_pci_tbl,
 583         .probe          = pdc202new_init_one,
 584 };
 585
 586 static int __init pdc202new_ide_init(void)
 587 {
 588         return ide_pci_register_driver(&driver);
 589 }
 590
 591 module_init(pdc202new_ide_init);
 592
 593 MODULE_AUTHOR("Andre Hedrick, Frank Tiernan");
 594 MODULE_DESCRIPTION("PCI driver module for Promise PDC20268 and higher");
 595 MODULE_LICENSE("GPL");