2 * Copyright (C) 1998-2002 Andre Hedrick <andre@linux-ide.org>
3 * Copyright (C) 2006-2007 MontaVista Software, Inc.
4 * Copyright (C) 2007 Bartlomiej Zolnierkiewicz
6 * Portions Copyright (C) 1999 Promise Technology, Inc.
7 * Author: Frank Tiernan (frankt@promise.com)
8 * Released under terms of General Public License
11 #include <linux/types.h>
12 #include <linux/module.h>
13 #include <linux/kernel.h>
14 #include <linux/delay.h>
15 #include <linux/blkdev.h>
16 #include <linux/hdreg.h>
17 #include <linux/pci.h>
18 #include <linux/init.h>
19 #include <linux/ide.h>
23 #define PDC202XX_DEBUG_DRIVE_INFO 0
25 static const char *pdc_quirk_drives
[] = {
26 "QUANTUM FIREBALLlct08 08",
27 "QUANTUM FIREBALLP KA6.4",
28 "QUANTUM FIREBALLP KA9.1",
29 "QUANTUM FIREBALLP LM20.4",
30 "QUANTUM FIREBALLP KX13.6",
31 "QUANTUM FIREBALLP KX20.5",
32 "QUANTUM FIREBALLP KX27.3",
33 "QUANTUM FIREBALLP LM20.5",
37 static void pdc_old_disable_66MHz_clock(ide_hwif_t
*);
39 static void pdc202xx_set_mode(ide_drive_t
*drive
, const u8 speed
)
41 ide_hwif_t
*hwif
= HWIF(drive
);
42 struct pci_dev
*dev
= to_pci_dev(hwif
->dev
);
43 u8 drive_pci
= 0x60 + (drive
->dn
<< 2);
45 u8 AP
= 0, BP
= 0, CP
= 0;
46 u8 TA
= 0, TB
= 0, TC
= 0;
48 #if PDC202XX_DEBUG_DRIVE_INFO
50 pci_read_config_dword(dev
, drive_pci
, &drive_conf
);
54 * TODO: do this once per channel
56 if (dev
->device
!= PCI_DEVICE_ID_PROMISE_20246
)
57 pdc_old_disable_66MHz_clock(hwif
);
59 pci_read_config_byte(dev
, drive_pci
, &AP
);
60 pci_read_config_byte(dev
, drive_pci
+ 1, &BP
);
61 pci_read_config_byte(dev
, drive_pci
+ 2, &CP
);
65 case XFER_UDMA_4
: TB
= 0x20; TC
= 0x01; break;
66 case XFER_UDMA_2
: TB
= 0x20; TC
= 0x01; break;
68 case XFER_UDMA_1
: TB
= 0x40; TC
= 0x02; break;
70 case XFER_MW_DMA_2
: TB
= 0x60; TC
= 0x03; break;
71 case XFER_MW_DMA_1
: TB
= 0x60; TC
= 0x04; break;
72 case XFER_MW_DMA_0
: TB
= 0xE0; TC
= 0x0F; break;
73 case XFER_PIO_4
: TA
= 0x01; TB
= 0x04; break;
74 case XFER_PIO_3
: TA
= 0x02; TB
= 0x06; break;
75 case XFER_PIO_2
: TA
= 0x03; TB
= 0x08; break;
76 case XFER_PIO_1
: TA
= 0x05; TB
= 0x0C; break;
78 default: TA
= 0x09; TB
= 0x13; break;
81 if (speed
< XFER_SW_DMA_0
) {
83 * preserve SYNC_INT / ERDDY_EN bits while clearing
84 * Prefetch_EN / IORDY_EN / PA[3:0] bits of register A
87 if (drive
->id
->capability
& 4)
88 AP
|= 0x20; /* set IORDY_EN bit */
89 if (drive
->media
== ide_disk
)
90 AP
|= 0x10; /* set Prefetch_EN bit */
91 /* clear PB[4:0] bits of register B */
93 pci_write_config_byte(dev
, drive_pci
, AP
| TA
);
94 pci_write_config_byte(dev
, drive_pci
+ 1, BP
| TB
);
96 /* clear MB[2:0] bits of register B */
98 /* clear MC[3:0] bits of register C */
100 pci_write_config_byte(dev
, drive_pci
+ 1, BP
| TB
);
101 pci_write_config_byte(dev
, drive_pci
+ 2, CP
| TC
);
104 #if PDC202XX_DEBUG_DRIVE_INFO
105 printk(KERN_DEBUG
"%s: %s drive%d 0x%08x ",
106 drive
->name
, ide_xfer_verbose(speed
),
107 drive
->dn
, drive_conf
);
108 pci_read_config_dword(dev
, drive_pci
, &drive_conf
);
109 printk("0x%08x\n", drive_conf
);
113 static void pdc202xx_set_pio_mode(ide_drive_t
*drive
, const u8 pio
)
115 pdc202xx_set_mode(drive
, XFER_PIO_0
+ pio
);
118 static u8 __devinit
pdc2026x_cable_detect(ide_hwif_t
*hwif
)
120 struct pci_dev
*dev
= to_pci_dev(hwif
->dev
);
121 u16 CIS
, mask
= hwif
->channel
? (1 << 11) : (1 << 10);
123 pci_read_config_word(dev
, 0x50, &CIS
);
125 return (CIS
& mask
) ? ATA_CBL_PATA40
: ATA_CBL_PATA80
;
129 * Set the control register to use the 66MHz system
130 * clock for UDMA 3/4/5 mode operation when necessary.
132 * FIXME: this register is shared by both channels, some locking is needed
134 * It may also be possible to leave the 66MHz clock on
135 * and readjust the timing parameters.
137 static void pdc_old_enable_66MHz_clock(ide_hwif_t
*hwif
)
139 unsigned long clock_reg
= hwif
->extra_base
+ 0x01;
140 u8 clock
= inb(clock_reg
);
142 outb(clock
| (hwif
->channel
? 0x08 : 0x02), clock_reg
);
145 static void pdc_old_disable_66MHz_clock(ide_hwif_t
*hwif
)
147 unsigned long clock_reg
= hwif
->extra_base
+ 0x01;
148 u8 clock
= inb(clock_reg
);
150 outb(clock
& ~(hwif
->channel
? 0x08 : 0x02), clock_reg
);
153 static void pdc202xx_quirkproc(ide_drive_t
*drive
)
155 const char **list
, *model
= drive
->id
->model
;
157 for (list
= pdc_quirk_drives
; *list
!= NULL
; list
++)
158 if (strstr(model
, *list
) != NULL
) {
159 drive
->quirk_list
= 2;
163 drive
->quirk_list
= 0;
166 static void pdc202xx_old_ide_dma_start(ide_drive_t
*drive
)
168 if (drive
->current_speed
> XFER_UDMA_2
)
169 pdc_old_enable_66MHz_clock(drive
->hwif
);
170 if (drive
->media
!= ide_disk
|| drive
->addressing
== 1) {
171 struct request
*rq
= HWGROUP(drive
)->rq
;
172 ide_hwif_t
*hwif
= HWIF(drive
);
173 unsigned long high_16
= hwif
->extra_base
- 16;
174 unsigned long atapi_reg
= high_16
+ (hwif
->channel
? 0x24 : 0x20);
176 u8 clock
= inb(high_16
+ 0x11);
178 outb(clock
| (hwif
->channel
? 0x08 : 0x02), high_16
+ 0x11);
179 word_count
= (rq
->nr_sectors
<< 8);
180 word_count
= (rq_data_dir(rq
) == READ
) ?
181 word_count
| 0x05000000 :
182 word_count
| 0x06000000;
183 outl(word_count
, atapi_reg
);
185 ide_dma_start(drive
);
188 static int pdc202xx_old_ide_dma_end(ide_drive_t
*drive
)
190 if (drive
->media
!= ide_disk
|| drive
->addressing
== 1) {
191 ide_hwif_t
*hwif
= HWIF(drive
);
192 unsigned long high_16
= hwif
->extra_base
- 16;
193 unsigned long atapi_reg
= high_16
+ (hwif
->channel
? 0x24 : 0x20);
196 outl(0, atapi_reg
); /* zero out extra */
197 clock
= inb(high_16
+ 0x11);
198 outb(clock
& ~(hwif
->channel
? 0x08:0x02), high_16
+ 0x11);
200 if (drive
->current_speed
> XFER_UDMA_2
)
201 pdc_old_disable_66MHz_clock(drive
->hwif
);
202 return __ide_dma_end(drive
);
205 static int pdc202xx_old_ide_dma_test_irq(ide_drive_t
*drive
)
207 ide_hwif_t
*hwif
= HWIF(drive
);
208 unsigned long high_16
= hwif
->extra_base
- 16;
209 u8 dma_stat
= inb(hwif
->dma_status
);
210 u8 sc1d
= inb(high_16
+ 0x001d);
213 /* bit7: Error, bit6: Interrupting, bit5: FIFO Full, bit4: FIFO Empty */
214 if ((sc1d
& 0x50) == 0x50)
216 else if ((sc1d
& 0x40) == 0x40)
217 return (dma_stat
& 4) == 4;
219 /* bit3: Error, bit2: Interrupting, bit1: FIFO Full, bit0: FIFO Empty */
220 if ((sc1d
& 0x05) == 0x05)
222 else if ((sc1d
& 0x04) == 0x04)
223 return (dma_stat
& 4) == 4;
226 return (dma_stat
& 4) == 4; /* return 1 if INTR asserted */
229 static void pdc202xx_reset_host (ide_hwif_t
*hwif
)
231 unsigned long high_16
= hwif
->extra_base
- 16;
232 u8 udma_speed_flag
= inb(high_16
| 0x001f);
234 outb(udma_speed_flag
| 0x10, high_16
| 0x001f);
236 outb(udma_speed_flag
& ~0x10, high_16
| 0x001f);
237 mdelay(2000); /* 2 seconds ?! */
239 printk(KERN_WARNING
"PDC202XX: %s channel reset.\n",
240 hwif
->channel
? "Secondary" : "Primary");
243 static void pdc202xx_reset (ide_drive_t
*drive
)
245 ide_hwif_t
*hwif
= HWIF(drive
);
246 ide_hwif_t
*mate
= hwif
->mate
;
248 pdc202xx_reset_host(hwif
);
249 pdc202xx_reset_host(mate
);
251 ide_set_max_pio(drive
);
254 static void pdc202xx_dma_lost_irq(ide_drive_t
*drive
)
256 pdc202xx_reset(drive
);
257 ide_dma_lost_irq(drive
);
260 static void pdc202xx_dma_timeout(ide_drive_t
*drive
)
262 pdc202xx_reset(drive
);
263 ide_dma_timeout(drive
);
266 static unsigned int __devinit
init_chipset_pdc202xx(struct pci_dev
*dev
,
272 static void __devinit
init_hwif_pdc202xx(ide_hwif_t
*hwif
)
274 struct pci_dev
*dev
= to_pci_dev(hwif
->dev
);
276 if (hwif
->dma_base
== 0)
279 hwif
->dma_lost_irq
= &pdc202xx_dma_lost_irq
;
280 hwif
->dma_timeout
= &pdc202xx_dma_timeout
;
282 if (dev
->device
!= PCI_DEVICE_ID_PROMISE_20246
) {
283 hwif
->dma_start
= &pdc202xx_old_ide_dma_start
;
284 hwif
->ide_dma_end
= &pdc202xx_old_ide_dma_end
;
286 hwif
->ide_dma_test_irq
= &pdc202xx_old_ide_dma_test_irq
;
289 static void __devinit
init_dma_pdc202xx(ide_hwif_t
*hwif
, unsigned long dmabase
)
291 u8 udma_speed_flag
= 0, primary_mode
= 0, secondary_mode
= 0;
294 ide_setup_dma(hwif
, dmabase
);
298 udma_speed_flag
= inb(dmabase
| 0x1f);
299 primary_mode
= inb(dmabase
| 0x1a);
300 secondary_mode
= inb(dmabase
| 0x1b);
301 printk(KERN_INFO
"%s: (U)DMA Burst Bit %sABLED " \
303 "Secondary %s Mode.\n", hwif
->cds
->name
,
304 (udma_speed_flag
& 1) ? "EN" : "DIS",
305 (primary_mode
& 1) ? "MASTER" : "PCI",
306 (secondary_mode
& 1) ? "MASTER" : "PCI" );
308 if (!(udma_speed_flag
& 1)) {
309 printk(KERN_INFO
"%s: FORCING BURST BIT 0x%02x->0x%02x ",
310 hwif
->cds
->name
, udma_speed_flag
,
311 (udma_speed_flag
|1));
312 outb(udma_speed_flag
| 1, dmabase
| 0x1f);
313 printk("%sACTIVE\n", (inb(dmabase
| 0x1f) & 1) ? "" : "IN");
316 ide_setup_dma(hwif
, dmabase
);
319 static void __devinit
pdc202ata4_fixup_irq(struct pci_dev
*dev
,
322 if ((dev
->class >> 8) != PCI_CLASS_STORAGE_IDE
) {
323 u8 irq
= 0, irq2
= 0;
324 pci_read_config_byte(dev
, PCI_INTERRUPT_LINE
, &irq
);
326 pci_read_config_byte(dev
, (PCI_INTERRUPT_LINE
)|0x80, &irq2
);
328 pci_write_config_byte(dev
,
329 (PCI_INTERRUPT_LINE
)|0x80, irq
); /* 0xbc */
330 printk(KERN_INFO
"%s: PCI config space interrupt "
331 "mirror fixed\n", name
);
336 #define IDE_HFLAGS_PDC202XX \
337 (IDE_HFLAG_ERROR_STOPS_FIFO | \
338 IDE_HFLAG_ABUSE_SET_DMA_MODE | \
341 static const struct ide_port_ops pdc20246_port_ops
= {
342 .set_pio_mode
= pdc202xx_set_pio_mode
,
343 .set_dma_mode
= pdc202xx_set_mode
,
344 .quirkproc
= pdc202xx_quirkproc
,
347 static const struct ide_port_ops pdc2026x_port_ops
= {
348 .set_pio_mode
= pdc202xx_set_pio_mode
,
349 .set_dma_mode
= pdc202xx_set_mode
,
350 .quirkproc
= pdc202xx_quirkproc
,
351 .resetproc
= pdc202xx_reset
,
352 .cable_detect
= pdc2026x_cable_detect
,
355 #define DECLARE_PDC2026X_DEV(name_str, udma, extra_flags) \
358 .init_chipset = init_chipset_pdc202xx, \
359 .init_hwif = init_hwif_pdc202xx, \
360 .init_dma = init_dma_pdc202xx, \
361 .port_ops = &pdc2026x_port_ops, \
362 .host_flags = IDE_HFLAGS_PDC202XX | extra_flags, \
363 .pio_mask = ATA_PIO4, \
364 .mwdma_mask = ATA_MWDMA2, \
368 static const struct ide_port_info pdc202xx_chipsets
[] __devinitdata
= {
371 .init_chipset
= init_chipset_pdc202xx
,
372 .init_hwif
= init_hwif_pdc202xx
,
373 .init_dma
= init_dma_pdc202xx
,
374 .port_ops
= &pdc20246_port_ops
,
375 .host_flags
= IDE_HFLAGS_PDC202XX
,
376 .pio_mask
= ATA_PIO4
,
377 .mwdma_mask
= ATA_MWDMA2
,
378 .udma_mask
= ATA_UDMA2
,
381 /* 1 */ DECLARE_PDC2026X_DEV("PDC20262", ATA_UDMA4
, 0),
382 /* 2 */ DECLARE_PDC2026X_DEV("PDC20263", ATA_UDMA4
, 0),
383 /* 3 */ DECLARE_PDC2026X_DEV("PDC20265", ATA_UDMA5
, IDE_HFLAG_RQSIZE_256
),
384 /* 4 */ DECLARE_PDC2026X_DEV("PDC20267", ATA_UDMA5
, IDE_HFLAG_RQSIZE_256
),
388 * pdc202xx_init_one - called when a PDC202xx is found
389 * @dev: the pdc202xx device
390 * @id: the matching pci id
392 * Called when the PCI registration layer (or the IDE initialization)
393 * finds a device matching our IDE device tables.
396 static int __devinit
pdc202xx_init_one(struct pci_dev
*dev
, const struct pci_device_id
*id
)
398 const struct ide_port_info
*d
;
399 u8 idx
= id
->driver_data
;
401 d
= &pdc202xx_chipsets
[idx
];
404 pdc202ata4_fixup_irq(dev
, d
->name
);
407 struct pci_dev
*bridge
= dev
->bus
->self
;
410 bridge
->vendor
== PCI_VENDOR_ID_INTEL
&&
411 (bridge
->device
== PCI_DEVICE_ID_INTEL_I960
||
412 bridge
->device
== PCI_DEVICE_ID_INTEL_I960RM
)) {
413 printk(KERN_INFO
"ide: Skipping Promise PDC20265 "
414 "attached to I2O RAID controller\n");
419 return ide_setup_pci_device(dev
, d
);
422 static const struct pci_device_id pdc202xx_pci_tbl
[] = {
423 { PCI_VDEVICE(PROMISE
, PCI_DEVICE_ID_PROMISE_20246
), 0 },
424 { PCI_VDEVICE(PROMISE
, PCI_DEVICE_ID_PROMISE_20262
), 1 },
425 { PCI_VDEVICE(PROMISE
, PCI_DEVICE_ID_PROMISE_20263
), 2 },
426 { PCI_VDEVICE(PROMISE
, PCI_DEVICE_ID_PROMISE_20265
), 3 },
427 { PCI_VDEVICE(PROMISE
, PCI_DEVICE_ID_PROMISE_20267
), 4 },
430 MODULE_DEVICE_TABLE(pci
, pdc202xx_pci_tbl
);
432 static struct pci_driver driver
= {
433 .name
= "Promise_Old_IDE",
434 .id_table
= pdc202xx_pci_tbl
,
435 .probe
= pdc202xx_init_one
,
438 static int __init
pdc202xx_ide_init(void)
440 return ide_pci_register_driver(&driver
);
443 module_init(pdc202xx_ide_init
);
445 MODULE_AUTHOR("Andre Hedrick, Frank Tiernan");
446 MODULE_DESCRIPTION("PCI driver module for older Promise IDE");
447 MODULE_LICENSE("GPL");