2 * linux/drivers/ide/pci/piix.c Version 0.44 March 20, 2003
4 * Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer
5 * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
6 * Copyright (C) 2003 Red Hat Inc <alan@redhat.com>
8 * May be copied or modified under the terms of the GNU General Public License
10 * PIO mode setting function for Intel chipsets.
11 * For use instead of BIOS settings.
19 * | PIO 0 | c0 | 80 | 0 | piix_tune_drive(drive, 0);
20 * | PIO 2 | SW2 | d0 | 90 | 4 | piix_tune_drive(drive, 2);
21 * | PIO 3 | MW1 | e1 | a1 | 9 | piix_tune_drive(drive, 3);
22 * | PIO 4 | MW2 | e3 | a3 | b | piix_tune_drive(drive, 4);
24 * sitre = word40 & 0x4000; primary
25 * sitre = word42 & 0x4000; secondary
27 * 44 8421|8421 hdd|hdb
29 * 48 8421 hdd|hdc|hdb|hda udma enabled
41 * ata-33/82801AB ata-66/82801AA
42 * 00|00 udma 0 00|00 reserved
43 * 01|01 udma 1 01|01 udma 3
44 * 10|10 udma 2 10|10 udma 4
45 * 11|11 reserved 11|11 reserved
47 * 54 8421|8421 ata66 drive|ata66 enable
49 * pci_read_config_word(HWIF(drive)->pci_dev, 0x40, ®40);
50 * pci_read_config_word(HWIF(drive)->pci_dev, 0x42, ®42);
51 * pci_read_config_word(HWIF(drive)->pci_dev, 0x44, ®44);
52 * pci_read_config_byte(HWIF(drive)->pci_dev, 0x48, ®48);
53 * pci_read_config_word(HWIF(drive)->pci_dev, 0x4a, ®4a);
54 * pci_read_config_byte(HWIF(drive)->pci_dev, 0x54, ®54);
57 * Publically available from Intel web site. Errata documentation
58 * is also publically available. As an aide to anyone hacking on this
59 * driver the list of errata that are relevant is below.going back to
60 * PIIX4. Older device documentation is now a bit tricky to find.
65 * PIIX4 errata #9 - Only on ultra obscure hw
66 * ICH3 errata #13 - Not observed to affect real hw
69 * Things we must deal with
70 * PIIX4 errata #10 - BM IDE hang with non UDMA
71 * (must stop/start dma to recover)
72 * 440MX errata #15 - As PIIX4 errata #10
73 * PIIX4 errata #15 - Must not read control registers
74 * during a PIO transfer
75 * 440MX errata #13 - As PIIX4 errata #15
76 * ICH2 errata #21 - DMA mode 0 doesn't work right
77 * ICH0/1 errata #55 - As ICH2 errata #21
78 * ICH2 spec c #9 - Extra operations needed to handle
79 * drive hotswap [NOT YET SUPPORTED]
80 * ICH2 spec c #20 - IDE PRD must not cross a 64K boundary
81 * and must be dword aligned
82 * ICH2 spec c #24 - UDMA mode 4,5 t85/86 should be 6ns not 3.3
84 * Should have been BIOS fixed:
85 * 450NX: errata #19 - DMA hangs on old 450NX
86 * 450NX: errata #20 - DMA hangs on old 450NX
87 * 450NX: errata #25 - Corruption with DMA on old 450NX
88 * ICH3 errata #15 - IDE deadlock under high load
89 * (BIOS must set dev 31 fn 0 bit 23)
90 * ICH3 errata #18 - Don't use native mode
93 #include <linux/types.h>
94 #include <linux/module.h>
95 #include <linux/kernel.h>
96 #include <linux/ioport.h>
97 #include <linux/pci.h>
98 #include <linux/hdreg.h>
99 #include <linux/ide.h>
100 #include <linux/delay.h>
101 #include <linux/init.h>
105 static int no_piix_dma
;
108 * piix_ratemask - compute rate mask for PIIX IDE
109 * @drive: IDE drive to compute for
111 * Returns the available modes for the PIIX IDE controller.
114 static u8
piix_ratemask (ide_drive_t
*drive
)
116 struct pci_dev
*dev
= HWIF(drive
)->pci_dev
;
119 switch(dev
->device
) {
120 case PCI_DEVICE_ID_INTEL_82801EB_1
:
123 /* UDMA 100 capable */
124 case PCI_DEVICE_ID_INTEL_82801BA_8
:
125 case PCI_DEVICE_ID_INTEL_82801BA_9
:
126 case PCI_DEVICE_ID_INTEL_82801CA_10
:
127 case PCI_DEVICE_ID_INTEL_82801CA_11
:
128 case PCI_DEVICE_ID_INTEL_82801E_11
:
129 case PCI_DEVICE_ID_INTEL_82801DB_1
:
130 case PCI_DEVICE_ID_INTEL_82801DB_10
:
131 case PCI_DEVICE_ID_INTEL_82801DB_11
:
132 case PCI_DEVICE_ID_INTEL_82801EB_11
:
133 case PCI_DEVICE_ID_INTEL_ESB_2
:
134 case PCI_DEVICE_ID_INTEL_ICH6_19
:
135 case PCI_DEVICE_ID_INTEL_ICH7_21
:
136 case PCI_DEVICE_ID_INTEL_ESB2_18
:
137 case PCI_DEVICE_ID_INTEL_ICH8_6
:
140 /* UDMA 66 capable */
141 case PCI_DEVICE_ID_INTEL_82801AA_1
:
142 case PCI_DEVICE_ID_INTEL_82372FB_1
:
145 /* UDMA 33 capable */
146 case PCI_DEVICE_ID_INTEL_82371AB
:
147 case PCI_DEVICE_ID_INTEL_82443MX_1
:
148 case PCI_DEVICE_ID_INTEL_82451NX
:
149 case PCI_DEVICE_ID_INTEL_82801AB_1
:
151 /* Non UDMA capable (MWDMA2) */
152 case PCI_DEVICE_ID_INTEL_82371SB_1
:
153 case PCI_DEVICE_ID_INTEL_82371FB_1
:
154 case PCI_DEVICE_ID_INTEL_82371FB_0
:
155 case PCI_DEVICE_ID_INTEL_82371MX
:
161 * If we are UDMA66 capable fall back to UDMA33
162 * if the drive cannot see an 80pin cable.
164 if (!eighty_ninty_three(drive
))
165 mode
= min(mode
, (u8
)1);
170 * piix_dma_2_pio - return the PIO mode matching DMA
171 * @xfer_rate: transfer speed
173 * Returns the nearest equivalent PIO timing for the PIO or DMA
174 * mode requested by the controller.
177 static u8
piix_dma_2_pio (u8 xfer_rate
) {
207 * piix_tune_drive - tune a drive attached to a PIIX
208 * @drive: drive to tune
209 * @pio: desired PIO mode
211 * Set the interface PIO mode based upon the settings done by AMI BIOS
212 * (might be useful if drive is not registered in CMOS for any reason).
214 static void piix_tune_drive (ide_drive_t
*drive
, u8 pio
)
216 ide_hwif_t
*hwif
= HWIF(drive
);
217 struct pci_dev
*dev
= hwif
->pci_dev
;
218 int is_slave
= (&hwif
->drives
[1] == drive
);
219 int master_port
= hwif
->channel
? 0x42 : 0x40;
220 int slave_port
= 0x44;
224 static DEFINE_SPINLOCK(tune_lock
);
227 u8 timings
[][2] = { { 0, 0 },
233 pio
= ide_get_best_pio_mode(drive
, pio
, 5, NULL
);
236 * Master vs slave is synchronized above us but the slave register is
237 * shared by the two hwifs so the corner case of two slave timeouts in
238 * parallel must be locked.
240 spin_lock_irqsave(&tune_lock
, flags
);
241 pci_read_config_word(dev
, master_port
, &master_data
);
243 master_data
= master_data
| 0x4000;
245 /* enable PPE, IE and TIME */
246 master_data
= master_data
| 0x0070;
247 pci_read_config_byte(dev
, slave_port
, &slave_data
);
248 slave_data
= slave_data
& (hwif
->channel
? 0x0f : 0xf0);
249 slave_data
= slave_data
| (((timings
[pio
][0] << 2) | timings
[pio
][1]) << (hwif
->channel
? 4 : 0));
251 master_data
= master_data
& 0xccf8;
253 /* enable PPE, IE and TIME */
254 master_data
= master_data
| 0x0007;
255 master_data
= master_data
| (timings
[pio
][0] << 12) | (timings
[pio
][1] << 8);
257 pci_write_config_word(dev
, master_port
, master_data
);
259 pci_write_config_byte(dev
, slave_port
, slave_data
);
260 spin_unlock_irqrestore(&tune_lock
, flags
);
264 * piix_tune_chipset - tune a PIIX interface
265 * @drive: IDE drive to tune
266 * @xferspeed: speed to configure
268 * Set a PIIX interface channel to the desired speeds. This involves
269 * requires the right timing data into the PIIX configuration space
270 * then setting the drive parameters appropriately
273 static int piix_tune_chipset (ide_drive_t
*drive
, u8 xferspeed
)
275 ide_hwif_t
*hwif
= HWIF(drive
);
276 struct pci_dev
*dev
= hwif
->pci_dev
;
277 u8 maslave
= hwif
->channel
? 0x42 : 0x40;
278 u8 speed
= ide_rate_filter(piix_ratemask(drive
), xferspeed
);
279 int a_speed
= 3 << (drive
->dn
* 4);
280 int u_flag
= 1 << drive
->dn
;
281 int v_flag
= 0x01 << drive
->dn
;
282 int w_flag
= 0x10 << drive
->dn
;
286 u8 reg48
, reg54
, reg55
;
288 pci_read_config_word(dev
, maslave
, ®4042
);
289 sitre
= (reg4042
& 0x4000) ? 1 : 0;
290 pci_read_config_byte(dev
, 0x48, ®48
);
291 pci_read_config_word(dev
, 0x4a, ®4a
);
292 pci_read_config_byte(dev
, 0x54, ®54
);
293 pci_read_config_byte(dev
, 0x55, ®55
);
297 case XFER_UDMA_2
: u_speed
= 2 << (drive
->dn
* 4); break;
300 case XFER_UDMA_1
: u_speed
= 1 << (drive
->dn
* 4); break;
301 case XFER_UDMA_0
: u_speed
= 0 << (drive
->dn
* 4); break;
304 case XFER_SW_DMA_2
: break;
308 case XFER_PIO_0
: break;
312 if (speed
>= XFER_UDMA_0
) {
313 if (!(reg48
& u_flag
))
314 pci_write_config_byte(dev
, 0x48, reg48
| u_flag
);
315 if (speed
== XFER_UDMA_5
) {
316 pci_write_config_byte(dev
, 0x55, (u8
) reg55
|w_flag
);
318 pci_write_config_byte(dev
, 0x55, (u8
) reg55
& ~w_flag
);
320 if ((reg4a
& a_speed
) != u_speed
)
321 pci_write_config_word(dev
, 0x4a, (reg4a
& ~a_speed
) | u_speed
);
322 if (speed
> XFER_UDMA_2
) {
323 if (!(reg54
& v_flag
))
324 pci_write_config_byte(dev
, 0x54, reg54
| v_flag
);
326 pci_write_config_byte(dev
, 0x54, reg54
& ~v_flag
);
329 pci_write_config_byte(dev
, 0x48, reg48
& ~u_flag
);
331 pci_write_config_word(dev
, 0x4a, reg4a
& ~a_speed
);
333 pci_write_config_byte(dev
, 0x54, reg54
& ~v_flag
);
335 pci_write_config_byte(dev
, 0x55, (u8
) reg55
& ~w_flag
);
338 piix_tune_drive(drive
, piix_dma_2_pio(speed
));
339 return (ide_config_drive_speed(drive
, speed
));
343 * piix_faulty_dma0 - check for DMA0 errata
344 * @hwif: IDE interface to check
346 * If an ICH/ICH0/ICH2 interface is is operating in multi-word
347 * DMA mode with 600nS cycle time the IDE PIO prefetch buffer will
348 * inadvertently provide an extra piece of secondary data to the primary
349 * device resulting in data corruption.
351 * With such a device this test function returns true. This allows
352 * our tuning code to follow Intel recommendations and use PIO on
356 static int piix_faulty_dma0(ide_hwif_t
*hwif
)
358 switch(hwif
->pci_dev
->device
)
360 case PCI_DEVICE_ID_INTEL_82801AA_1
: /* ICH */
361 case PCI_DEVICE_ID_INTEL_82801AB_1
: /* ICH0 */
362 case PCI_DEVICE_ID_INTEL_82801BA_8
: /* ICH2 */
363 case PCI_DEVICE_ID_INTEL_82801BA_9
: /* ICH2 */
370 * piix_config_drive_for_dma - configure drive for DMA
371 * @drive: IDE drive to configure
373 * Set up a PIIX interface channel for the best available speed.
374 * We prefer UDMA if it is available and then MWDMA. If DMA is
375 * not available we switch to PIO and return 0.
378 static int piix_config_drive_for_dma (ide_drive_t
*drive
)
380 u8 speed
= ide_dma_speed(drive
, piix_ratemask(drive
));
382 /* Some ICH devices cannot support DMA mode 0 */
383 if(speed
== XFER_MW_DMA_0
&& piix_faulty_dma0(HWIF(drive
)))
386 /* If no DMA speed was available or the chipset has DMA bugs
387 then disable DMA and use PIO */
389 if (!speed
|| no_piix_dma
) {
390 u8 tspeed
= ide_get_best_pio_mode(drive
, 255, 5, NULL
);
391 speed
= piix_dma_2_pio(XFER_PIO_0
+ tspeed
);
394 (void) piix_tune_chipset(drive
, speed
);
395 return ide_dma_enable(drive
);
399 * piix_config_drive_xfer_rate - set up an IDE device
400 * @drive: IDE drive to configure
402 * Set up the PIIX interface for the best available speed on this
403 * interface, preferring DMA to PIO.
406 static int piix_config_drive_xfer_rate (ide_drive_t
*drive
)
408 ide_hwif_t
*hwif
= HWIF(drive
);
409 struct hd_driveid
*id
= drive
->id
;
411 drive
->init_speed
= 0;
413 if ((id
->capability
& 1) && drive
->autodma
) {
415 if (ide_use_dma(drive
)) {
416 if (piix_config_drive_for_dma(drive
))
417 return hwif
->ide_dma_on(drive
);
422 } else if ((id
->capability
& 8) || (id
->field_valid
& 2)) {
424 /* Find best PIO mode. */
425 hwif
->tuneproc(drive
, 255);
426 return hwif
->ide_dma_off_quietly(drive
);
428 /* IORDY not supported */
433 * init_chipset_piix - set up the PIIX chipset
434 * @dev: PCI device to set up
435 * @name: Name of the device
437 * Initialize the PCI device as required. For the PIIX this turns
438 * out to be nice and simple
441 static unsigned int __devinit
init_chipset_piix (struct pci_dev
*dev
, const char *name
)
443 switch(dev
->device
) {
444 case PCI_DEVICE_ID_INTEL_82801EB_1
:
445 case PCI_DEVICE_ID_INTEL_82801AA_1
:
446 case PCI_DEVICE_ID_INTEL_82801AB_1
:
447 case PCI_DEVICE_ID_INTEL_82801BA_8
:
448 case PCI_DEVICE_ID_INTEL_82801BA_9
:
449 case PCI_DEVICE_ID_INTEL_82801CA_10
:
450 case PCI_DEVICE_ID_INTEL_82801CA_11
:
451 case PCI_DEVICE_ID_INTEL_82801DB_1
:
452 case PCI_DEVICE_ID_INTEL_82801DB_10
:
453 case PCI_DEVICE_ID_INTEL_82801DB_11
:
454 case PCI_DEVICE_ID_INTEL_82801EB_11
:
455 case PCI_DEVICE_ID_INTEL_82801E_11
:
456 case PCI_DEVICE_ID_INTEL_ESB_2
:
457 case PCI_DEVICE_ID_INTEL_ICH6_19
:
458 case PCI_DEVICE_ID_INTEL_ICH7_21
:
459 case PCI_DEVICE_ID_INTEL_ESB2_18
:
460 case PCI_DEVICE_ID_INTEL_ICH8_6
:
462 unsigned int extra
= 0;
463 pci_read_config_dword(dev
, 0x54, &extra
);
464 pci_write_config_dword(dev
, 0x54, extra
|0x400);
474 * init_hwif_piix - fill in the hwif for the PIIX
475 * @hwif: IDE interface
477 * Set up the ide_hwif_t for the PIIX interface according to the
478 * capabilities of the hardware.
481 static void __devinit
init_hwif_piix(ide_hwif_t
*hwif
)
483 u8 reg54h
= 0, reg55h
= 0, ata66
= 0;
484 u8 mask
= hwif
->channel
? 0xc0 : 0x30;
488 hwif
->irq
= hwif
->channel
? 15 : 14;
489 #endif /* CONFIG_IA64 */
491 if (hwif
->pci_dev
->device
== PCI_DEVICE_ID_INTEL_82371MX
) {
492 /* This is a painful system best to let it self tune for now */
497 hwif
->tuneproc
= &piix_tune_drive
;
498 hwif
->speedproc
= &piix_tune_chipset
;
499 hwif
->drives
[0].autotune
= 1;
500 hwif
->drives
[1].autotune
= 1;
506 hwif
->ultra_mask
= 0x3f;
507 hwif
->mwdma_mask
= 0x06;
508 hwif
->swdma_mask
= 0x04;
510 switch(hwif
->pci_dev
->device
) {
511 case PCI_DEVICE_ID_INTEL_82371MX
:
512 hwif
->mwdma_mask
= 0x80;
513 hwif
->swdma_mask
= 0x80;
514 case PCI_DEVICE_ID_INTEL_82371FB_0
:
515 case PCI_DEVICE_ID_INTEL_82371FB_1
:
516 case PCI_DEVICE_ID_INTEL_82371SB_1
:
517 hwif
->ultra_mask
= 0x80;
519 case PCI_DEVICE_ID_INTEL_82371AB
:
520 case PCI_DEVICE_ID_INTEL_82443MX_1
:
521 case PCI_DEVICE_ID_INTEL_82451NX
:
522 case PCI_DEVICE_ID_INTEL_82801AB_1
:
523 hwif
->ultra_mask
= 0x07;
526 pci_read_config_byte(hwif
->pci_dev
, 0x54, ®54h
);
527 pci_read_config_byte(hwif
->pci_dev
, 0x55, ®55h
);
528 ata66
= (reg54h
& mask
) ? 1 : 0;
532 if (!(hwif
->udma_four
))
533 hwif
->udma_four
= ata66
;
534 hwif
->ide_dma_check
= &piix_config_drive_xfer_rate
;
538 hwif
->drives
[1].autodma
= hwif
->autodma
;
539 hwif
->drives
[0].autodma
= hwif
->autodma
;
542 #define DECLARE_PIIX_DEV(name_str) \
545 .init_chipset = init_chipset_piix, \
546 .init_hwif = init_hwif_piix, \
548 .autodma = AUTODMA, \
549 .enablebits = {{0x41,0x80,0x80}, {0x43,0x80,0x80}}, \
550 .bootable = ON_BOARD, \
553 static ide_pci_device_t piix_pci_info
[] __devinitdata
= {
554 /* 0 */ DECLARE_PIIX_DEV("PIIXa"),
555 /* 1 */ DECLARE_PIIX_DEV("PIIXb"),
559 .init_hwif
= init_hwif_piix
,
562 .enablebits
= {{0x6D,0x80,0x80}, {0x6F,0x80,0x80}},
563 .bootable
= ON_BOARD
,
566 /* 3 */ DECLARE_PIIX_DEV("PIIX3"),
567 /* 4 */ DECLARE_PIIX_DEV("PIIX4"),
568 /* 5 */ DECLARE_PIIX_DEV("ICH0"),
569 /* 6 */ DECLARE_PIIX_DEV("PIIX4"),
570 /* 7 */ DECLARE_PIIX_DEV("ICH"),
571 /* 8 */ DECLARE_PIIX_DEV("PIIX4"),
572 /* 9 */ DECLARE_PIIX_DEV("PIIX4"),
573 /* 10 */ DECLARE_PIIX_DEV("ICH2"),
574 /* 11 */ DECLARE_PIIX_DEV("ICH2M"),
575 /* 12 */ DECLARE_PIIX_DEV("ICH3M"),
576 /* 13 */ DECLARE_PIIX_DEV("ICH3"),
577 /* 14 */ DECLARE_PIIX_DEV("ICH4"),
578 /* 15 */ DECLARE_PIIX_DEV("ICH5"),
579 /* 16 */ DECLARE_PIIX_DEV("C-ICH"),
580 /* 17 */ DECLARE_PIIX_DEV("ICH4"),
581 /* 18 */ DECLARE_PIIX_DEV("ICH5-SATA"),
582 /* 19 */ DECLARE_PIIX_DEV("ICH5"),
583 /* 20 */ DECLARE_PIIX_DEV("ICH6"),
584 /* 21 */ DECLARE_PIIX_DEV("ICH7"),
585 /* 22 */ DECLARE_PIIX_DEV("ICH4"),
586 /* 23 */ DECLARE_PIIX_DEV("ESB2"),
587 /* 24 */ DECLARE_PIIX_DEV("ICH8M"),
591 * piix_init_one - called when a PIIX is found
592 * @dev: the piix device
593 * @id: the matching pci id
595 * Called when the PCI registration layer (or the IDE initialization)
596 * finds a device matching our IDE device tables.
599 static int __devinit
piix_init_one(struct pci_dev
*dev
, const struct pci_device_id
*id
)
601 ide_pci_device_t
*d
= &piix_pci_info
[id
->driver_data
];
603 return ide_setup_pci_device(dev
, d
);
607 * piix_check_450nx - Check for problem 450NX setup
609 * Check for the present of 450NX errata #19 and errata #25. If
610 * they are found, disable use of DMA IDE
613 static void __devinit
piix_check_450nx(void)
615 struct pci_dev
*pdev
= NULL
;
618 while((pdev
=pci_find_device(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82454NX
, pdev
))!=NULL
)
620 /* Look for 450NX PXB. Check for problem configurations
621 A PCI quirk checks bit 6 already */
622 pci_read_config_byte(pdev
, PCI_REVISION_ID
, &rev
);
623 pci_read_config_word(pdev
, 0x41, &cfg
);
624 /* Only on the original revision: IDE DMA can hang */
627 /* On all revisions below 5 PXB bus lock must be disabled for IDE */
628 else if(cfg
& (1<<14) && rev
< 5)
632 printk(KERN_WARNING
"piix: 450NX errata present, disabling IDE DMA.\n");
634 printk(KERN_WARNING
"piix: A BIOS update may resolve this.\n");
637 static struct pci_device_id piix_pci_tbl
[] = {
638 { PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82371FB_0
, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0},
639 { PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82371FB_1
, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 1},
640 { PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82371MX
, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 2},
641 { PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82371SB_1
, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 3},
642 { PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82371AB
, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 4},
643 { PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801AB_1
, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 5},
644 { PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82443MX_1
, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 6},
645 { PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801AA_1
, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 7},
646 { PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82372FB_1
, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 8},
647 { PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82451NX
, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 9},
648 { PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801BA_9
, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 10},
649 { PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801BA_8
, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 11},
650 { PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801CA_10
,PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 12},
651 { PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801CA_11
,PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 13},
652 { PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801DB_11
,PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 14},
653 { PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801EB_11
,PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 15},
654 { PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801E_11
, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 16},
655 { PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801DB_10
,PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 17},
656 #ifdef CONFIG_BLK_DEV_IDE_SATA
657 { PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801EB_1
, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 18},
659 { PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ESB_2
, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 19},
660 { PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH6_19
, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 20},
661 { PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH7_21
, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 21},
662 { PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801DB_1
, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 22},
663 { PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ESB2_18
, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 23},
664 { PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH8_6
, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 24},
667 MODULE_DEVICE_TABLE(pci
, piix_pci_tbl
);
669 static struct pci_driver driver
= {
671 .id_table
= piix_pci_tbl
,
672 .probe
= piix_init_one
,
675 static int __init
piix_ide_init(void)
678 return ide_pci_register_driver(&driver
);
681 module_init(piix_ide_init
);
683 MODULE_AUTHOR("Andre Hedrick, Andrzej Krzysztofowicz");
684 MODULE_DESCRIPTION("PCI driver module for Intel PIIX IDE");
685 MODULE_LICENSE("GPL");