2 * linux/drivers/ide/pci/piix.c Version 0.52 Jul 14, 2007
4 * Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer
5 * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
6 * Copyright (C) 2003 Red Hat Inc <alan@redhat.com>
7 * Copyright (C) 2006-2007 MontaVista Software, Inc. <source@mvista.com>
9 * May be copied or modified under the terms of the GNU General Public License
11 * PIO mode setting function for Intel chipsets.
12 * For use instead of BIOS settings.
20 * | PIO 0 | c0 | 80 | 0 |
21 * | PIO 2 | SW2 | d0 | 90 | 4 |
22 * | PIO 3 | MW1 | e1 | a1 | 9 |
23 * | PIO 4 | MW2 | e3 | a3 | b |
25 * sitre = word40 & 0x4000; primary
26 * sitre = word42 & 0x4000; secondary
28 * 44 8421|8421 hdd|hdb
30 * 48 8421 hdd|hdc|hdb|hda udma enabled
42 * ata-33/82801AB ata-66/82801AA
43 * 00|00 udma 0 00|00 reserved
44 * 01|01 udma 1 01|01 udma 3
45 * 10|10 udma 2 10|10 udma 4
46 * 11|11 reserved 11|11 reserved
48 * 54 8421|8421 ata66 drive|ata66 enable
50 * pci_read_config_word(HWIF(drive)->pci_dev, 0x40, ®40);
51 * pci_read_config_word(HWIF(drive)->pci_dev, 0x42, ®42);
52 * pci_read_config_word(HWIF(drive)->pci_dev, 0x44, ®44);
53 * pci_read_config_byte(HWIF(drive)->pci_dev, 0x48, ®48);
54 * pci_read_config_word(HWIF(drive)->pci_dev, 0x4a, ®4a);
55 * pci_read_config_byte(HWIF(drive)->pci_dev, 0x54, ®54);
58 * Publically available from Intel web site. Errata documentation
59 * is also publically available. As an aide to anyone hacking on this
60 * driver the list of errata that are relevant is below.going back to
61 * PIIX4. Older device documentation is now a bit tricky to find.
66 * PIIX4 errata #9 - Only on ultra obscure hw
67 * ICH3 errata #13 - Not observed to affect real hw
70 * Things we must deal with
71 * PIIX4 errata #10 - BM IDE hang with non UDMA
72 * (must stop/start dma to recover)
73 * 440MX errata #15 - As PIIX4 errata #10
74 * PIIX4 errata #15 - Must not read control registers
75 * during a PIO transfer
76 * 440MX errata #13 - As PIIX4 errata #15
77 * ICH2 errata #21 - DMA mode 0 doesn't work right
78 * ICH0/1 errata #55 - As ICH2 errata #21
79 * ICH2 spec c #9 - Extra operations needed to handle
80 * drive hotswap [NOT YET SUPPORTED]
81 * ICH2 spec c #20 - IDE PRD must not cross a 64K boundary
82 * and must be dword aligned
83 * ICH2 spec c #24 - UDMA mode 4,5 t85/86 should be 6ns not 3.3
85 * Should have been BIOS fixed:
86 * 450NX: errata #19 - DMA hangs on old 450NX
87 * 450NX: errata #20 - DMA hangs on old 450NX
88 * 450NX: errata #25 - Corruption with DMA on old 450NX
89 * ICH3 errata #15 - IDE deadlock under high load
90 * (BIOS must set dev 31 fn 0 bit 23)
91 * ICH3 errata #18 - Don't use native mode
94 #include <linux/types.h>
95 #include <linux/module.h>
96 #include <linux/kernel.h>
97 #include <linux/ioport.h>
98 #include <linux/pci.h>
99 #include <linux/hdreg.h>
100 #include <linux/ide.h>
101 #include <linux/delay.h>
102 #include <linux/init.h>
106 static int no_piix_dma
;
109 * piix_dma_2_pio - return the PIO mode matching DMA
110 * @xfer_rate: transfer speed
112 * Returns the nearest equivalent PIO timing for the DMA
113 * mode requested by the controller.
116 static u8
piix_dma_2_pio (u8 xfer_rate
) {
140 * piix_tune_pio - tune PIIX for PIO mode
141 * @drive: drive to tune
142 * @pio: desired PIO mode
144 * Set the interface PIO mode based upon the settings done by AMI BIOS.
146 static void piix_tune_pio (ide_drive_t
*drive
, u8 pio
)
148 ide_hwif_t
*hwif
= HWIF(drive
);
149 struct pci_dev
*dev
= hwif
->pci_dev
;
150 int is_slave
= drive
->dn
& 1;
151 int master_port
= hwif
->channel
? 0x42 : 0x40;
152 int slave_port
= 0x44;
156 static DEFINE_SPINLOCK(tune_lock
);
160 static const u8 timings
[][2]= {
168 * Master vs slave is synchronized above us but the slave register is
169 * shared by the two hwifs so the corner case of two slave timeouts in
170 * parallel must be locked.
172 spin_lock_irqsave(&tune_lock
, flags
);
173 pci_read_config_word(dev
, master_port
, &master_data
);
176 control
|= 1; /* Programmable timing on */
177 if (drive
->media
== ide_disk
)
178 control
|= 4; /* Prefetch, post write */
180 control
|= 2; /* IORDY */
182 master_data
|= 0x4000;
183 master_data
&= ~0x0070;
185 /* Set PPE, IE and TIME */
186 master_data
|= control
<< 4;
188 pci_read_config_byte(dev
, slave_port
, &slave_data
);
189 slave_data
&= hwif
->channel
? 0x0f : 0xf0;
190 slave_data
|= ((timings
[pio
][0] << 2) | timings
[pio
][1]) <<
191 (hwif
->channel
? 4 : 0);
193 master_data
&= ~0x3307;
195 /* enable PPE, IE and TIME */
196 master_data
|= control
;
198 master_data
|= (timings
[pio
][0] << 12) | (timings
[pio
][1] << 8);
200 pci_write_config_word(dev
, master_port
, master_data
);
202 pci_write_config_byte(dev
, slave_port
, slave_data
);
203 spin_unlock_irqrestore(&tune_lock
, flags
);
207 * piix_set_pio_mode - set PIO mode
208 * @drive: drive to tune
209 * @pio: desired PIO mode
211 * Set the drive's PIO mode (might be useful if drive is not registered
212 * in CMOS for any reason).
215 static void piix_set_pio_mode(ide_drive_t
*drive
, const u8 pio
)
217 piix_tune_pio(drive
, pio
);
218 (void) ide_config_drive_speed(drive
, XFER_PIO_0
+ pio
);
222 * piix_tune_chipset - tune a PIIX interface
223 * @drive: IDE drive to tune
224 * @speed: speed to configure
226 * Set a PIIX interface channel to the desired speeds. This involves
227 * requires the right timing data into the PIIX configuration space
228 * then setting the drive parameters appropriately
231 static int piix_tune_chipset(ide_drive_t
*drive
, const u8 speed
)
233 ide_hwif_t
*hwif
= HWIF(drive
);
234 struct pci_dev
*dev
= hwif
->pci_dev
;
235 u8 maslave
= hwif
->channel
? 0x42 : 0x40;
236 int a_speed
= 3 << (drive
->dn
* 4);
237 int u_flag
= 1 << drive
->dn
;
238 int v_flag
= 0x01 << drive
->dn
;
239 int w_flag
= 0x10 << drive
->dn
;
243 u8 reg48
, reg54
, reg55
;
245 pci_read_config_word(dev
, maslave
, ®4042
);
246 sitre
= (reg4042
& 0x4000) ? 1 : 0;
247 pci_read_config_byte(dev
, 0x48, ®48
);
248 pci_read_config_word(dev
, 0x4a, ®4a
);
249 pci_read_config_byte(dev
, 0x54, ®54
);
250 pci_read_config_byte(dev
, 0x55, ®55
);
254 case XFER_UDMA_2
: u_speed
= 2 << (drive
->dn
* 4); break;
257 case XFER_UDMA_1
: u_speed
= 1 << (drive
->dn
* 4); break;
258 case XFER_UDMA_0
: u_speed
= 0 << (drive
->dn
* 4); break;
261 case XFER_SW_DMA_2
: break;
265 if (speed
>= XFER_UDMA_0
) {
266 if (!(reg48
& u_flag
))
267 pci_write_config_byte(dev
, 0x48, reg48
| u_flag
);
268 if (speed
== XFER_UDMA_5
) {
269 pci_write_config_byte(dev
, 0x55, (u8
) reg55
|w_flag
);
271 pci_write_config_byte(dev
, 0x55, (u8
) reg55
& ~w_flag
);
273 if ((reg4a
& a_speed
) != u_speed
)
274 pci_write_config_word(dev
, 0x4a, (reg4a
& ~a_speed
) | u_speed
);
275 if (speed
> XFER_UDMA_2
) {
276 if (!(reg54
& v_flag
))
277 pci_write_config_byte(dev
, 0x54, reg54
| v_flag
);
279 pci_write_config_byte(dev
, 0x54, reg54
& ~v_flag
);
282 pci_write_config_byte(dev
, 0x48, reg48
& ~u_flag
);
284 pci_write_config_word(dev
, 0x4a, reg4a
& ~a_speed
);
286 pci_write_config_byte(dev
, 0x54, reg54
& ~v_flag
);
288 pci_write_config_byte(dev
, 0x55, (u8
) reg55
& ~w_flag
);
291 piix_tune_pio(drive
, piix_dma_2_pio(speed
));
293 return ide_config_drive_speed(drive
, speed
);
297 * piix_config_drive_xfer_rate - set up an IDE device
298 * @drive: IDE drive to configure
300 * Set up the PIIX interface for the best available speed on this
301 * interface, preferring DMA to PIO.
304 static int piix_config_drive_xfer_rate (ide_drive_t
*drive
)
306 drive
->init_speed
= 0;
308 if (ide_tune_dma(drive
))
311 if (ide_use_fast_pio(drive
))
312 ide_set_max_pio(drive
);
318 * piix_is_ichx - check if ICHx
319 * @dev: PCI device to check
321 * returns 1 if ICHx, 0 otherwise.
323 static int piix_is_ichx(struct pci_dev
*dev
)
325 switch (dev
->device
) {
326 case PCI_DEVICE_ID_INTEL_82801EB_1
:
327 case PCI_DEVICE_ID_INTEL_82801AA_1
:
328 case PCI_DEVICE_ID_INTEL_82801AB_1
:
329 case PCI_DEVICE_ID_INTEL_82801BA_8
:
330 case PCI_DEVICE_ID_INTEL_82801BA_9
:
331 case PCI_DEVICE_ID_INTEL_82801CA_10
:
332 case PCI_DEVICE_ID_INTEL_82801CA_11
:
333 case PCI_DEVICE_ID_INTEL_82801DB_1
:
334 case PCI_DEVICE_ID_INTEL_82801DB_10
:
335 case PCI_DEVICE_ID_INTEL_82801DB_11
:
336 case PCI_DEVICE_ID_INTEL_82801EB_11
:
337 case PCI_DEVICE_ID_INTEL_82801E_11
:
338 case PCI_DEVICE_ID_INTEL_ESB_2
:
339 case PCI_DEVICE_ID_INTEL_ICH6_19
:
340 case PCI_DEVICE_ID_INTEL_ICH7_21
:
341 case PCI_DEVICE_ID_INTEL_ESB2_18
:
342 case PCI_DEVICE_ID_INTEL_ICH8_6
:
350 * init_chipset_piix - set up the PIIX chipset
351 * @dev: PCI device to set up
352 * @name: Name of the device
354 * Initialize the PCI device as required. For the PIIX this turns
355 * out to be nice and simple
358 static unsigned int __devinit
init_chipset_piix (struct pci_dev
*dev
, const char *name
)
360 if (piix_is_ichx(dev
)) {
361 unsigned int extra
= 0;
362 pci_read_config_dword(dev
, 0x54, &extra
);
363 pci_write_config_dword(dev
, 0x54, extra
|0x400);
370 * piix_dma_clear_irq - clear BMDMA status
371 * @drive: IDE drive to clear
373 * Called from ide_intr() for PIO interrupts
374 * to clear BMDMA status as needed by ICHx
376 static void piix_dma_clear_irq(ide_drive_t
*drive
)
378 ide_hwif_t
*hwif
= HWIF(drive
);
381 /* clear the INTR & ERROR bits */
382 dma_stat
= hwif
->INB(hwif
->dma_status
);
383 /* Should we force the bit as well ? */
384 hwif
->OUTB(dma_stat
, hwif
->dma_status
);
394 * List of laptops that use short cables rather than 80 wire
397 static const struct ich_laptop ich_laptop
[] = {
398 /* devid, subvendor, subdev */
399 { 0x27DF, 0x0005, 0x0280 }, /* ICH7 on Acer 5602WLMi */
400 { 0x27DF, 0x1025, 0x0110 }, /* ICH7 on Acer 3682WLMi */
401 { 0x27DF, 0x1043, 0x1267 }, /* ICH7 on Asus W5F */
402 { 0x24CA, 0x1025, 0x0061 }, /* ICH4 on Acer Aspire 2023WLMi */
407 static u8 __devinit
piix_cable_detect(ide_hwif_t
*hwif
)
409 struct pci_dev
*pdev
= hwif
->pci_dev
;
410 const struct ich_laptop
*lap
= &ich_laptop
[0];
411 u8 reg54h
= 0, mask
= hwif
->channel
? 0xc0 : 0x30;
413 /* check for specials */
414 while (lap
->device
) {
415 if (lap
->device
== pdev
->device
&&
416 lap
->subvendor
== pdev
->subsystem_vendor
&&
417 lap
->subdevice
== pdev
->subsystem_device
) {
418 return ATA_CBL_PATA40_SHORT
;
423 pci_read_config_byte(pdev
, 0x54, ®54h
);
425 return (reg54h
& mask
) ? ATA_CBL_PATA80
: ATA_CBL_PATA40
;
429 * init_hwif_piix - fill in the hwif for the PIIX
430 * @hwif: IDE interface
432 * Set up the ide_hwif_t for the PIIX interface according to the
433 * capabilities of the hardware.
436 static void __devinit
init_hwif_piix(ide_hwif_t
*hwif
)
440 hwif
->irq
= hwif
->channel
? 15 : 14;
441 #endif /* CONFIG_IA64 */
443 if (hwif
->pci_dev
->device
== PCI_DEVICE_ID_INTEL_82371MX
) {
444 /* This is a painful system best to let it self tune for now */
450 hwif
->set_pio_mode
= &piix_set_pio_mode
;
451 hwif
->speedproc
= &piix_tune_chipset
;
452 hwif
->drives
[0].autotune
= 1;
453 hwif
->drives
[1].autotune
= 1;
458 /* ICHx need to clear the bmdma status for all interrupts */
459 if (piix_is_ichx(hwif
->pci_dev
))
460 hwif
->ide_dma_clear_irq
= &piix_dma_clear_irq
;
464 hwif
->ultra_mask
= hwif
->cds
->udma_mask
;
465 hwif
->mwdma_mask
= 0x06;
466 hwif
->swdma_mask
= 0x04;
468 if (hwif
->ultra_mask
& 0x78) {
469 if (hwif
->cbl
!= ATA_CBL_PATA40_SHORT
)
470 hwif
->cbl
= piix_cable_detect(hwif
);
474 hwif
->ultra_mask
= hwif
->mwdma_mask
= hwif
->swdma_mask
= 0;
476 hwif
->ide_dma_check
= &piix_config_drive_xfer_rate
;
480 hwif
->drives
[1].autodma
= hwif
->autodma
;
481 hwif
->drives
[0].autodma
= hwif
->autodma
;
484 #define DECLARE_PIIX_DEV(name_str, udma) \
487 .init_chipset = init_chipset_piix, \
488 .init_hwif = init_hwif_piix, \
489 .autodma = AUTODMA, \
490 .enablebits = {{0x41,0x80,0x80}, {0x43,0x80,0x80}}, \
491 .bootable = ON_BOARD, \
492 .pio_mask = ATA_PIO4, \
496 static ide_pci_device_t piix_pci_info
[] __devinitdata
= {
497 /* 0 */ DECLARE_PIIX_DEV("PIIXa", 0x00), /* no udma */
498 /* 1 */ DECLARE_PIIX_DEV("PIIXb", 0x00), /* no udma */
502 * MPIIX actually has only a single IDE channel mapped to
503 * the primary or secondary ports depending on the value
504 * of the bit 14 of the IDETIM register at offset 0x6c
507 .init_hwif
= init_hwif_piix
,
509 .enablebits
= {{0x6d,0xc0,0x80}, {0x6d,0xc0,0xc0}},
510 .bootable
= ON_BOARD
,
511 .host_flags
= IDE_HFLAG_ISA_PORTS
,
512 .pio_mask
= ATA_PIO4
,
515 /* 3 */ DECLARE_PIIX_DEV("PIIX3", 0x00), /* no udma */
516 /* 4 */ DECLARE_PIIX_DEV("PIIX4", 0x07), /* udma0-2 */
517 /* 5 */ DECLARE_PIIX_DEV("ICH0", 0x07), /* udma0-2 */
518 /* 6 */ DECLARE_PIIX_DEV("PIIX4", 0x07), /* udma0-2 */
519 /* 7 */ DECLARE_PIIX_DEV("ICH", 0x1f), /* udma0-4 */
520 /* 8 */ DECLARE_PIIX_DEV("PIIX4", 0x1f), /* udma0-4 */
521 /* 9 */ DECLARE_PIIX_DEV("PIIX4", 0x07), /* udma0-2 */
522 /* 10 */ DECLARE_PIIX_DEV("ICH2", 0x3f), /* udma0-5 */
523 /* 11 */ DECLARE_PIIX_DEV("ICH2M", 0x3f), /* udma0-5 */
524 /* 12 */ DECLARE_PIIX_DEV("ICH3M", 0x3f), /* udma0-5 */
525 /* 13 */ DECLARE_PIIX_DEV("ICH3", 0x3f), /* udma0-5 */
526 /* 14 */ DECLARE_PIIX_DEV("ICH4", 0x3f), /* udma0-5 */
527 /* 15 */ DECLARE_PIIX_DEV("ICH5", 0x3f), /* udma0-5 */
528 /* 16 */ DECLARE_PIIX_DEV("C-ICH", 0x3f), /* udma0-5 */
529 /* 17 */ DECLARE_PIIX_DEV("ICH4", 0x3f), /* udma0-5 */
530 /* 18 */ DECLARE_PIIX_DEV("ICH5-SATA", 0x3f), /* udma0-5 */
531 /* 19 */ DECLARE_PIIX_DEV("ICH5", 0x3f), /* udma0-5 */
532 /* 20 */ DECLARE_PIIX_DEV("ICH6", 0x3f), /* udma0-5 */
533 /* 21 */ DECLARE_PIIX_DEV("ICH7", 0x3f), /* udma0-5 */
534 /* 22 */ DECLARE_PIIX_DEV("ICH4", 0x3f), /* udma0-5 */
535 /* 23 */ DECLARE_PIIX_DEV("ESB2", 0x3f), /* udma0-5 */
536 /* 24 */ DECLARE_PIIX_DEV("ICH8M", 0x3f), /* udma0-5 */
540 * piix_init_one - called when a PIIX is found
541 * @dev: the piix device
542 * @id: the matching pci id
544 * Called when the PCI registration layer (or the IDE initialization)
545 * finds a device matching our IDE device tables.
548 static int __devinit
piix_init_one(struct pci_dev
*dev
, const struct pci_device_id
*id
)
550 ide_pci_device_t
*d
= &piix_pci_info
[id
->driver_data
];
552 return ide_setup_pci_device(dev
, d
);
556 * piix_check_450nx - Check for problem 450NX setup
558 * Check for the present of 450NX errata #19 and errata #25. If
559 * they are found, disable use of DMA IDE
562 static void __devinit
piix_check_450nx(void)
564 struct pci_dev
*pdev
= NULL
;
566 while((pdev
=pci_get_device(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82454NX
, pdev
))!=NULL
)
568 /* Look for 450NX PXB. Check for problem configurations
569 A PCI quirk checks bit 6 already */
570 pci_read_config_word(pdev
, 0x41, &cfg
);
571 /* Only on the original revision: IDE DMA can hang */
572 if (pdev
->revision
== 0x00)
574 /* On all revisions below 5 PXB bus lock must be disabled for IDE */
575 else if (cfg
& (1<<14) && pdev
->revision
< 5)
579 printk(KERN_WARNING
"piix: 450NX errata present, disabling IDE DMA.\n");
581 printk(KERN_WARNING
"piix: A BIOS update may resolve this.\n");
584 static struct pci_device_id piix_pci_tbl
[] = {
585 { PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82371FB_0
, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0},
586 { PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82371FB_1
, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 1},
587 { PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82371MX
, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 2},
588 { PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82371SB_1
, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 3},
589 { PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82371AB
, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 4},
590 { PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801AB_1
, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 5},
591 { PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82443MX_1
, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 6},
592 { PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801AA_1
, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 7},
593 { PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82372FB_1
, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 8},
594 { PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82451NX
, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 9},
595 { PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801BA_9
, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 10},
596 { PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801BA_8
, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 11},
597 { PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801CA_10
,PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 12},
598 { PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801CA_11
,PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 13},
599 { PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801DB_11
,PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 14},
600 { PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801EB_11
,PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 15},
601 { PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801E_11
, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 16},
602 { PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801DB_10
,PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 17},
603 #ifdef CONFIG_BLK_DEV_IDE_SATA
604 { PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801EB_1
, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 18},
606 { PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ESB_2
, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 19},
607 { PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH6_19
, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 20},
608 { PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH7_21
, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 21},
609 { PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801DB_1
, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 22},
610 { PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ESB2_18
, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 23},
611 { PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH8_6
, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 24},
614 MODULE_DEVICE_TABLE(pci
, piix_pci_tbl
);
616 static struct pci_driver driver
= {
618 .id_table
= piix_pci_tbl
,
619 .probe
= piix_init_one
,
622 static int __init
piix_ide_init(void)
625 return ide_pci_register_driver(&driver
);
628 module_init(piix_ide_init
);
630 MODULE_AUTHOR("Andre Hedrick, Andrzej Krzysztofowicz");
631 MODULE_DESCRIPTION("PCI driver module for Intel PIIX IDE");
632 MODULE_LICENSE("GPL");