2 * linux/drivers/ide/pci/sc1200.c Version 0.95 Jun 16 2007
4 * Copyright (C) 2000-2002 Mark Lord <mlord@pobox.com>
5 * Copyright (C) 2007 Bartlomiej Zolnierkiewicz
7 * May be copied or modified under the terms of the GNU General Public License
9 * Development of this chipset driver was funded
10 * by the nice folks at National Semiconductor.
13 * Available from National Semiconductor
16 #include <linux/module.h>
17 #include <linux/types.h>
18 #include <linux/kernel.h>
19 #include <linux/delay.h>
20 #include <linux/timer.h>
22 #include <linux/ioport.h>
23 #include <linux/blkdev.h>
24 #include <linux/hdreg.h>
25 #include <linux/interrupt.h>
26 #include <linux/pci.h>
27 #include <linux/init.h>
28 #include <linux/ide.h>
33 #define SC1200_REV_A 0x00
34 #define SC1200_REV_B1 0x01
35 #define SC1200_REV_B3 0x02
36 #define SC1200_REV_C1 0x03
37 #define SC1200_REV_D1 0x04
39 #define PCI_CLK_33 0x00
40 #define PCI_CLK_48 0x01
41 #define PCI_CLK_66 0x02
42 #define PCI_CLK_33A 0x03
44 static unsigned short sc1200_get_pci_clock (void)
46 unsigned char chip_id
, silicon_revision
;
47 unsigned int pci_clock
;
49 * Check the silicon revision, as not all versions of the chip
50 * have the register with the fast PCI bus timings.
52 chip_id
= inb (0x903c);
53 silicon_revision
= inb (0x903d);
55 // Read the fast pci clock frequency
56 if (chip_id
== 0x04 && silicon_revision
< SC1200_REV_B1
) {
57 pci_clock
= PCI_CLK_33
;
59 // check clock generator configuration (cfcc)
60 // the clock is in bits 8 and 9 of this word
62 pci_clock
= inw (0x901e);
65 if (pci_clock
== PCI_CLK_33A
)
66 pci_clock
= PCI_CLK_33
;
71 extern char *ide_xfer_verbose (byte xfer_rate
);
74 * Set a new transfer mode at the drive
76 static int sc1200_set_xfer_mode (ide_drive_t
*drive
, byte mode
)
78 printk("%s: sc1200_set_xfer_mode(%s)\n", drive
->name
, ide_xfer_verbose(mode
));
79 return ide_config_drive_speed(drive
, mode
);
83 * Here are the standard PIO mode 0-4 timings for each "format".
84 * Format-0 uses fast data reg timings, with slower command reg timings.
85 * Format-1 uses fast timings for all registers, but won't work with all drives.
87 static const unsigned int sc1200_pio_timings
[4][5] =
88 {{0x00009172, 0x00012171, 0x00020080, 0x00032010, 0x00040010}, // format0 33Mhz
89 {0xd1329172, 0x71212171, 0x30200080, 0x20102010, 0x00100010}, // format1, 33Mhz
90 {0xfaa3f4f3, 0xc23232b2, 0x513101c1, 0x31213121, 0x10211021}, // format1, 48Mhz
91 {0xfff4fff4, 0xf35353d3, 0x814102f1, 0x42314231, 0x11311131}}; // format1, 66Mhz
94 * After chip reset, the PIO timings are set to 0x00009172, which is not valid.
96 //#define SC1200_BAD_PIO(timings) (((timings)&~0x80000000)==0x00009172)
98 static void sc1200_tunepio(ide_drive_t
*drive
, u8 pio
)
100 ide_hwif_t
*hwif
= drive
->hwif
;
101 struct pci_dev
*pdev
= hwif
->pci_dev
;
102 unsigned int basereg
= hwif
->channel
? 0x50 : 0x40, format
= 0;
104 pci_read_config_dword(pdev
, basereg
+ 4, &format
);
105 format
= (format
>> 31) & 1;
107 format
+= sc1200_get_pci_clock();
108 pci_write_config_dword(pdev
, basereg
+ ((drive
->dn
& 1) << 3),
109 sc1200_pio_timings
[format
][pio
]);
113 * The SC1200 specifies that two drives sharing a cable cannot mix
114 * UDMA/MDMA. It has to be one or the other, for the pair, though
115 * different timings can still be chosen for each drive. We could
116 * set the appropriate timing bits on the fly, but that might be
117 * a bit confusing. So, for now we statically handle this requirement
118 * by looking at our mate drive to see what it is capable of, before
119 * choosing a mode for our own drive.
121 static u8
sc1200_udma_filter(ide_drive_t
*drive
)
123 ide_hwif_t
*hwif
= drive
->hwif
;
124 ide_drive_t
*mate
= &hwif
->drives
[(drive
->dn
& 1) ^ 1];
125 struct hd_driveid
*mateid
= mate
->id
;
126 u8 mask
= hwif
->ultra_mask
;
128 if (mate
->present
== 0)
131 if ((mateid
->capability
& 1) && __ide_dma_bad_drive(mate
) == 0) {
132 if ((mateid
->field_valid
& 4) && (mateid
->dma_ultra
& 7))
134 if ((mateid
->field_valid
& 2) && (mateid
->dma_mword
& 7))
141 static int sc1200_tune_chipset(ide_drive_t
*drive
, u8 mode
)
143 ide_hwif_t
*hwif
= HWIF(drive
);
144 int unit
= drive
->select
.b
.unit
;
145 unsigned int reg
, timings
;
146 unsigned short pci_clock
;
147 unsigned int basereg
= hwif
->channel
? 0x50 : 0x40;
149 mode
= ide_rate_filter(drive
, mode
);
152 * Tell the drive to switch to the new mode; abort on failure.
154 if (sc1200_set_xfer_mode(drive
, mode
)) {
155 printk("SC1200: set xfer mode failure\n");
156 return 1; /* failure */
165 sc1200_tunepio(drive
, mode
- XFER_PIO_0
);
169 pci_clock
= sc1200_get_pci_clock();
172 * Now tune the chipset to match the drive:
174 * Note that each DMA mode has several timings associated with it.
175 * The correct timing depends on the fast PCI clock freq.
181 case PCI_CLK_33
: timings
= 0x00921250; break;
182 case PCI_CLK_48
: timings
= 0x00932470; break;
183 case PCI_CLK_66
: timings
= 0x009436a1; break;
188 case PCI_CLK_33
: timings
= 0x00911140; break;
189 case PCI_CLK_48
: timings
= 0x00922260; break;
190 case PCI_CLK_66
: timings
= 0x00933481; break;
195 case PCI_CLK_33
: timings
= 0x00911030; break;
196 case PCI_CLK_48
: timings
= 0x00922140; break;
197 case PCI_CLK_66
: timings
= 0x00923261; break;
202 case PCI_CLK_33
: timings
= 0x00077771; break;
203 case PCI_CLK_48
: timings
= 0x000bbbb2; break;
204 case PCI_CLK_66
: timings
= 0x000ffff3; break;
209 case PCI_CLK_33
: timings
= 0x00012121; break;
210 case PCI_CLK_48
: timings
= 0x00024241; break;
211 case PCI_CLK_66
: timings
= 0x00035352; break;
216 case PCI_CLK_33
: timings
= 0x00002020; break;
217 case PCI_CLK_48
: timings
= 0x00013131; break;
218 case PCI_CLK_66
: timings
= 0x00015151; break;
226 if (unit
== 0) { /* are we configuring drive0? */
227 pci_read_config_dword(hwif
->pci_dev
, basereg
+4, ®
);
228 timings
|= reg
& 0x80000000; /* preserve PIO format bit */
229 pci_write_config_dword(hwif
->pci_dev
, basereg
+4, timings
);
231 pci_write_config_dword(hwif
->pci_dev
, basereg
+12, timings
);
234 return 0; /* success */
238 * sc1200_config_dma() handles selection/setting of DMA/UDMA modes
239 * for both the chipset and drive.
241 static int sc1200_config_dma (ide_drive_t
*drive
)
243 if (ide_tune_dma(drive
))
250 /* Replacement for the standard ide_dma_end action in
253 * returns 1 on error, 0 otherwise
255 static int sc1200_ide_dma_end (ide_drive_t
*drive
)
257 ide_hwif_t
*hwif
= HWIF(drive
);
258 unsigned long dma_base
= hwif
->dma_base
;
261 dma_stat
= inb(dma_base
+2); /* get DMA status */
264 printk(" ide_dma_end dma_stat=%0x err=%x newerr=%x\n",
265 dma_stat
, ((dma_stat
&7)!=4), ((dma_stat
&2)==2));
267 outb(dma_stat
|0x1b, dma_base
+2); /* clear the INTR & ERROR bits */
268 outb(inb(dma_base
)&~1, dma_base
); /* !! DO THIS HERE !! stop DMA */
270 drive
->waiting_for_dma
= 0;
271 ide_destroy_dmatable(drive
); /* purge DMA mappings */
273 return (dma_stat
& 7) != 4; /* verify good DMA status */
277 * sc1200_tuneproc() handles selection/setting of PIO modes
278 * for both the chipset and drive.
280 * All existing BIOSs for this chipset guarantee that all drives
281 * will have valid default PIO timings set up before we get here.
283 static void sc1200_tuneproc (ide_drive_t
*drive
, byte pio
) /* mode=255 means "autotune" */
285 ide_hwif_t
*hwif
= HWIF(drive
);
289 * bad abuse of ->tuneproc interface
292 case 200: mode
= XFER_UDMA_0
; break;
293 case 201: mode
= XFER_UDMA_1
; break;
294 case 202: mode
= XFER_UDMA_2
; break;
295 case 100: mode
= XFER_MW_DMA_0
; break;
296 case 101: mode
= XFER_MW_DMA_1
; break;
297 case 102: mode
= XFER_MW_DMA_2
; break;
300 printk("SC1200: %s: changing (U)DMA mode\n", drive
->name
);
301 hwif
->dma_off_quietly(drive
);
302 if (sc1200_tune_chipset(drive
, mode
) == 0)
303 hwif
->dma_host_on(drive
);
307 pio
= ide_get_best_pio_mode(drive
, pio
, 4);
308 printk("SC1200: %s: setting PIO mode%d\n", drive
->name
, pio
);
310 if (sc1200_set_xfer_mode(drive
, XFER_PIO_0
+ pio
) == 0)
311 sc1200_tunepio(drive
, pio
);
315 static ide_hwif_t
*lookup_pci_dev (ide_hwif_t
*prev
, struct pci_dev
*dev
)
319 for (h
= 0; h
< MAX_HWIFS
; h
++) {
320 ide_hwif_t
*hwif
= &ide_hwifs
[h
];
323 prev
= NULL
; // found previous, now look for next match
325 if (hwif
&& hwif
->pci_dev
== dev
)
326 return hwif
; // found next match
329 return NULL
; // not found
332 typedef struct sc1200_saved_state_s
{
334 } sc1200_saved_state_t
;
337 static int sc1200_suspend (struct pci_dev
*dev
, pm_message_t state
)
339 ide_hwif_t
*hwif
= NULL
;
341 printk("SC1200: suspend(%u)\n", state
.event
);
343 if (state
.event
== PM_EVENT_ON
) {
344 // we only save state when going from full power to less
347 // Loop over all interfaces that are part of this PCI device:
349 while ((hwif
= lookup_pci_dev(hwif
, dev
)) != NULL
) {
350 sc1200_saved_state_t
*ss
;
351 unsigned int basereg
, r
;
353 // allocate a permanent save area, if not already allocated
355 ss
= (sc1200_saved_state_t
*)hwif
->config_data
;
357 ss
= kmalloc(sizeof(sc1200_saved_state_t
), GFP_KERNEL
);
360 hwif
->config_data
= (unsigned long)ss
;
362 ss
= (sc1200_saved_state_t
*)hwif
->config_data
;
364 // Save timing registers: this may be unnecessary if
367 basereg
= hwif
->channel
? 0x50 : 0x40;
368 for (r
= 0; r
< 4; ++r
) {
369 pci_read_config_dword (hwif
->pci_dev
, basereg
+ (r
<<2), &ss
->regs
[r
]);
374 /* You don't need to iterate over disks -- sysfs should have done that for you already */
376 pci_disable_device(dev
);
377 pci_set_power_state(dev
, pci_choose_state(dev
, state
));
378 dev
->current_state
= state
.event
;
382 static int sc1200_resume (struct pci_dev
*dev
)
384 ide_hwif_t
*hwif
= NULL
;
386 pci_set_power_state(dev
, PCI_D0
); // bring chip back from sleep state
387 dev
->current_state
= PM_EVENT_ON
;
388 pci_enable_device(dev
);
390 // loop over all interfaces that are part of this pci device:
392 while ((hwif
= lookup_pci_dev(hwif
, dev
)) != NULL
) {
393 unsigned int basereg
, r
;
394 sc1200_saved_state_t
*ss
= (sc1200_saved_state_t
*)hwif
->config_data
;
397 // Restore timing registers: this may be unnecessary if BIOS also does it
399 basereg
= hwif
->channel
? 0x50 : 0x40;
401 for (r
= 0; r
< 4; ++r
) {
402 pci_write_config_dword(hwif
->pci_dev
, basereg
+ (r
<<2), ss
->regs
[r
]);
411 * This gets invoked by the IDE driver once for each channel,
412 * and performs channel-specific pre-initialization before drive probing.
414 static void __devinit
init_hwif_sc1200 (ide_hwif_t
*hwif
)
417 hwif
->serialized
= hwif
->mate
->serialized
= 1;
419 if (hwif
->dma_base
) {
420 hwif
->udma_filter
= sc1200_udma_filter
;
421 hwif
->ide_dma_check
= &sc1200_config_dma
;
422 hwif
->ide_dma_end
= &sc1200_ide_dma_end
;
425 hwif
->tuneproc
= &sc1200_tuneproc
;
426 hwif
->speedproc
= &sc1200_tune_chipset
;
429 hwif
->ultra_mask
= 0x07;
430 hwif
->mwdma_mask
= 0x07;
432 hwif
->drives
[0].autodma
= hwif
->autodma
;
433 hwif
->drives
[1].autodma
= hwif
->autodma
;
436 static ide_pci_device_t sc1200_chipset __devinitdata
= {
438 .init_hwif
= init_hwif_sc1200
,
440 .bootable
= ON_BOARD
,
443 static int __devinit
sc1200_init_one(struct pci_dev
*dev
, const struct pci_device_id
*id
)
445 return ide_setup_pci_device(dev
, &sc1200_chipset
);
448 static struct pci_device_id sc1200_pci_tbl
[] = {
449 { PCI_DEVICE(PCI_VENDOR_ID_NS
, PCI_DEVICE_ID_NS_SCx200_IDE
), 0},
452 MODULE_DEVICE_TABLE(pci
, sc1200_pci_tbl
);
454 static struct pci_driver driver
= {
455 .name
= "SC1200_IDE",
456 .id_table
= sc1200_pci_tbl
,
457 .probe
= sc1200_init_one
,
459 .suspend
= sc1200_suspend
,
460 .resume
= sc1200_resume
,
464 static int __init
sc1200_ide_init(void)
466 return ide_pci_register_driver(&driver
);
469 module_init(sc1200_ide_init
);
471 MODULE_AUTHOR("Mark Lord");
472 MODULE_DESCRIPTION("PCI driver module for NS SC1200 IDE");
473 MODULE_LICENSE("GPL");