drivers/ide/pci/scc_pata.c

   1 /*
   2  * Support for IDE interfaces on Celleb platform
   3  *
   4  * (C) Copyright 2006 TOSHIBA CORPORATION
   5  *
   6  * This code is based on drivers/ide/pci/siimage.c:
   7  * Copyright (C) 2001-2002      Andre Hedrick <andre@linux-ide.org>
   8  * Copyright (C) 2003           Red Hat <alan@redhat.com>
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License as published by
  12  * the Free Software Foundation; either version 2 of the License, or
  13  * (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License along
  21  * with this program; if not, write to the Free Software Foundation, Inc.,
  22  * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
  23  */
  24
  25 #include <linux/types.h>
  26 #include <linux/module.h>
  27 #include <linux/pci.h>
  28 #include <linux/delay.h>
  29 #include <linux/hdreg.h>
  30 #include <linux/ide.h>
  31 #include <linux/init.h>
  32
  33 #define PCI_DEVICE_ID_TOSHIBA_SCC_ATA            0x01b4
  34
  35 #define SCC_PATA_NAME           "scc IDE"
  36
  37 #define TDVHSEL_MASTER          0x00000001
  38 #define TDVHSEL_SLAVE           0x00000004
  39
  40 #define MODE_JCUSFEN            0x00000080
  41
  42 #define CCKCTRL_ATARESET        0x00040000
  43 #define CCKCTRL_BUFCNT          0x00020000
  44 #define CCKCTRL_CRST            0x00010000
  45 #define CCKCTRL_OCLKEN          0x00000100
  46 #define CCKCTRL_ATACLKOEN       0x00000002
  47 #define CCKCTRL_LCLKEN          0x00000001
  48
  49 #define QCHCD_IOS_SS            0x00000001
  50
  51 #define QCHSD_STPDIAG           0x00020000
  52
  53 #define INTMASK_MSK             0xD1000012
  54 #define INTSTS_SERROR           0x80000000
  55 #define INTSTS_PRERR            0x40000000
  56 #define INTSTS_RERR             0x10000000
  57 #define INTSTS_ICERR            0x01000000
  58 #define INTSTS_BMSINT           0x00000010
  59 #define INTSTS_BMHE             0x00000008
  60 #define INTSTS_IOIRQS           0x00000004
  61 #define INTSTS_INTRQ            0x00000002
  62 #define INTSTS_ACTEINT          0x00000001
  63
  64 #define ECMODE_VALUE 0x01
  65
  66 static struct scc_ports {
  67         unsigned long ctl, dma;
  68         unsigned char hwif_id;  /* for removing hwif from system */
  69 } scc_ports[MAX_HWIFS];
  70
  71 /* PIO transfer mode  table */
  72 /* JCHST */
  73 static unsigned long JCHSTtbl[2][7] = {
  74         {0x0E, 0x05, 0x02, 0x03, 0x02, 0x00, 0x00},   /* 100MHz */
  75         {0x13, 0x07, 0x04, 0x04, 0x03, 0x00, 0x00}    /* 133MHz */
  76 };
  77
  78 /* JCHHT */
  79 static unsigned long JCHHTtbl[2][7] = {
  80         {0x0E, 0x02, 0x02, 0x02, 0x02, 0x00, 0x00},   /* 100MHz */
  81         {0x13, 0x03, 0x03, 0x03, 0x03, 0x00, 0x00}    /* 133MHz */
  82 };
  83
  84 /* JCHCT */
  85 static unsigned long JCHCTtbl[2][7] = {
  86         {0x1D, 0x1D, 0x1C, 0x0B, 0x06, 0x00, 0x00},   /* 100MHz */
  87         {0x27, 0x26, 0x26, 0x0E, 0x09, 0x00, 0x00}    /* 133MHz */
  88 };
  89
  90
  91 /* DMA transfer mode  table */
  92 /* JCHDCTM/JCHDCTS */
  93 static unsigned long JCHDCTxtbl[2][7] = {
  94         {0x0A, 0x06, 0x04, 0x03, 0x01, 0x00, 0x00},   /* 100MHz */
  95         {0x0E, 0x09, 0x06, 0x04, 0x02, 0x01, 0x00}    /* 133MHz */
  96 };
  97
  98 /* JCSTWTM/JCSTWTS  */
  99 static unsigned long JCSTWTxtbl[2][7] = {
 100         {0x06, 0x04, 0x03, 0x02, 0x02, 0x02, 0x00},   /* 100MHz */
 101         {0x09, 0x06, 0x04, 0x02, 0x02, 0x02, 0x02}    /* 133MHz */
 102 };
 103
 104 /* JCTSS */
 105 static unsigned long JCTSStbl[2][7] = {
 106         {0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x00},   /* 100MHz */
 107         {0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05}    /* 133MHz */
 108 };
 109
 110 /* JCENVT */
 111 static unsigned long JCENVTtbl[2][7] = {
 112         {0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x00},   /* 100MHz */
 113         {0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02}    /* 133MHz */
 114 };
 115
 116 /* JCACTSELS/JCACTSELM */
 117 static unsigned long JCACTSELtbl[2][7] = {
 118         {0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00},   /* 100MHz */
 119         {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01}    /* 133MHz */
 120 };
 121
 122
 123 static u8 scc_ide_inb(unsigned long port)
 124 {
 125         u32 data = in_be32((void*)port);
 126         return (u8)data;
 127 }
 128
 129 static u16 scc_ide_inw(unsigned long port)
 130 {
 131         u32 data = in_be32((void*)port);
 132         return (u16)data;
 133 }
 134
 135 static void scc_ide_insw(unsigned long port, void *addr, u32 count)
 136 {
 137         u16 *ptr = (u16 *)addr;
 138         while (count--) {
 139                 *ptr++ = le16_to_cpu(in_be32((void*)port));
 140         }
 141 }
 142
 143 static void scc_ide_insl(unsigned long port, void *addr, u32 count)
 144 {
 145         u16 *ptr = (u16 *)addr;
 146         while (count--) {
 147                 *ptr++ = le16_to_cpu(in_be32((void*)port));
 148                 *ptr++ = le16_to_cpu(in_be32((void*)port));
 149         }
 150 }
 151
 152 static void scc_ide_outb(u8 addr, unsigned long port)
 153 {
 154         out_be32((void*)port, addr);
 155 }
 156
 157 static void scc_ide_outw(u16 addr, unsigned long port)
 158 {
 159         out_be32((void*)port, addr);
 160 }
 161
 162 static void
 163 scc_ide_outbsync(ide_drive_t * drive, u8 addr, unsigned long port)
 164 {
 165         ide_hwif_t *hwif = HWIF(drive);
 166
 167         out_be32((void*)port, addr);
 168         eieio();
 169         in_be32((void*)(hwif->dma_base + 0x01c));
 170         eieio();
 171 }
 172
 173 static void
 174 scc_ide_outsw(unsigned long port, void *addr, u32 count)
 175 {
 176         u16 *ptr = (u16 *)addr;
 177         while (count--) {
 178                 out_be32((void*)port, cpu_to_le16(*ptr++));
 179         }
 180 }
 181
 182 static void
 183 scc_ide_outsl(unsigned long port, void *addr, u32 count)
 184 {
 185         u16 *ptr = (u16 *)addr;
 186         while (count--) {
 187                 out_be32((void*)port, cpu_to_le16(*ptr++));
 188                 out_be32((void*)port, cpu_to_le16(*ptr++));
 189         }
 190 }
 191
 192 /**
 193  *      scc_set_pio_mode        -       set host controller for PIO mode
 194  *      @drive: drive
 195  *      @pio: PIO mode number
 196  *
 197  *      Load the timing settings for this device mode into the
 198  *      controller.
 199  */
 200
 201 static void scc_set_pio_mode(ide_drive_t *drive, const u8 pio)
 202 {
 203         ide_hwif_t *hwif = HWIF(drive);
 204         struct scc_ports *ports = ide_get_hwifdata(hwif);
 205         unsigned long ctl_base = ports->ctl;
 206         unsigned long cckctrl_port = ctl_base + 0xff0;
 207         unsigned long piosht_port = ctl_base + 0x000;
 208         unsigned long pioct_port = ctl_base + 0x004;
 209         unsigned long reg;
 210         int offset;
 211
 212         reg = in_be32((void __iomem *)cckctrl_port);
 213         if (reg & CCKCTRL_ATACLKOEN) {
 214                 offset = 1; /* 133MHz */
 215         } else {
 216                 offset = 0; /* 100MHz */
 217         }
 218         reg = JCHSTtbl[offset][pio] << 16 | JCHHTtbl[offset][pio];
 219         out_be32((void __iomem *)piosht_port, reg);
 220         reg = JCHCTtbl[offset][pio];
 221         out_be32((void __iomem *)pioct_port, reg);
 222 }
 223
 224 /**
 225  *      scc_set_dma_mode        -       set host controller for DMA mode
 226  *      @drive: drive
 227  *      @speed: DMA mode
 228  *
 229  *      Load the timing settings for this device mode into the
 230  *      controller.
 231  */
 232
 233 static void scc_set_dma_mode(ide_drive_t *drive, const u8 speed)
 234 {
 235         ide_hwif_t *hwif = HWIF(drive);
 236         struct scc_ports *ports = ide_get_hwifdata(hwif);
 237         unsigned long ctl_base = ports->ctl;
 238         unsigned long cckctrl_port = ctl_base + 0xff0;
 239         unsigned long mdmact_port = ctl_base + 0x008;
 240         unsigned long mcrcst_port = ctl_base + 0x00c;
 241         unsigned long sdmact_port = ctl_base + 0x010;
 242         unsigned long scrcst_port = ctl_base + 0x014;
 243         unsigned long udenvt_port = ctl_base + 0x018;
 244         unsigned long tdvhsel_port   = ctl_base + 0x020;
 245         int is_slave = (&hwif->drives[1] == drive);
 246         int offset, idx;
 247         unsigned long reg;
 248         unsigned long jcactsel;
 249
 250         reg = in_be32((void __iomem *)cckctrl_port);
 251         if (reg & CCKCTRL_ATACLKOEN) {
 252                 offset = 1; /* 133MHz */
 253         } else {
 254                 offset = 0; /* 100MHz */
 255         }
 256
 257         idx = speed - XFER_UDMA_0;
 258
 259         jcactsel = JCACTSELtbl[offset][idx];
 260         if (is_slave) {
 261                 out_be32((void __iomem *)sdmact_port, JCHDCTxtbl[offset][idx]);
 262                 out_be32((void __iomem *)scrcst_port, JCSTWTxtbl[offset][idx]);
 263                 jcactsel = jcactsel << 2;
 264                 out_be32((void __iomem *)tdvhsel_port, (in_be32((void __iomem *)tdvhsel_port) & ~TDVHSEL_SLAVE) | jcactsel);
 265         } else {
 266                 out_be32((void __iomem *)mdmact_port, JCHDCTxtbl[offset][idx]);
 267                 out_be32((void __iomem *)mcrcst_port, JCSTWTxtbl[offset][idx]);
 268                 out_be32((void __iomem *)tdvhsel_port, (in_be32((void __iomem *)tdvhsel_port) & ~TDVHSEL_MASTER) | jcactsel);
 269         }
 270         reg = JCTSStbl[offset][idx] << 16 | JCENVTtbl[offset][idx];
 271         out_be32((void __iomem *)udenvt_port, reg);
 272 }
 273
 274 /**
 275  *      scc_ide_dma_setup       -       begin a DMA phase
 276  *      @drive: target device
 277  *
 278  *      Build an IDE DMA PRD (IDE speak for scatter gather table)
 279  *      and then set up the DMA transfer registers.
 280  *
 281  *      Returns 0 on success. If a PIO fallback is required then 1
 282  *      is returned.
 283  */
 284
 285 static int scc_dma_setup(ide_drive_t *drive)
 286 {
 287         ide_hwif_t *hwif = drive->hwif;
 288         struct request *rq = HWGROUP(drive)->rq;
 289         unsigned int reading;
 290         u8 dma_stat;
 291
 292         if (rq_data_dir(rq))
 293                 reading = 0;
 294         else
 295                 reading = 1 << 3;
 296
 297         /* fall back to pio! */
 298         if (!ide_build_dmatable(drive, rq)) {
 299                 ide_map_sg(drive, rq);
 300                 return 1;
 301         }
 302
 303         /* PRD table */
 304         out_be32((void __iomem *)hwif->dma_prdtable, hwif->dmatable_dma);
 305
 306         /* specify r/w */
 307         out_be32((void __iomem *)hwif->dma_command, reading);
 308
 309         /* read dma_status for INTR & ERROR flags */
 310         dma_stat = in_be32((void __iomem *)hwif->dma_status);
 311
 312         /* clear INTR & ERROR flags */
 313         out_be32((void __iomem *)hwif->dma_status, dma_stat|6);
 314         drive->waiting_for_dma = 1;
 315         return 0;
 316 }
 317
 318
 319 /**
 320  *      scc_ide_dma_end -       Stop DMA
 321  *      @drive: IDE drive
 322  *
 323  *      Check and clear INT Status register.
 324  *      Then call __ide_dma_end().
 325  */
 326
 327 static int scc_ide_dma_end(ide_drive_t * drive)
 328 {
 329         ide_hwif_t *hwif = HWIF(drive);
 330         unsigned long intsts_port = hwif->dma_base + 0x014;
 331         u32 reg;
 332         int dma_stat, data_loss = 0;
 333         static int retry = 0;
 334
 335         /* errata A308 workaround: Step5 (check data loss) */
 336         /* We don't check non ide_disk because it is limited to UDMA4 */
 337         if (!(in_be32((void __iomem *)IDE_ALTSTATUS_REG) & ERR_STAT) &&
 338             drive->media == ide_disk && drive->current_speed > XFER_UDMA_4) {
 339                 reg = in_be32((void __iomem *)intsts_port);
 340                 if (!(reg & INTSTS_ACTEINT)) {
 341                         printk(KERN_WARNING "%s: operation failed (transfer data loss)\n",
 342                                drive->name);
 343                         data_loss = 1;
 344                         if (retry++) {
 345                                 struct request *rq = HWGROUP(drive)->rq;
 346                                 int unit;
 347                                 /* ERROR_RESET and drive->crc_count are needed
 348                                  * to reduce DMA transfer mode in retry process.
 349                                  */
 350                                 if (rq)
 351                                         rq->errors |= ERROR_RESET;
 352                                 for (unit = 0; unit < MAX_DRIVES; unit++) {
 353                                         ide_drive_t *drive = &hwif->drives[unit];
 354                                         drive->crc_count++;
 355                                 }
 356                         }
 357                 }
 358         }
 359
 360         while (1) {
 361                 reg = in_be32((void __iomem *)intsts_port);
 362
 363                 if (reg & INTSTS_SERROR) {
 364                         printk(KERN_WARNING "%s: SERROR\n", SCC_PATA_NAME);
 365                         out_be32((void __iomem *)intsts_port, INTSTS_SERROR|INTSTS_BMSINT);
 366
 367                         out_be32((void __iomem *)hwif->dma_command, in_be32((void __iomem *)hwif->dma_command) & ~QCHCD_IOS_SS);
 368                         continue;
 369                 }
 370
 371                 if (reg & INTSTS_PRERR) {
 372                         u32 maea0, maec0;
 373                         unsigned long ctl_base = hwif->config_data;
 374
 375                         maea0 = in_be32((void __iomem *)(ctl_base + 0xF50));
 376                         maec0 = in_be32((void __iomem *)(ctl_base + 0xF54));
 377
 378                         printk(KERN_WARNING "%s: PRERR [addr:%x cmd:%x]\n", SCC_PATA_NAME, maea0, maec0);
 379
 380                         out_be32((void __iomem *)intsts_port, INTSTS_PRERR|INTSTS_BMSINT);
 381
 382                         out_be32((void __iomem *)hwif->dma_command, in_be32((void __iomem *)hwif->dma_command) & ~QCHCD_IOS_SS);
 383                         continue;
 384                 }
 385
 386                 if (reg & INTSTS_RERR) {
 387                         printk(KERN_WARNING "%s: Response Error\n", SCC_PATA_NAME);
 388                         out_be32((void __iomem *)intsts_port, INTSTS_RERR|INTSTS_BMSINT);
 389
 390                         out_be32((void __iomem *)hwif->dma_command, in_be32((void __iomem *)hwif->dma_command) & ~QCHCD_IOS_SS);
 391                         continue;
 392                 }
 393
 394                 if (reg & INTSTS_ICERR) {
 395                         out_be32((void __iomem *)hwif->dma_command, in_be32((void __iomem *)hwif->dma_command) & ~QCHCD_IOS_SS);
 396
 397                         printk(KERN_WARNING "%s: Illegal Configuration\n", SCC_PATA_NAME);
 398                         out_be32((void __iomem *)intsts_port, INTSTS_ICERR|INTSTS_BMSINT);
 399                         continue;
 400                 }
 401
 402                 if (reg & INTSTS_BMSINT) {
 403                         printk(KERN_WARNING "%s: Internal Bus Error\n", SCC_PATA_NAME);
 404                         out_be32((void __iomem *)intsts_port, INTSTS_BMSINT);
 405
 406                         ide_do_reset(drive);
 407                         continue;
 408                 }
 409
 410                 if (reg & INTSTS_BMHE) {
 411                         out_be32((void __iomem *)intsts_port, INTSTS_BMHE);
 412                         continue;
 413                 }
 414
 415                 if (reg & INTSTS_ACTEINT) {
 416                         out_be32((void __iomem *)intsts_port, INTSTS_ACTEINT);
 417                         continue;
 418                 }
 419
 420                 if (reg & INTSTS_IOIRQS) {
 421                         out_be32((void __iomem *)intsts_port, INTSTS_IOIRQS);
 422                         continue;
 423                 }
 424                 break;
 425         }
 426
 427         dma_stat = __ide_dma_end(drive);
 428         if (data_loss)
 429                 dma_stat |= 2; /* emulate DMA error (to retry command) */
 430         return dma_stat;
 431 }
 432
 433 /* returns 1 if dma irq issued, 0 otherwise */
 434 static int scc_dma_test_irq(ide_drive_t *drive)
 435 {
 436         ide_hwif_t *hwif = HWIF(drive);
 437         u32 int_stat = in_be32((void __iomem *)hwif->dma_base + 0x014);
 438
 439         /* SCC errata A252,A308 workaround: Step4 */
 440         if ((in_be32((void __iomem *)IDE_ALTSTATUS_REG) & ERR_STAT) &&
 441             (int_stat & INTSTS_INTRQ))
 442                 return 1;
 443
 444         /* SCC errata A308 workaround: Step5 (polling IOIRQS) */
 445         if (int_stat & INTSTS_IOIRQS)
 446                 return 1;
 447
 448         if (!drive->waiting_for_dma)
 449                 printk(KERN_WARNING "%s: (%s) called while not waiting\n",
 450                         drive->name, __FUNCTION__);
 451         return 0;
 452 }
 453
 454 static u8 scc_udma_filter(ide_drive_t *drive)
 455 {
 456         ide_hwif_t *hwif = drive->hwif;
 457         u8 mask = hwif->ultra_mask;
 458
 459         /* errata A308 workaround: limit non ide_disk drive to UDMA4 */
 460         if ((drive->media != ide_disk) && (mask & 0xE0)) {
 461                 printk(KERN_INFO "%s: limit %s to UDMA4\n",
 462                        SCC_PATA_NAME, drive->name);
 463                 mask = ATA_UDMA4;
 464         }
 465
 466         return mask;
 467 }
 468
 469 /**
 470  *      setup_mmio_scc  -       map CTRL/BMID region
 471  *      @dev: PCI device we are configuring
 472  *      @name: device name
 473  *
 474  */
 475
 476 static int setup_mmio_scc (struct pci_dev *dev, const char *name)
 477 {
 478         unsigned long ctl_base = pci_resource_start(dev, 0);
 479         unsigned long dma_base = pci_resource_start(dev, 1);
 480         unsigned long ctl_size = pci_resource_len(dev, 0);
 481         unsigned long dma_size = pci_resource_len(dev, 1);
 482         void __iomem *ctl_addr;
 483         void __iomem *dma_addr;
 484         int i;
 485
 486         for (i = 0; i < MAX_HWIFS; i++) {
 487                 if (scc_ports[i].ctl == 0)
 488                         break;
 489         }
 490         if (i >= MAX_HWIFS)
 491                 return -ENOMEM;
 492
 493         if (!request_mem_region(ctl_base, ctl_size, name)) {
 494                 printk(KERN_WARNING "%s: IDE controller MMIO ports not available.\n", SCC_PATA_NAME);
 495                 goto fail_0;
 496         }
 497
 498         if (!request_mem_region(dma_base, dma_size, name)) {
 499                 printk(KERN_WARNING "%s: IDE controller MMIO ports not available.\n", SCC_PATA_NAME);
 500                 goto fail_1;
 501         }
 502
 503         if ((ctl_addr = ioremap(ctl_base, ctl_size)) == NULL)
 504                 goto fail_2;
 505
 506         if ((dma_addr = ioremap(dma_base, dma_size)) == NULL)
 507                 goto fail_3;
 508
 509         pci_set_master(dev);
 510         scc_ports[i].ctl = (unsigned long)ctl_addr;
 511         scc_ports[i].dma = (unsigned long)dma_addr;
 512         pci_set_drvdata(dev, (void *) &scc_ports[i]);
 513
 514         return 1;
 515
 516  fail_3:
 517         iounmap(ctl_addr);
 518  fail_2:
 519         release_mem_region(dma_base, dma_size);
 520  fail_1:
 521         release_mem_region(ctl_base, ctl_size);
 522  fail_0:
 523         return -ENOMEM;
 524 }
 525
 526 static int scc_ide_setup_pci_device(struct pci_dev *dev,
 527                                     const struct ide_port_info *d)
 528 {
 529         struct scc_ports *ports = pci_get_drvdata(dev);
 530         ide_hwif_t *hwif = NULL;
 531         hw_regs_t hw;
 532         u8 idx[4] = { 0xff, 0xff, 0xff, 0xff };
 533         int i;
 534
 535         for (i = 0; i < MAX_HWIFS; i++) {
 536                 hwif = &ide_hwifs[i];
 537                 if (hwif->chipset == ide_unknown)
 538                         break; /* pick an unused entry */
 539         }
 540         if (i == MAX_HWIFS) {
 541                 printk(KERN_ERR "%s: too many IDE interfaces, "
 542                                 "no room in table\n", SCC_PATA_NAME);
 543                 return -ENOMEM;
 544         }
 545
 546         memset(&hw, 0, sizeof(hw));
 547         for (i = IDE_DATA_OFFSET; i <= IDE_CONTROL_OFFSET; i++)
 548                 hw.io_ports[i] = ports->dma + 0x20 + i * 4;
 549         hw.irq = dev->irq;
 550         hw.dev = &dev->dev;
 551         hw.chipset = ide_pci;
 552         ide_init_port_hw(hwif, &hw);
 553         hwif->dev = &dev->dev;
 554         hwif->cds = d;
 555
 556         idx[0] = hwif->index;
 557
 558         ide_device_add(idx, d);
 559
 560         return 0;
 561 }
 562
 563 /**
 564  *      init_setup_scc  -       set up an SCC PATA Controller
 565  *      @dev: PCI device
 566  *      @d: IDE port info
 567  *
 568  *      Perform the initial set up for this device.
 569  */
 570
 571 static int __devinit init_setup_scc(struct pci_dev *dev,
 572                                     const struct ide_port_info *d)
 573 {
 574         unsigned long ctl_base;
 575         unsigned long dma_base;
 576         unsigned long cckctrl_port;
 577         unsigned long intmask_port;
 578         unsigned long mode_port;
 579         unsigned long ecmode_port;
 580         unsigned long dma_status_port;
 581         u32 reg = 0;
 582         struct scc_ports *ports;
 583         int rc;
 584
 585         rc = pci_enable_device(dev);
 586         if (rc)
 587                 goto end;
 588
 589         rc = setup_mmio_scc(dev, d->name);
 590         if (rc < 0)
 591                 goto end;
 592
 593         ports = pci_get_drvdata(dev);
 594         ctl_base = ports->ctl;
 595         dma_base = ports->dma;
 596         cckctrl_port = ctl_base + 0xff0;
 597         intmask_port = dma_base + 0x010;
 598         mode_port = ctl_base + 0x024;
 599         ecmode_port = ctl_base + 0xf00;
 600         dma_status_port = dma_base + 0x004;
 601
 602         /* controller initialization */
 603         reg = 0;
 604         out_be32((void*)cckctrl_port, reg);
 605         reg |= CCKCTRL_ATACLKOEN;
 606         out_be32((void*)cckctrl_port, reg);
 607         reg |= CCKCTRL_LCLKEN | CCKCTRL_OCLKEN;
 608         out_be32((void*)cckctrl_port, reg);
 609         reg |= CCKCTRL_CRST;
 610         out_be32((void*)cckctrl_port, reg);
 611
 612         for (;;) {
 613                 reg = in_be32((void*)cckctrl_port);
 614                 if (reg & CCKCTRL_CRST)
 615                         break;
 616                 udelay(5000);
 617         }
 618
 619         reg |= CCKCTRL_ATARESET;
 620         out_be32((void*)cckctrl_port, reg);
 621
 622         out_be32((void*)ecmode_port, ECMODE_VALUE);
 623         out_be32((void*)mode_port, MODE_JCUSFEN);
 624         out_be32((void*)intmask_port, INTMASK_MSK);
 625
 626         rc = scc_ide_setup_pci_device(dev, d);
 627
 628  end:
 629         return rc;
 630 }
 631
 632 /**
 633  *      init_mmio_iops_scc      -       set up the iops for MMIO
 634  *      @hwif: interface to set up
 635  *
 636  */
 637
 638 static void __devinit init_mmio_iops_scc(ide_hwif_t *hwif)
 639 {
 640         struct pci_dev *dev = to_pci_dev(hwif->dev);
 641         struct scc_ports *ports = pci_get_drvdata(dev);
 642         unsigned long dma_base = ports->dma;
 643
 644         ide_set_hwifdata(hwif, ports);
 645
 646         hwif->INB = scc_ide_inb;
 647         hwif->INW = scc_ide_inw;
 648         hwif->INSW = scc_ide_insw;
 649         hwif->INSL = scc_ide_insl;
 650         hwif->OUTB = scc_ide_outb;
 651         hwif->OUTBSYNC = scc_ide_outbsync;
 652         hwif->OUTW = scc_ide_outw;
 653         hwif->OUTSW = scc_ide_outsw;
 654         hwif->OUTSL = scc_ide_outsl;
 655
 656         hwif->dma_base = dma_base;
 657         hwif->config_data = ports->ctl;
 658         hwif->mmio = 1;
 659 }
 660
 661 /**
 662  *      init_iops_scc   -       set up iops
 663  *      @hwif: interface to set up
 664  *
 665  *      Do the basic setup for the SCC hardware interface
 666  *      and then do the MMIO setup.
 667  */
 668
 669 static void __devinit init_iops_scc(ide_hwif_t *hwif)
 670 {
 671         struct pci_dev *dev = to_pci_dev(hwif->dev);
 672
 673         hwif->hwif_data = NULL;
 674         if (pci_get_drvdata(dev) == NULL)
 675                 return;
 676         init_mmio_iops_scc(hwif);
 677 }
 678
 679 static u8 __devinit scc_cable_detect(ide_hwif_t *hwif)
 680 {
 681         return ATA_CBL_PATA80;
 682 }
 683
 684 /**
 685  *      init_hwif_scc   -       set up hwif
 686  *      @hwif: interface to set up
 687  *
 688  *      We do the basic set up of the interface structure. The SCC
 689  *      requires several custom handlers so we override the default
 690  *      ide DMA handlers appropriately.
 691  */
 692
 693 static void __devinit init_hwif_scc(ide_hwif_t *hwif)
 694 {
 695         struct scc_ports *ports = ide_get_hwifdata(hwif);
 696
 697         ports->hwif_id = hwif->index;
 698
 699         hwif->dma_command = hwif->dma_base;
 700         hwif->dma_status = hwif->dma_base + 0x04;
 701         hwif->dma_prdtable = hwif->dma_base + 0x08;
 702
 703         /* PTERADD */
 704         out_be32((void __iomem *)(hwif->dma_base + 0x018), hwif->dmatable_dma);
 705
 706         hwif->dma_setup = scc_dma_setup;
 707         hwif->ide_dma_end = scc_ide_dma_end;
 708         hwif->set_pio_mode = scc_set_pio_mode;
 709         hwif->set_dma_mode = scc_set_dma_mode;
 710         hwif->ide_dma_test_irq = scc_dma_test_irq;
 711         hwif->udma_filter = scc_udma_filter;
 712
 713         if (in_be32((void __iomem *)(hwif->config_data + 0xff0)) & CCKCTRL_ATACLKOEN)
 714                 hwif->ultra_mask = ATA_UDMA6; /* 133MHz */
 715         else
 716                 hwif->ultra_mask = ATA_UDMA5; /* 100MHz */
 717
 718         hwif->cable_detect = scc_cable_detect;
 719 }
 720
 721 #define DECLARE_SCC_DEV(name_str)                       \
 722   {                                                     \
 723       .name             = name_str,                     \
 724       .init_iops        = init_iops_scc,                \
 725       .init_hwif        = init_hwif_scc,                \
 726       .host_flags       = IDE_HFLAG_SINGLE |            \
 727                           IDE_HFLAG_BOOTABLE,           \
 728       .pio_mask         = ATA_PIO4,                     \
 729   }
 730
 731 static const struct ide_port_info scc_chipsets[] __devinitdata = {
 732         /* 0 */ DECLARE_SCC_DEV("sccIDE"),
 733 };
 734
 735 /**
 736  *      scc_init_one    -       pci layer discovery entry
 737  *      @dev: PCI device
 738  *      @id: ident table entry
 739  *
 740  *      Called by the PCI code when it finds an SCC PATA controller.
 741  *      We then use the IDE PCI generic helper to do most of the work.
 742  */
 743
 744 static int __devinit scc_init_one(struct pci_dev *dev, const struct pci_device_id *id)
 745 {
 746         return init_setup_scc(dev, &scc_chipsets[id->driver_data]);
 747 }
 748
 749 /**
 750  *      scc_remove      -       pci layer remove entry
 751  *      @dev: PCI device
 752  *
 753  *      Called by the PCI code when it removes an SCC PATA controller.
 754  */
 755
 756 static void __devexit scc_remove(struct pci_dev *dev)
 757 {
 758         struct scc_ports *ports = pci_get_drvdata(dev);
 759         ide_hwif_t *hwif = &ide_hwifs[ports->hwif_id];
 760         unsigned long ctl_base = pci_resource_start(dev, 0);
 761         unsigned long dma_base = pci_resource_start(dev, 1);
 762         unsigned long ctl_size = pci_resource_len(dev, 0);
 763         unsigned long dma_size = pci_resource_len(dev, 1);
 764
 765         if (hwif->dmatable_cpu) {
 766                 pci_free_consistent(dev, PRD_ENTRIES * PRD_BYTES,
 767                                     hwif->dmatable_cpu, hwif->dmatable_dma);
 768                 hwif->dmatable_cpu = NULL;
 769         }
 770
 771         ide_unregister(hwif->index);
 772
 773         hwif->chipset = ide_unknown;
 774         iounmap((void*)ports->dma);
 775         iounmap((void*)ports->ctl);
 776         release_mem_region(dma_base, dma_size);
 777         release_mem_region(ctl_base, ctl_size);
 778         memset(ports, 0, sizeof(*ports));
 779 }
 780
 781 static const struct pci_device_id scc_pci_tbl[] = {
 782         { PCI_VDEVICE(TOSHIBA_2, PCI_DEVICE_ID_TOSHIBA_SCC_ATA), 0 },
 783         { 0, },
 784 };
 785 MODULE_DEVICE_TABLE(pci, scc_pci_tbl);
 786
 787 static struct pci_driver driver = {
 788         .name = "SCC IDE",
 789         .id_table = scc_pci_tbl,
 790         .probe = scc_init_one,
 791         .remove = scc_remove,
 792 };
 793
 794 static int scc_ide_init(void)
 795 {
 796         return ide_pci_register_driver(&driver);
 797 }
 798
 799 module_init(scc_ide_init);
 800 /* -- No exit code?
 801 static void scc_ide_exit(void)
 802 {
 803         ide_pci_unregister_driver(&driver);
 804 }
 805 module_exit(scc_ide_exit);
 806  */
 807
 808
 809 MODULE_DESCRIPTION("PCI driver module for Toshiba SCC IDE");
 810 MODULE_LICENSE("GPL");