2 * Support for IDE interfaces on Celleb platform
4 * (C) Copyright 2006 TOSHIBA CORPORATION
6 * This code is based on drivers/ide/pci/siimage.c:
7 * Copyright (C) 2001-2002 Andre Hedrick <andre@linux-ide.org>
8 * Copyright (C) 2003 Red Hat <alan@redhat.com>
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License along
21 * with this program; if not, write to the Free Software Foundation, Inc.,
22 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
25 #include <linux/types.h>
26 #include <linux/module.h>
27 #include <linux/pci.h>
28 #include <linux/delay.h>
29 #include <linux/hdreg.h>
30 #include <linux/ide.h>
31 #include <linux/init.h>
33 #define PCI_DEVICE_ID_TOSHIBA_SCC_ATA 0x01b4
35 #define SCC_PATA_NAME "scc IDE"
37 #define TDVHSEL_MASTER 0x00000001
38 #define TDVHSEL_SLAVE 0x00000004
40 #define MODE_JCUSFEN 0x00000080
42 #define CCKCTRL_ATARESET 0x00040000
43 #define CCKCTRL_BUFCNT 0x00020000
44 #define CCKCTRL_CRST 0x00010000
45 #define CCKCTRL_OCLKEN 0x00000100
46 #define CCKCTRL_ATACLKOEN 0x00000002
47 #define CCKCTRL_LCLKEN 0x00000001
49 #define QCHCD_IOS_SS 0x00000001
51 #define QCHSD_STPDIAG 0x00020000
53 #define INTMASK_MSK 0xD1000012
54 #define INTSTS_SERROR 0x80000000
55 #define INTSTS_PRERR 0x40000000
56 #define INTSTS_RERR 0x10000000
57 #define INTSTS_ICERR 0x01000000
58 #define INTSTS_BMSINT 0x00000010
59 #define INTSTS_BMHE 0x00000008
60 #define INTSTS_IOIRQS 0x00000004
61 #define INTSTS_INTRQ 0x00000002
62 #define INTSTS_ACTEINT 0x00000001
64 #define ECMODE_VALUE 0x01
66 static struct scc_ports
{
67 unsigned long ctl
, dma
;
68 ide_hwif_t
*hwif
; /* for removing port from system */
69 } scc_ports
[MAX_HWIFS
];
71 /* PIO transfer mode table */
73 static unsigned long JCHSTtbl
[2][7] = {
74 {0x0E, 0x05, 0x02, 0x03, 0x02, 0x00, 0x00}, /* 100MHz */
75 {0x13, 0x07, 0x04, 0x04, 0x03, 0x00, 0x00} /* 133MHz */
79 static unsigned long JCHHTtbl
[2][7] = {
80 {0x0E, 0x02, 0x02, 0x02, 0x02, 0x00, 0x00}, /* 100MHz */
81 {0x13, 0x03, 0x03, 0x03, 0x03, 0x00, 0x00} /* 133MHz */
85 static unsigned long JCHCTtbl
[2][7] = {
86 {0x1D, 0x1D, 0x1C, 0x0B, 0x06, 0x00, 0x00}, /* 100MHz */
87 {0x27, 0x26, 0x26, 0x0E, 0x09, 0x00, 0x00} /* 133MHz */
91 /* DMA transfer mode table */
93 static unsigned long JCHDCTxtbl
[2][7] = {
94 {0x0A, 0x06, 0x04, 0x03, 0x01, 0x00, 0x00}, /* 100MHz */
95 {0x0E, 0x09, 0x06, 0x04, 0x02, 0x01, 0x00} /* 133MHz */
99 static unsigned long JCSTWTxtbl
[2][7] = {
100 {0x06, 0x04, 0x03, 0x02, 0x02, 0x02, 0x00}, /* 100MHz */
101 {0x09, 0x06, 0x04, 0x02, 0x02, 0x02, 0x02} /* 133MHz */
105 static unsigned long JCTSStbl
[2][7] = {
106 {0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x00}, /* 100MHz */
107 {0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05} /* 133MHz */
111 static unsigned long JCENVTtbl
[2][7] = {
112 {0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x00}, /* 100MHz */
113 {0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02} /* 133MHz */
116 /* JCACTSELS/JCACTSELM */
117 static unsigned long JCACTSELtbl
[2][7] = {
118 {0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00}, /* 100MHz */
119 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01} /* 133MHz */
123 static u8
scc_ide_inb(unsigned long port
)
125 u32 data
= in_be32((void*)port
);
129 static void scc_ide_insw(unsigned long port
, void *addr
, u32 count
)
131 u16
*ptr
= (u16
*)addr
;
133 *ptr
++ = le16_to_cpu(in_be32((void*)port
));
137 static void scc_ide_insl(unsigned long port
, void *addr
, u32 count
)
139 u16
*ptr
= (u16
*)addr
;
141 *ptr
++ = le16_to_cpu(in_be32((void*)port
));
142 *ptr
++ = le16_to_cpu(in_be32((void*)port
));
146 static void scc_ide_outb(u8 addr
, unsigned long port
)
148 out_be32((void*)port
, addr
);
152 scc_ide_outbsync(ide_drive_t
* drive
, u8 addr
, unsigned long port
)
154 ide_hwif_t
*hwif
= HWIF(drive
);
156 out_be32((void*)port
, addr
);
158 in_be32((void*)(hwif
->dma_base
+ 0x01c));
163 scc_ide_outsw(unsigned long port
, void *addr
, u32 count
)
165 u16
*ptr
= (u16
*)addr
;
167 out_be32((void*)port
, cpu_to_le16(*ptr
++));
172 scc_ide_outsl(unsigned long port
, void *addr
, u32 count
)
174 u16
*ptr
= (u16
*)addr
;
176 out_be32((void*)port
, cpu_to_le16(*ptr
++));
177 out_be32((void*)port
, cpu_to_le16(*ptr
++));
182 * scc_set_pio_mode - set host controller for PIO mode
184 * @pio: PIO mode number
186 * Load the timing settings for this device mode into the
190 static void scc_set_pio_mode(ide_drive_t
*drive
, const u8 pio
)
192 ide_hwif_t
*hwif
= HWIF(drive
);
193 struct scc_ports
*ports
= ide_get_hwifdata(hwif
);
194 unsigned long ctl_base
= ports
->ctl
;
195 unsigned long cckctrl_port
= ctl_base
+ 0xff0;
196 unsigned long piosht_port
= ctl_base
+ 0x000;
197 unsigned long pioct_port
= ctl_base
+ 0x004;
201 reg
= in_be32((void __iomem
*)cckctrl_port
);
202 if (reg
& CCKCTRL_ATACLKOEN
) {
203 offset
= 1; /* 133MHz */
205 offset
= 0; /* 100MHz */
207 reg
= JCHSTtbl
[offset
][pio
] << 16 | JCHHTtbl
[offset
][pio
];
208 out_be32((void __iomem
*)piosht_port
, reg
);
209 reg
= JCHCTtbl
[offset
][pio
];
210 out_be32((void __iomem
*)pioct_port
, reg
);
214 * scc_set_dma_mode - set host controller for DMA mode
218 * Load the timing settings for this device mode into the
222 static void scc_set_dma_mode(ide_drive_t
*drive
, const u8 speed
)
224 ide_hwif_t
*hwif
= HWIF(drive
);
225 struct scc_ports
*ports
= ide_get_hwifdata(hwif
);
226 unsigned long ctl_base
= ports
->ctl
;
227 unsigned long cckctrl_port
= ctl_base
+ 0xff0;
228 unsigned long mdmact_port
= ctl_base
+ 0x008;
229 unsigned long mcrcst_port
= ctl_base
+ 0x00c;
230 unsigned long sdmact_port
= ctl_base
+ 0x010;
231 unsigned long scrcst_port
= ctl_base
+ 0x014;
232 unsigned long udenvt_port
= ctl_base
+ 0x018;
233 unsigned long tdvhsel_port
= ctl_base
+ 0x020;
234 int is_slave
= (&hwif
->drives
[1] == drive
);
237 unsigned long jcactsel
;
239 reg
= in_be32((void __iomem
*)cckctrl_port
);
240 if (reg
& CCKCTRL_ATACLKOEN
) {
241 offset
= 1; /* 133MHz */
243 offset
= 0; /* 100MHz */
246 idx
= speed
- XFER_UDMA_0
;
248 jcactsel
= JCACTSELtbl
[offset
][idx
];
250 out_be32((void __iomem
*)sdmact_port
, JCHDCTxtbl
[offset
][idx
]);
251 out_be32((void __iomem
*)scrcst_port
, JCSTWTxtbl
[offset
][idx
]);
252 jcactsel
= jcactsel
<< 2;
253 out_be32((void __iomem
*)tdvhsel_port
, (in_be32((void __iomem
*)tdvhsel_port
) & ~TDVHSEL_SLAVE
) | jcactsel
);
255 out_be32((void __iomem
*)mdmact_port
, JCHDCTxtbl
[offset
][idx
]);
256 out_be32((void __iomem
*)mcrcst_port
, JCSTWTxtbl
[offset
][idx
]);
257 out_be32((void __iomem
*)tdvhsel_port
, (in_be32((void __iomem
*)tdvhsel_port
) & ~TDVHSEL_MASTER
) | jcactsel
);
259 reg
= JCTSStbl
[offset
][idx
] << 16 | JCENVTtbl
[offset
][idx
];
260 out_be32((void __iomem
*)udenvt_port
, reg
);
263 static void scc_dma_host_set(ide_drive_t
*drive
, int on
)
265 ide_hwif_t
*hwif
= drive
->hwif
;
266 u8 unit
= (drive
->select
.b
.unit
& 0x01);
267 u8 dma_stat
= scc_ide_inb(hwif
->dma_status
);
270 dma_stat
|= (1 << (5 + unit
));
272 dma_stat
&= ~(1 << (5 + unit
));
274 scc_ide_outb(dma_stat
, hwif
->dma_status
);
278 * scc_ide_dma_setup - begin a DMA phase
279 * @drive: target device
281 * Build an IDE DMA PRD (IDE speak for scatter gather table)
282 * and then set up the DMA transfer registers.
284 * Returns 0 on success. If a PIO fallback is required then 1
288 static int scc_dma_setup(ide_drive_t
*drive
)
290 ide_hwif_t
*hwif
= drive
->hwif
;
291 struct request
*rq
= HWGROUP(drive
)->rq
;
292 unsigned int reading
;
300 /* fall back to pio! */
301 if (!ide_build_dmatable(drive
, rq
)) {
302 ide_map_sg(drive
, rq
);
307 out_be32((void __iomem
*)hwif
->dma_prdtable
, hwif
->dmatable_dma
);
310 out_be32((void __iomem
*)hwif
->dma_command
, reading
);
312 /* read dma_status for INTR & ERROR flags */
313 dma_stat
= in_be32((void __iomem
*)hwif
->dma_status
);
315 /* clear INTR & ERROR flags */
316 out_be32((void __iomem
*)hwif
->dma_status
, dma_stat
|6);
317 drive
->waiting_for_dma
= 1;
321 static void scc_dma_start(ide_drive_t
*drive
)
323 ide_hwif_t
*hwif
= drive
->hwif
;
324 u8 dma_cmd
= scc_ide_inb(hwif
->dma_command
);
327 scc_ide_outb(dma_cmd
| 1, hwif
->dma_command
);
332 static int __scc_dma_end(ide_drive_t
*drive
)
334 ide_hwif_t
*hwif
= drive
->hwif
;
335 u8 dma_stat
, dma_cmd
;
337 drive
->waiting_for_dma
= 0;
338 /* get DMA command mode */
339 dma_cmd
= scc_ide_inb(hwif
->dma_command
);
341 scc_ide_outb(dma_cmd
& ~1, hwif
->dma_command
);
343 dma_stat
= scc_ide_inb(hwif
->dma_status
);
344 /* clear the INTR & ERROR bits */
345 scc_ide_outb(dma_stat
| 6, hwif
->dma_status
);
346 /* purge DMA mappings */
347 ide_destroy_dmatable(drive
);
348 /* verify good DMA status */
351 return (dma_stat
& 7) != 4 ? (0x10 | dma_stat
) : 0;
355 * scc_dma_end - Stop DMA
358 * Check and clear INT Status register.
359 * Then call __scc_dma_end().
362 static int scc_dma_end(ide_drive_t
*drive
)
364 ide_hwif_t
*hwif
= HWIF(drive
);
365 unsigned long intsts_port
= hwif
->dma_base
+ 0x014;
367 int dma_stat
, data_loss
= 0;
368 static int retry
= 0;
370 /* errata A308 workaround: Step5 (check data loss) */
371 /* We don't check non ide_disk because it is limited to UDMA4 */
372 if (!(in_be32((void __iomem
*)hwif
->io_ports
.ctl_addr
)
374 drive
->media
== ide_disk
&& drive
->current_speed
> XFER_UDMA_4
) {
375 reg
= in_be32((void __iomem
*)intsts_port
);
376 if (!(reg
& INTSTS_ACTEINT
)) {
377 printk(KERN_WARNING
"%s: operation failed (transfer data loss)\n",
381 struct request
*rq
= HWGROUP(drive
)->rq
;
383 /* ERROR_RESET and drive->crc_count are needed
384 * to reduce DMA transfer mode in retry process.
387 rq
->errors
|= ERROR_RESET
;
388 for (unit
= 0; unit
< MAX_DRIVES
; unit
++) {
389 ide_drive_t
*drive
= &hwif
->drives
[unit
];
397 reg
= in_be32((void __iomem
*)intsts_port
);
399 if (reg
& INTSTS_SERROR
) {
400 printk(KERN_WARNING
"%s: SERROR\n", SCC_PATA_NAME
);
401 out_be32((void __iomem
*)intsts_port
, INTSTS_SERROR
|INTSTS_BMSINT
);
403 out_be32((void __iomem
*)hwif
->dma_command
, in_be32((void __iomem
*)hwif
->dma_command
) & ~QCHCD_IOS_SS
);
407 if (reg
& INTSTS_PRERR
) {
409 unsigned long ctl_base
= hwif
->config_data
;
411 maea0
= in_be32((void __iomem
*)(ctl_base
+ 0xF50));
412 maec0
= in_be32((void __iomem
*)(ctl_base
+ 0xF54));
414 printk(KERN_WARNING
"%s: PRERR [addr:%x cmd:%x]\n", SCC_PATA_NAME
, maea0
, maec0
);
416 out_be32((void __iomem
*)intsts_port
, INTSTS_PRERR
|INTSTS_BMSINT
);
418 out_be32((void __iomem
*)hwif
->dma_command
, in_be32((void __iomem
*)hwif
->dma_command
) & ~QCHCD_IOS_SS
);
422 if (reg
& INTSTS_RERR
) {
423 printk(KERN_WARNING
"%s: Response Error\n", SCC_PATA_NAME
);
424 out_be32((void __iomem
*)intsts_port
, INTSTS_RERR
|INTSTS_BMSINT
);
426 out_be32((void __iomem
*)hwif
->dma_command
, in_be32((void __iomem
*)hwif
->dma_command
) & ~QCHCD_IOS_SS
);
430 if (reg
& INTSTS_ICERR
) {
431 out_be32((void __iomem
*)hwif
->dma_command
, in_be32((void __iomem
*)hwif
->dma_command
) & ~QCHCD_IOS_SS
);
433 printk(KERN_WARNING
"%s: Illegal Configuration\n", SCC_PATA_NAME
);
434 out_be32((void __iomem
*)intsts_port
, INTSTS_ICERR
|INTSTS_BMSINT
);
438 if (reg
& INTSTS_BMSINT
) {
439 printk(KERN_WARNING
"%s: Internal Bus Error\n", SCC_PATA_NAME
);
440 out_be32((void __iomem
*)intsts_port
, INTSTS_BMSINT
);
446 if (reg
& INTSTS_BMHE
) {
447 out_be32((void __iomem
*)intsts_port
, INTSTS_BMHE
);
451 if (reg
& INTSTS_ACTEINT
) {
452 out_be32((void __iomem
*)intsts_port
, INTSTS_ACTEINT
);
456 if (reg
& INTSTS_IOIRQS
) {
457 out_be32((void __iomem
*)intsts_port
, INTSTS_IOIRQS
);
463 dma_stat
= __scc_dma_end(drive
);
465 dma_stat
|= 2; /* emulate DMA error (to retry command) */
469 /* returns 1 if dma irq issued, 0 otherwise */
470 static int scc_dma_test_irq(ide_drive_t
*drive
)
472 ide_hwif_t
*hwif
= HWIF(drive
);
473 u32 int_stat
= in_be32((void __iomem
*)hwif
->dma_base
+ 0x014);
475 /* SCC errata A252,A308 workaround: Step4 */
476 if ((in_be32((void __iomem
*)hwif
->io_ports
.ctl_addr
)
478 (int_stat
& INTSTS_INTRQ
))
481 /* SCC errata A308 workaround: Step5 (polling IOIRQS) */
482 if (int_stat
& INTSTS_IOIRQS
)
485 if (!drive
->waiting_for_dma
)
486 printk(KERN_WARNING
"%s: (%s) called while not waiting\n",
487 drive
->name
, __func__
);
491 static u8
scc_udma_filter(ide_drive_t
*drive
)
493 ide_hwif_t
*hwif
= drive
->hwif
;
494 u8 mask
= hwif
->ultra_mask
;
496 /* errata A308 workaround: limit non ide_disk drive to UDMA4 */
497 if ((drive
->media
!= ide_disk
) && (mask
& 0xE0)) {
498 printk(KERN_INFO
"%s: limit %s to UDMA4\n",
499 SCC_PATA_NAME
, drive
->name
);
507 * setup_mmio_scc - map CTRL/BMID region
508 * @dev: PCI device we are configuring
513 static int setup_mmio_scc (struct pci_dev
*dev
, const char *name
)
515 unsigned long ctl_base
= pci_resource_start(dev
, 0);
516 unsigned long dma_base
= pci_resource_start(dev
, 1);
517 unsigned long ctl_size
= pci_resource_len(dev
, 0);
518 unsigned long dma_size
= pci_resource_len(dev
, 1);
519 void __iomem
*ctl_addr
;
520 void __iomem
*dma_addr
;
523 for (i
= 0; i
< MAX_HWIFS
; i
++) {
524 if (scc_ports
[i
].ctl
== 0)
530 ret
= pci_request_selected_regions(dev
, (1 << 2) - 1, name
);
532 printk(KERN_ERR
"%s: can't reserve resources\n", name
);
536 if ((ctl_addr
= ioremap(ctl_base
, ctl_size
)) == NULL
)
539 if ((dma_addr
= ioremap(dma_base
, dma_size
)) == NULL
)
543 scc_ports
[i
].ctl
= (unsigned long)ctl_addr
;
544 scc_ports
[i
].dma
= (unsigned long)dma_addr
;
545 pci_set_drvdata(dev
, (void *) &scc_ports
[i
]);
555 static int scc_ide_setup_pci_device(struct pci_dev
*dev
,
556 const struct ide_port_info
*d
)
558 struct scc_ports
*ports
= pci_get_drvdata(dev
);
559 ide_hwif_t
*hwif
= NULL
;
561 u8 idx
[4] = { 0xff, 0xff, 0xff, 0xff };
564 hwif
= ide_find_port();
566 printk(KERN_ERR
"%s: too many IDE interfaces, "
567 "no room in table\n", SCC_PATA_NAME
);
571 memset(&hw
, 0, sizeof(hw
));
572 for (i
= 0; i
<= 8; i
++)
573 hw
.io_ports_array
[i
] = ports
->dma
+ 0x20 + i
* 4;
576 hw
.chipset
= ide_pci
;
577 ide_init_port_hw(hwif
, &hw
);
578 hwif
->dev
= &dev
->dev
;
580 idx
[0] = hwif
->index
;
582 ide_device_add(idx
, d
);
588 * init_setup_scc - set up an SCC PATA Controller
592 * Perform the initial set up for this device.
595 static int __devinit
init_setup_scc(struct pci_dev
*dev
,
596 const struct ide_port_info
*d
)
598 unsigned long ctl_base
;
599 unsigned long dma_base
;
600 unsigned long cckctrl_port
;
601 unsigned long intmask_port
;
602 unsigned long mode_port
;
603 unsigned long ecmode_port
;
604 unsigned long dma_status_port
;
606 struct scc_ports
*ports
;
609 rc
= pci_enable_device(dev
);
613 rc
= setup_mmio_scc(dev
, d
->name
);
617 ports
= pci_get_drvdata(dev
);
618 ctl_base
= ports
->ctl
;
619 dma_base
= ports
->dma
;
620 cckctrl_port
= ctl_base
+ 0xff0;
621 intmask_port
= dma_base
+ 0x010;
622 mode_port
= ctl_base
+ 0x024;
623 ecmode_port
= ctl_base
+ 0xf00;
624 dma_status_port
= dma_base
+ 0x004;
626 /* controller initialization */
628 out_be32((void*)cckctrl_port
, reg
);
629 reg
|= CCKCTRL_ATACLKOEN
;
630 out_be32((void*)cckctrl_port
, reg
);
631 reg
|= CCKCTRL_LCLKEN
| CCKCTRL_OCLKEN
;
632 out_be32((void*)cckctrl_port
, reg
);
634 out_be32((void*)cckctrl_port
, reg
);
637 reg
= in_be32((void*)cckctrl_port
);
638 if (reg
& CCKCTRL_CRST
)
643 reg
|= CCKCTRL_ATARESET
;
644 out_be32((void*)cckctrl_port
, reg
);
646 out_be32((void*)ecmode_port
, ECMODE_VALUE
);
647 out_be32((void*)mode_port
, MODE_JCUSFEN
);
648 out_be32((void*)intmask_port
, INTMASK_MSK
);
650 rc
= scc_ide_setup_pci_device(dev
, d
);
656 static void scc_tf_load(ide_drive_t
*drive
, ide_task_t
*task
)
658 struct ide_io_ports
*io_ports
= &drive
->hwif
->io_ports
;
659 struct ide_taskfile
*tf
= &task
->tf
;
660 u8 HIHI
= (task
->tf_flags
& IDE_TFLAG_LBA48
) ? 0xE0 : 0xEF;
662 if (task
->tf_flags
& IDE_TFLAG_FLAGGED
)
665 ide_set_irq(drive
, 1);
667 if (task
->tf_flags
& IDE_TFLAG_OUT_DATA
)
668 out_be32((void *)io_ports
->data_addr
,
669 (tf
->hob_data
<< 8) | tf
->data
);
671 if (task
->tf_flags
& IDE_TFLAG_OUT_HOB_FEATURE
)
672 scc_ide_outb(tf
->hob_feature
, io_ports
->feature_addr
);
673 if (task
->tf_flags
& IDE_TFLAG_OUT_HOB_NSECT
)
674 scc_ide_outb(tf
->hob_nsect
, io_ports
->nsect_addr
);
675 if (task
->tf_flags
& IDE_TFLAG_OUT_HOB_LBAL
)
676 scc_ide_outb(tf
->hob_lbal
, io_ports
->lbal_addr
);
677 if (task
->tf_flags
& IDE_TFLAG_OUT_HOB_LBAM
)
678 scc_ide_outb(tf
->hob_lbam
, io_ports
->lbam_addr
);
679 if (task
->tf_flags
& IDE_TFLAG_OUT_HOB_LBAH
)
680 scc_ide_outb(tf
->hob_lbah
, io_ports
->lbah_addr
);
682 if (task
->tf_flags
& IDE_TFLAG_OUT_FEATURE
)
683 scc_ide_outb(tf
->feature
, io_ports
->feature_addr
);
684 if (task
->tf_flags
& IDE_TFLAG_OUT_NSECT
)
685 scc_ide_outb(tf
->nsect
, io_ports
->nsect_addr
);
686 if (task
->tf_flags
& IDE_TFLAG_OUT_LBAL
)
687 scc_ide_outb(tf
->lbal
, io_ports
->lbal_addr
);
688 if (task
->tf_flags
& IDE_TFLAG_OUT_LBAM
)
689 scc_ide_outb(tf
->lbam
, io_ports
->lbam_addr
);
690 if (task
->tf_flags
& IDE_TFLAG_OUT_LBAH
)
691 scc_ide_outb(tf
->lbah
, io_ports
->lbah_addr
);
693 if (task
->tf_flags
& IDE_TFLAG_OUT_DEVICE
)
694 scc_ide_outb((tf
->device
& HIHI
) | drive
->select
.all
,
695 io_ports
->device_addr
);
698 static void scc_tf_read(ide_drive_t
*drive
, ide_task_t
*task
)
700 struct ide_io_ports
*io_ports
= &drive
->hwif
->io_ports
;
701 struct ide_taskfile
*tf
= &task
->tf
;
703 if (task
->tf_flags
& IDE_TFLAG_IN_DATA
) {
704 u16 data
= (u16
)in_be32((void *)io_ports
->data_addr
);
706 tf
->data
= data
& 0xff;
707 tf
->hob_data
= (data
>> 8) & 0xff;
710 /* be sure we're looking at the low order bits */
711 scc_ide_outb(drive
->ctl
& ~0x80, io_ports
->ctl_addr
);
713 if (task
->tf_flags
& IDE_TFLAG_IN_NSECT
)
714 tf
->nsect
= scc_ide_inb(io_ports
->nsect_addr
);
715 if (task
->tf_flags
& IDE_TFLAG_IN_LBAL
)
716 tf
->lbal
= scc_ide_inb(io_ports
->lbal_addr
);
717 if (task
->tf_flags
& IDE_TFLAG_IN_LBAM
)
718 tf
->lbam
= scc_ide_inb(io_ports
->lbam_addr
);
719 if (task
->tf_flags
& IDE_TFLAG_IN_LBAH
)
720 tf
->lbah
= scc_ide_inb(io_ports
->lbah_addr
);
721 if (task
->tf_flags
& IDE_TFLAG_IN_DEVICE
)
722 tf
->device
= scc_ide_inb(io_ports
->device_addr
);
724 if (task
->tf_flags
& IDE_TFLAG_LBA48
) {
725 scc_ide_outb(drive
->ctl
| 0x80, io_ports
->ctl_addr
);
727 if (task
->tf_flags
& IDE_TFLAG_IN_HOB_FEATURE
)
728 tf
->hob_feature
= scc_ide_inb(io_ports
->feature_addr
);
729 if (task
->tf_flags
& IDE_TFLAG_IN_HOB_NSECT
)
730 tf
->hob_nsect
= scc_ide_inb(io_ports
->nsect_addr
);
731 if (task
->tf_flags
& IDE_TFLAG_IN_HOB_LBAL
)
732 tf
->hob_lbal
= scc_ide_inb(io_ports
->lbal_addr
);
733 if (task
->tf_flags
& IDE_TFLAG_IN_HOB_LBAM
)
734 tf
->hob_lbam
= scc_ide_inb(io_ports
->lbam_addr
);
735 if (task
->tf_flags
& IDE_TFLAG_IN_HOB_LBAH
)
736 tf
->hob_lbah
= scc_ide_inb(io_ports
->lbah_addr
);
740 static void scc_input_data(ide_drive_t
*drive
, struct request
*rq
,
741 void *buf
, unsigned int len
)
743 unsigned long data_addr
= drive
->hwif
->io_ports
.data_addr
;
747 if (drive
->io_32bit
) {
748 scc_ide_insl(data_addr
, buf
, len
/ 4);
751 scc_ide_insw(data_addr
, (u8
*)buf
+ (len
& ~3), 1);
753 scc_ide_insw(data_addr
, buf
, len
/ 2);
756 static void scc_output_data(ide_drive_t
*drive
, struct request
*rq
,
757 void *buf
, unsigned int len
)
759 unsigned long data_addr
= drive
->hwif
->io_ports
.data_addr
;
763 if (drive
->io_32bit
) {
764 scc_ide_outsl(data_addr
, buf
, len
/ 4);
767 scc_ide_outsw(data_addr
, (u8
*)buf
+ (len
& ~3), 1);
769 scc_ide_outsw(data_addr
, buf
, len
/ 2);
773 * init_mmio_iops_scc - set up the iops for MMIO
774 * @hwif: interface to set up
778 static void __devinit
init_mmio_iops_scc(ide_hwif_t
*hwif
)
780 struct pci_dev
*dev
= to_pci_dev(hwif
->dev
);
781 struct scc_ports
*ports
= pci_get_drvdata(dev
);
782 unsigned long dma_base
= ports
->dma
;
784 ide_set_hwifdata(hwif
, ports
);
786 hwif
->tf_load
= scc_tf_load
;
787 hwif
->tf_read
= scc_tf_read
;
789 hwif
->input_data
= scc_input_data
;
790 hwif
->output_data
= scc_output_data
;
792 hwif
->INB
= scc_ide_inb
;
793 hwif
->OUTB
= scc_ide_outb
;
794 hwif
->OUTBSYNC
= scc_ide_outbsync
;
796 hwif
->dma_base
= dma_base
;
797 hwif
->config_data
= ports
->ctl
;
802 * init_iops_scc - set up iops
803 * @hwif: interface to set up
805 * Do the basic setup for the SCC hardware interface
806 * and then do the MMIO setup.
809 static void __devinit
init_iops_scc(ide_hwif_t
*hwif
)
811 struct pci_dev
*dev
= to_pci_dev(hwif
->dev
);
813 hwif
->hwif_data
= NULL
;
814 if (pci_get_drvdata(dev
) == NULL
)
816 init_mmio_iops_scc(hwif
);
819 static u8 __devinit
scc_cable_detect(ide_hwif_t
*hwif
)
821 return ATA_CBL_PATA80
;
825 * init_hwif_scc - set up hwif
826 * @hwif: interface to set up
828 * We do the basic set up of the interface structure. The SCC
829 * requires several custom handlers so we override the default
830 * ide DMA handlers appropriately.
833 static void __devinit
init_hwif_scc(ide_hwif_t
*hwif
)
835 struct scc_ports
*ports
= ide_get_hwifdata(hwif
);
839 hwif
->dma_command
= hwif
->dma_base
;
840 hwif
->dma_status
= hwif
->dma_base
+ 0x04;
841 hwif
->dma_prdtable
= hwif
->dma_base
+ 0x08;
844 out_be32((void __iomem
*)(hwif
->dma_base
+ 0x018), hwif
->dmatable_dma
);
846 if (in_be32((void __iomem
*)(hwif
->config_data
+ 0xff0)) & CCKCTRL_ATACLKOEN
)
847 hwif
->ultra_mask
= ATA_UDMA6
; /* 133MHz */
849 hwif
->ultra_mask
= ATA_UDMA5
; /* 100MHz */
852 static const struct ide_port_ops scc_port_ops
= {
853 .set_pio_mode
= scc_set_pio_mode
,
854 .set_dma_mode
= scc_set_dma_mode
,
855 .udma_filter
= scc_udma_filter
,
856 .cable_detect
= scc_cable_detect
,
859 static const struct ide_dma_ops scc_dma_ops
= {
860 .dma_host_set
= scc_dma_host_set
,
861 .dma_setup
= scc_dma_setup
,
862 .dma_exec_cmd
= ide_dma_exec_cmd
,
863 .dma_start
= scc_dma_start
,
864 .dma_end
= scc_dma_end
,
865 .dma_test_irq
= scc_dma_test_irq
,
866 .dma_lost_irq
= ide_dma_lost_irq
,
867 .dma_timeout
= ide_dma_timeout
,
870 #define DECLARE_SCC_DEV(name_str) \
873 .init_iops = init_iops_scc, \
874 .init_hwif = init_hwif_scc, \
875 .port_ops = &scc_port_ops, \
876 .dma_ops = &scc_dma_ops, \
877 .host_flags = IDE_HFLAG_SINGLE, \
878 .pio_mask = ATA_PIO4, \
881 static const struct ide_port_info scc_chipsets
[] __devinitdata
= {
882 /* 0 */ DECLARE_SCC_DEV("sccIDE"),
886 * scc_init_one - pci layer discovery entry
888 * @id: ident table entry
890 * Called by the PCI code when it finds an SCC PATA controller.
891 * We then use the IDE PCI generic helper to do most of the work.
894 static int __devinit
scc_init_one(struct pci_dev
*dev
, const struct pci_device_id
*id
)
896 return init_setup_scc(dev
, &scc_chipsets
[id
->driver_data
]);
900 * scc_remove - pci layer remove entry
903 * Called by the PCI code when it removes an SCC PATA controller.
906 static void __devexit
scc_remove(struct pci_dev
*dev
)
908 struct scc_ports
*ports
= pci_get_drvdata(dev
);
909 ide_hwif_t
*hwif
= ports
->hwif
;
911 if (hwif
->dmatable_cpu
) {
912 pci_free_consistent(dev
, PRD_ENTRIES
* PRD_BYTES
,
913 hwif
->dmatable_cpu
, hwif
->dmatable_dma
);
914 hwif
->dmatable_cpu
= NULL
;
917 ide_unregister(hwif
);
919 iounmap((void*)ports
->dma
);
920 iounmap((void*)ports
->ctl
);
921 pci_release_selected_regions(dev
, (1 << 2) - 1);
922 memset(ports
, 0, sizeof(*ports
));
925 static const struct pci_device_id scc_pci_tbl
[] = {
926 { PCI_VDEVICE(TOSHIBA_2
, PCI_DEVICE_ID_TOSHIBA_SCC_ATA
), 0 },
929 MODULE_DEVICE_TABLE(pci
, scc_pci_tbl
);
931 static struct pci_driver driver
= {
933 .id_table
= scc_pci_tbl
,
934 .probe
= scc_init_one
,
935 .remove
= scc_remove
,
938 static int scc_ide_init(void)
940 return ide_pci_register_driver(&driver
);
943 module_init(scc_ide_init
);
945 static void scc_ide_exit(void)
947 ide_pci_unregister_driver(&driver);
949 module_exit(scc_ide_exit);
953 MODULE_DESCRIPTION("PCI driver module for Toshiba SCC IDE");
954 MODULE_LICENSE("GPL");