drivers/ide/pci/serverworks.c

   1 /*
   2  * linux/drivers/ide/pci/serverworks.c          Version 0.22    Jun 27 2007
   3  *
   4  * Copyright (C) 1998-2000 Michel Aubry
   5  * Copyright (C) 1998-2000 Andrzej Krzysztofowicz
   6  * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
   7  * Copyright (C)      2007 Bartlomiej Zolnierkiewicz
   8  * Portions copyright (c) 2001 Sun Microsystems
   9  *
  10  *
  11  * RCC/ServerWorks IDE driver for Linux
  12  *
  13  *   OSB4: `Open South Bridge' IDE Interface (fn 1)
  14  *         supports UDMA mode 2 (33 MB/s)
  15  *
  16  *   CSB5: `Champion South Bridge' IDE Interface (fn 1)
  17  *         all revisions support UDMA mode 4 (66 MB/s)
  18  *         revision A2.0 and up support UDMA mode 5 (100 MB/s)
  19  *
  20  *         *** The CSB5 does not provide ANY register ***
  21  *         *** to detect 80-conductor cable presence. ***
  22  *
  23  *   CSB6: `Champion South Bridge' IDE Interface (optional: third channel)
  24  *
  25  *   HT1000: AKA BCM5785 - Hypertransport Southbridge for Opteron systems. IDE
  26  *   controller same as the CSB6. Single channel ATA100 only.
  27  *
  28  * Documentation:
  29  *      Available under NDA only. Errata info very hard to get.
  30  *
  31  */
  32
  33 #include <linux/types.h>
  34 #include <linux/module.h>
  35 #include <linux/kernel.h>
  36 #include <linux/ioport.h>
  37 #include <linux/pci.h>
  38 #include <linux/hdreg.h>
  39 #include <linux/ide.h>
  40 #include <linux/init.h>
  41 #include <linux/delay.h>
  42
  43 #include <asm/io.h>
  44
  45 #define SVWKS_CSB5_REVISION_NEW 0x92 /* min PCI_REVISION_ID for UDMA5 (A2.0) */
  46 #define SVWKS_CSB6_REVISION     0xa0 /* min PCI_REVISION_ID for UDMA4 (A1.0) */
  47
  48 /* Seagate Barracuda ATA IV Family drives in UDMA mode 5
  49  * can overrun their FIFOs when used with the CSB5 */
  50 static const char *svwks_bad_ata100[] = {
  51         "ST320011A",
  52         "ST340016A",
  53         "ST360021A",
  54         "ST380021A",
  55         NULL
  56 };
  57
  58 static struct pci_dev *isa_dev;
  59
  60 static int check_in_drive_lists (ide_drive_t *drive, const char **list)
  61 {
  62         while (*list)
  63                 if (!strcmp(*list++, drive->id->model))
  64                         return 1;
  65         return 0;
  66 }
  67
  68 static u8 svwks_udma_filter(ide_drive_t *drive)
  69 {
  70         struct pci_dev *dev     = HWIF(drive)->pci_dev;
  71         u8 mask = 0;
  72
  73         if (dev->device == PCI_DEVICE_ID_SERVERWORKS_HT1000IDE)
  74                 return 0x1f;
  75         if (dev->device == PCI_DEVICE_ID_SERVERWORKS_OSB4IDE) {
  76                 u32 reg = 0;
  77                 if (isa_dev)
  78                         pci_read_config_dword(isa_dev, 0x64, &reg);
  79
  80                 /*
  81                  *      Don't enable UDMA on disk devices for the moment
  82                  */
  83                 if(drive->media == ide_disk)
  84                         return 0;
  85                 /* Check the OSB4 DMA33 enable bit */
  86                 return ((reg & 0x00004000) == 0x00004000) ? 0x07 : 0;
  87         } else if (dev->revision < SVWKS_CSB5_REVISION_NEW) {
  88                 return 0x07;
  89         } else if (dev->revision >= SVWKS_CSB5_REVISION_NEW) {
  90                 u8 btr = 0, mode;
  91                 pci_read_config_byte(dev, 0x5A, &btr);
  92                 mode = btr & 0x3;
  93
  94                 /* If someone decides to do UDMA133 on CSB5 the same
  95                    issue will bite so be inclusive */
  96                 if (mode > 2 && check_in_drive_lists(drive, svwks_bad_ata100))
  97                         mode = 2;
  98
  99                 switch(mode) {
 100                 case 2:  mask = 0x1f; break;
 101                 case 1:  mask = 0x07; break;
 102                 default: mask = 0x00; break;
 103                 }
 104         }
 105         if (((dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE) ||
 106              (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2)) &&
 107             (!(PCI_FUNC(dev->devfn) & 1)))
 108                 mask = 0x1f;
 109
 110         return mask;
 111 }
 112
 113 static u8 svwks_csb_check (struct pci_dev *dev)
 114 {
 115         switch (dev->device) {
 116                 case PCI_DEVICE_ID_SERVERWORKS_CSB5IDE:
 117                 case PCI_DEVICE_ID_SERVERWORKS_CSB6IDE:
 118                 case PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2:
 119                 case PCI_DEVICE_ID_SERVERWORKS_HT1000IDE:
 120                         return 1;
 121                 default:
 122                         break;
 123         }
 124         return 0;
 125 }
 126
 127 static void svwks_tune_pio(ide_drive_t *drive, const u8 pio)
 128 {
 129         static const u8 pio_modes[] = { 0x5d, 0x47, 0x34, 0x22, 0x20 };
 130         static const u8 drive_pci[] = { 0x41, 0x40, 0x43, 0x42 };
 131
 132         struct pci_dev *dev = drive->hwif->pci_dev;
 133
 134         pci_write_config_byte(dev, drive_pci[drive->dn], pio_modes[pio]);
 135
 136         if (svwks_csb_check(dev)) {
 137                 u16 csb_pio = 0;
 138
 139                 pci_read_config_word(dev, 0x4a, &csb_pio);
 140
 141                 csb_pio &= ~(0x0f << (4 * drive->dn));
 142                 csb_pio |= (pio << (4 * drive->dn));
 143
 144                 pci_write_config_word(dev, 0x4a, csb_pio);
 145         }
 146 }
 147
 148 static int svwks_tune_chipset(ide_drive_t *drive, const u8 speed)
 149 {
 150         static const u8 udma_modes[]            = { 0x00, 0x01, 0x02, 0x03, 0x04, 0x05 };
 151         static const u8 dma_modes[]             = { 0x77, 0x21, 0x20 };
 152         static const u8 drive_pci2[]            = { 0x45, 0x44, 0x47, 0x46 };
 153
 154         ide_hwif_t *hwif        = HWIF(drive);
 155         struct pci_dev *dev     = hwif->pci_dev;
 156         u8 unit                 = (drive->select.b.unit & 0x01);
 157
 158         u8 ultra_enable  = 0, ultra_timing = 0, dma_timing = 0;
 159
 160         /* If we are about to put a disk into UDMA mode we screwed up.
 161            Our code assumes we never _ever_ do this on an OSB4 */
 162
 163         if(dev->device == PCI_DEVICE_ID_SERVERWORKS_OSB4 &&
 164                 drive->media == ide_disk && speed >= XFER_UDMA_0)
 165                         BUG();
 166
 167         pci_read_config_byte(dev, (0x56|hwif->channel), &ultra_timing);
 168         pci_read_config_byte(dev, 0x54, &ultra_enable);
 169
 170         ultra_timing    &= ~(0x0F << (4*unit));
 171         ultra_enable    &= ~(0x01 << drive->dn);
 172
 173         switch(speed) {
 174                 case XFER_MW_DMA_2:
 175                 case XFER_MW_DMA_1:
 176                 case XFER_MW_DMA_0:
 177                         dma_timing |= dma_modes[speed - XFER_MW_DMA_0];
 178                         break;
 179
 180                 case XFER_UDMA_5:
 181                 case XFER_UDMA_4:
 182                 case XFER_UDMA_3:
 183                 case XFER_UDMA_2:
 184                 case XFER_UDMA_1:
 185                 case XFER_UDMA_0:
 186                         dma_timing   |= dma_modes[2];
 187                         ultra_timing |= ((udma_modes[speed - XFER_UDMA_0]) << (4*unit));
 188                         ultra_enable |= (0x01 << drive->dn);
 189                 default:
 190                         break;
 191         }
 192
 193         pci_write_config_byte(dev, drive_pci2[drive->dn], dma_timing);
 194         pci_write_config_byte(dev, (0x56|hwif->channel), ultra_timing);
 195         pci_write_config_byte(dev, 0x54, ultra_enable);
 196
 197         return (ide_config_drive_speed(drive, speed));
 198 }
 199
 200 static void svwks_set_pio_mode(ide_drive_t *drive, const u8 pio)
 201 {
 202         svwks_tune_pio(drive, pio);
 203         (void)ide_config_drive_speed(drive, XFER_PIO_0 + pio);
 204 }
 205
 206 static int svwks_config_drive_xfer_rate (ide_drive_t *drive)
 207 {
 208         drive->init_speed = 0;
 209
 210         if (ide_tune_dma(drive))
 211                 return 0;
 212
 213         if (ide_use_fast_pio(drive))
 214                 ide_set_max_pio(drive);
 215
 216         return -1;
 217 }
 218
 219 static unsigned int __devinit init_chipset_svwks (struct pci_dev *dev, const char *name)
 220 {
 221         unsigned int reg;
 222         u8 btr;
 223
 224         /* force Master Latency Timer value to 64 PCICLKs */
 225         pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x40);
 226
 227         /* OSB4 : South Bridge and IDE */
 228         if (dev->device == PCI_DEVICE_ID_SERVERWORKS_OSB4IDE) {
 229                 isa_dev = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
 230                           PCI_DEVICE_ID_SERVERWORKS_OSB4, NULL);
 231                 if (isa_dev) {
 232                         pci_read_config_dword(isa_dev, 0x64, &reg);
 233                         reg &= ~0x00002000; /* disable 600ns interrupt mask */
 234                         if(!(reg & 0x00004000))
 235                                 printk(KERN_DEBUG "%s: UDMA not BIOS enabled.\n", name);
 236                         reg |=  0x00004000; /* enable UDMA/33 support */
 237                         pci_write_config_dword(isa_dev, 0x64, reg);
 238                 }
 239         }
 240
 241         /* setup CSB5/CSB6 : South Bridge and IDE option RAID */
 242         else if ((dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5IDE) ||
 243                  (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE) ||
 244                  (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2)) {
 245
 246                 /* Third Channel Test */
 247                 if (!(PCI_FUNC(dev->devfn) & 1)) {
 248                         struct pci_dev * findev = NULL;
 249                         u32 reg4c = 0;
 250                         findev = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
 251                                 PCI_DEVICE_ID_SERVERWORKS_CSB5, NULL);
 252                         if (findev) {
 253                                 pci_read_config_dword(findev, 0x4C, &reg4c);
 254                                 reg4c &= ~0x000007FF;
 255                                 reg4c |=  0x00000040;
 256                                 reg4c |=  0x00000020;
 257                                 pci_write_config_dword(findev, 0x4C, reg4c);
 258                                 pci_dev_put(findev);
 259                         }
 260                         outb_p(0x06, 0x0c00);
 261                         dev->irq = inb_p(0x0c01);
 262                 } else {
 263                         struct pci_dev * findev = NULL;
 264                         u8 reg41 = 0;
 265
 266                         findev = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
 267                                         PCI_DEVICE_ID_SERVERWORKS_CSB6, NULL);
 268                         if (findev) {
 269                                 pci_read_config_byte(findev, 0x41, &reg41);
 270                                 reg41 &= ~0x40;
 271                                 pci_write_config_byte(findev, 0x41, reg41);
 272                                 pci_dev_put(findev);
 273                         }
 274                         /*
 275                          * This is a device pin issue on CSB6.
 276                          * Since there will be a future raid mode,
 277                          * early versions of the chipset require the
 278                          * interrupt pin to be set, and it is a compatibility
 279                          * mode issue.
 280                          */
 281                         if ((dev->class >> 8) == PCI_CLASS_STORAGE_IDE)
 282                                 dev->irq = 0;
 283                 }
 284 //              pci_read_config_dword(dev, 0x40, &pioreg)
 285 //              pci_write_config_dword(dev, 0x40, 0x99999999);
 286 //              pci_read_config_dword(dev, 0x44, &dmareg);
 287 //              pci_write_config_dword(dev, 0x44, 0xFFFFFFFF);
 288                 /* setup the UDMA Control register
 289                  *
 290                  * 1. clear bit 6 to enable DMA
 291                  * 2. enable DMA modes with bits 0-1
 292                  *      00 : legacy
 293                  *      01 : udma2
 294                  *      10 : udma2/udma4
 295                  *      11 : udma2/udma4/udma5
 296                  */
 297                 pci_read_config_byte(dev, 0x5A, &btr);
 298                 btr &= ~0x40;
 299                 if (!(PCI_FUNC(dev->devfn) & 1))
 300                         btr |= 0x2;
 301                 else
 302                         btr |= (dev->revision >= SVWKS_CSB5_REVISION_NEW) ? 0x3 : 0x2;
 303                 pci_write_config_byte(dev, 0x5A, btr);
 304         }
 305         /* Setup HT1000 SouthBridge Controller - Single Channel Only */
 306         else if (dev->device == PCI_DEVICE_ID_SERVERWORKS_HT1000IDE) {
 307                 pci_read_config_byte(dev, 0x5A, &btr);
 308                 btr &= ~0x40;
 309                 btr |= 0x3;
 310                 pci_write_config_byte(dev, 0x5A, btr);
 311         }
 312
 313         return dev->irq;
 314 }
 315
 316 static u8 __devinit ata66_svwks_svwks(ide_hwif_t *hwif)
 317 {
 318         return ATA_CBL_PATA80;
 319 }
 320
 321 /* On Dell PowerEdge servers with a CSB5/CSB6, the top two bits
 322  * of the subsystem device ID indicate presence of an 80-pin cable.
 323  * Bit 15 clear = secondary IDE channel does not have 80-pin cable.
 324  * Bit 15 set   = secondary IDE channel has 80-pin cable.
 325  * Bit 14 clear = primary IDE channel does not have 80-pin cable.
 326  * Bit 14 set   = primary IDE channel has 80-pin cable.
 327  */
 328 static u8 __devinit ata66_svwks_dell(ide_hwif_t *hwif)
 329 {
 330         struct pci_dev *dev = hwif->pci_dev;
 331         if (dev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
 332             dev->vendor == PCI_VENDOR_ID_SERVERWORKS &&
 333             (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5IDE ||
 334              dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE))
 335                 return ((1 << (hwif->channel + 14)) &
 336                         dev->subsystem_device) ? ATA_CBL_PATA80 : ATA_CBL_PATA40;
 337         return ATA_CBL_PATA40;
 338 }
 339
 340 /* Sun Cobalt Alpine hardware avoids the 80-pin cable
 341  * detect issue by attaching the drives directly to the board.
 342  * This check follows the Dell precedent (how scary is that?!)
 343  *
 344  * WARNING: this only works on Alpine hardware!
 345  */
 346 static u8 __devinit ata66_svwks_cobalt(ide_hwif_t *hwif)
 347 {
 348         struct pci_dev *dev = hwif->pci_dev;
 349         if (dev->subsystem_vendor == PCI_VENDOR_ID_SUN &&
 350             dev->vendor == PCI_VENDOR_ID_SERVERWORKS &&
 351             dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5IDE)
 352                 return ((1 << (hwif->channel + 14)) &
 353                         dev->subsystem_device) ? ATA_CBL_PATA80 : ATA_CBL_PATA40;
 354         return ATA_CBL_PATA40;
 355 }
 356
 357 static u8 __devinit ata66_svwks(ide_hwif_t *hwif)
 358 {
 359         struct pci_dev *dev = hwif->pci_dev;
 360
 361         /* Server Works */
 362         if (dev->subsystem_vendor == PCI_VENDOR_ID_SERVERWORKS)
 363                 return ata66_svwks_svwks (hwif);
 364
 365         /* Dell PowerEdge */
 366         if (dev->subsystem_vendor == PCI_VENDOR_ID_DELL)
 367                 return ata66_svwks_dell (hwif);
 368
 369         /* Cobalt Alpine */
 370         if (dev->subsystem_vendor == PCI_VENDOR_ID_SUN)
 371                 return ata66_svwks_cobalt (hwif);
 372
 373         /* Per Specified Design by OEM, and ASIC Architect */
 374         if ((dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE) ||
 375             (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2))
 376                 return ATA_CBL_PATA80;
 377
 378         return ATA_CBL_PATA40;
 379 }
 380
 381 static void __devinit init_hwif_svwks (ide_hwif_t *hwif)
 382 {
 383         if (!hwif->irq)
 384                 hwif->irq = hwif->channel ? 15 : 14;
 385
 386         hwif->set_pio_mode = &svwks_set_pio_mode;
 387         hwif->speedproc = &svwks_tune_chipset;
 388         hwif->udma_filter = &svwks_udma_filter;
 389
 390         hwif->atapi_dma = 1;
 391
 392         if (hwif->pci_dev->device != PCI_DEVICE_ID_SERVERWORKS_OSB4IDE)
 393                 hwif->ultra_mask = 0x3f;
 394
 395         hwif->mwdma_mask = 0x07;
 396
 397         hwif->autodma = 0;
 398
 399         hwif->drives[0].autotune = 1;
 400         hwif->drives[1].autotune = 1;
 401
 402         if (!hwif->dma_base)
 403                 return;
 404
 405         hwif->ide_dma_check = &svwks_config_drive_xfer_rate;
 406         if (hwif->pci_dev->device != PCI_DEVICE_ID_SERVERWORKS_OSB4IDE) {
 407                 if (hwif->cbl != ATA_CBL_PATA40_SHORT)
 408                         hwif->cbl = ata66_svwks(hwif);
 409         }
 410         if (!noautodma)
 411                 hwif->autodma = 1;
 412
 413         hwif->drives[0].autodma = hwif->drives[1].autodma = 1;
 414 }
 415
 416 static int __devinit init_setup_svwks (struct pci_dev *dev, ide_pci_device_t *d)
 417 {
 418         return ide_setup_pci_device(dev, d);
 419 }
 420
 421 static int __devinit init_setup_csb6 (struct pci_dev *dev, ide_pci_device_t *d)
 422 {
 423         if (!(PCI_FUNC(dev->devfn) & 1)) {
 424                 d->bootable = NEVER_BOARD;
 425                 if (dev->resource[0].start == 0x01f1)
 426                         d->bootable = ON_BOARD;
 427         }
 428
 429         if ((dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE ||
 430             dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2) &&
 431             (!(PCI_FUNC(dev->devfn) & 1)))
 432                 d->host_flags |= IDE_HFLAG_SINGLE;
 433         else
 434                 d->host_flags &= ~IDE_HFLAG_SINGLE;
 435
 436         return ide_setup_pci_device(dev, d);
 437 }
 438
 439 static ide_pci_device_t serverworks_chipsets[] __devinitdata = {
 440         {       /* 0 */
 441                 .name           = "SvrWks OSB4",
 442                 .init_setup     = init_setup_svwks,
 443                 .init_chipset   = init_chipset_svwks,
 444                 .init_hwif      = init_hwif_svwks,
 445                 .autodma        = AUTODMA,
 446                 .bootable       = ON_BOARD,
 447                 .pio_mask       = ATA_PIO4,
 448         },{     /* 1 */
 449                 .name           = "SvrWks CSB5",
 450                 .init_setup     = init_setup_svwks,
 451                 .init_chipset   = init_chipset_svwks,
 452                 .init_hwif      = init_hwif_svwks,
 453                 .autodma        = AUTODMA,
 454                 .bootable       = ON_BOARD,
 455                 .pio_mask       = ATA_PIO4,
 456         },{     /* 2 */
 457                 .name           = "SvrWks CSB6",
 458                 .init_setup     = init_setup_csb6,
 459                 .init_chipset   = init_chipset_svwks,
 460                 .init_hwif      = init_hwif_svwks,
 461                 .autodma        = AUTODMA,
 462                 .bootable       = ON_BOARD,
 463                 .pio_mask       = ATA_PIO4,
 464         },{     /* 3 */
 465                 .name           = "SvrWks CSB6",
 466                 .init_setup     = init_setup_csb6,
 467                 .init_chipset   = init_chipset_svwks,
 468                 .init_hwif      = init_hwif_svwks,
 469                 .autodma        = AUTODMA,
 470                 .bootable       = ON_BOARD,
 471                 .host_flags     = IDE_HFLAG_SINGLE,
 472                 .pio_mask       = ATA_PIO4,
 473         },{     /* 4 */
 474                 .name           = "SvrWks HT1000",
 475                 .init_setup     = init_setup_svwks,
 476                 .init_chipset   = init_chipset_svwks,
 477                 .init_hwif      = init_hwif_svwks,
 478                 .autodma        = AUTODMA,
 479                 .bootable       = ON_BOARD,
 480                 .host_flags     = IDE_HFLAG_SINGLE,
 481                 .pio_mask       = ATA_PIO4,
 482         }
 483 };
 484
 485 /**
 486  *      svwks_init_one  -       called when a OSB/CSB is found
 487  *      @dev: the svwks device
 488  *      @id: the matching pci id
 489  *
 490  *      Called when the PCI registration layer (or the IDE initialization)
 491  *      finds a device matching our IDE device tables.
 492  */
 493
 494 static int __devinit svwks_init_one(struct pci_dev *dev, const struct pci_device_id *id)
 495 {
 496         ide_pci_device_t *d = &serverworks_chipsets[id->driver_data];
 497
 498         return d->init_setup(dev, d);
 499 }
 500
 501 static struct pci_device_id svwks_pci_tbl[] = {
 502         { PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_OSB4IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
 503         { PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1},
 504         { PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB6IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2},
 505         { PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3},
 506         { PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4},
 507         { 0, },
 508 };
 509 MODULE_DEVICE_TABLE(pci, svwks_pci_tbl);
 510
 511 static struct pci_driver driver = {
 512         .name           = "Serverworks_IDE",
 513         .id_table       = svwks_pci_tbl,
 514         .probe          = svwks_init_one,
 515 };
 516
 517 static int __init svwks_ide_init(void)
 518 {
 519         return ide_pci_register_driver(&driver);
 520 }
 521
 522 module_init(svwks_ide_init);
 523
 524 MODULE_AUTHOR("Michael Aubry. Andrzej Krzysztofowicz, Andre Hedrick");
 525 MODULE_DESCRIPTION("PCI driver module for Serverworks OSB4/CSB5/CSB6 IDE");
 526 MODULE_LICENSE("GPL");