2 * linux/drivers/ide/pci/serverworks.c Version 0.22 Jun 27 2007
4 * Copyright (C) 1998-2000 Michel Aubry
5 * Copyright (C) 1998-2000 Andrzej Krzysztofowicz
6 * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
7 * Copyright (C) 2007 Bartlomiej Zolnierkiewicz
8 * Portions copyright (c) 2001 Sun Microsystems
11 * RCC/ServerWorks IDE driver for Linux
13 * OSB4: `Open South Bridge' IDE Interface (fn 1)
14 * supports UDMA mode 2 (33 MB/s)
16 * CSB5: `Champion South Bridge' IDE Interface (fn 1)
17 * all revisions support UDMA mode 4 (66 MB/s)
18 * revision A2.0 and up support UDMA mode 5 (100 MB/s)
20 * *** The CSB5 does not provide ANY register ***
21 * *** to detect 80-conductor cable presence. ***
23 * CSB6: `Champion South Bridge' IDE Interface (optional: third channel)
25 * HT1000: AKA BCM5785 - Hypertransport Southbridge for Opteron systems. IDE
26 * controller same as the CSB6. Single channel ATA100 only.
29 * Available under NDA only. Errata info very hard to get.
33 #include <linux/types.h>
34 #include <linux/module.h>
35 #include <linux/kernel.h>
36 #include <linux/ioport.h>
37 #include <linux/pci.h>
38 #include <linux/hdreg.h>
39 #include <linux/ide.h>
40 #include <linux/init.h>
41 #include <linux/delay.h>
45 #define SVWKS_CSB5_REVISION_NEW 0x92 /* min PCI_REVISION_ID for UDMA5 (A2.0) */
46 #define SVWKS_CSB6_REVISION 0xa0 /* min PCI_REVISION_ID for UDMA4 (A1.0) */
48 /* Seagate Barracuda ATA IV Family drives in UDMA mode 5
49 * can overrun their FIFOs when used with the CSB5 */
50 static const char *svwks_bad_ata100
[] = {
58 static struct pci_dev
*isa_dev
;
60 static int check_in_drive_lists (ide_drive_t
*drive
, const char **list
)
63 if (!strcmp(*list
++, drive
->id
->model
))
68 static u8
svwks_udma_filter(ide_drive_t
*drive
)
70 struct pci_dev
*dev
= HWIF(drive
)->pci_dev
;
73 if (dev
->device
== PCI_DEVICE_ID_SERVERWORKS_HT1000IDE
)
75 if (dev
->device
== PCI_DEVICE_ID_SERVERWORKS_OSB4IDE
) {
78 pci_read_config_dword(isa_dev
, 0x64, ®
);
81 * Don't enable UDMA on disk devices for the moment
83 if(drive
->media
== ide_disk
)
85 /* Check the OSB4 DMA33 enable bit */
86 return ((reg
& 0x00004000) == 0x00004000) ? 0x07 : 0;
87 } else if (dev
->revision
< SVWKS_CSB5_REVISION_NEW
) {
89 } else if (dev
->revision
>= SVWKS_CSB5_REVISION_NEW
) {
91 pci_read_config_byte(dev
, 0x5A, &btr
);
94 /* If someone decides to do UDMA133 on CSB5 the same
95 issue will bite so be inclusive */
96 if (mode
> 2 && check_in_drive_lists(drive
, svwks_bad_ata100
))
100 case 2: mask
= 0x1f; break;
101 case 1: mask
= 0x07; break;
102 default: mask
= 0x00; break;
105 if (((dev
->device
== PCI_DEVICE_ID_SERVERWORKS_CSB6IDE
) ||
106 (dev
->device
== PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2
)) &&
107 (!(PCI_FUNC(dev
->devfn
) & 1)))
113 static u8
svwks_csb_check (struct pci_dev
*dev
)
115 switch (dev
->device
) {
116 case PCI_DEVICE_ID_SERVERWORKS_CSB5IDE
:
117 case PCI_DEVICE_ID_SERVERWORKS_CSB6IDE
:
118 case PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2
:
119 case PCI_DEVICE_ID_SERVERWORKS_HT1000IDE
:
127 static void svwks_set_pio_mode(ide_drive_t
*drive
, const u8 pio
)
129 static const u8 pio_modes
[] = { 0x5d, 0x47, 0x34, 0x22, 0x20 };
130 static const u8 drive_pci
[] = { 0x41, 0x40, 0x43, 0x42 };
132 struct pci_dev
*dev
= drive
->hwif
->pci_dev
;
134 pci_write_config_byte(dev
, drive_pci
[drive
->dn
], pio_modes
[pio
]);
136 if (svwks_csb_check(dev
)) {
139 pci_read_config_word(dev
, 0x4a, &csb_pio
);
141 csb_pio
&= ~(0x0f << (4 * drive
->dn
));
142 csb_pio
|= (pio
<< (4 * drive
->dn
));
144 pci_write_config_word(dev
, 0x4a, csb_pio
);
148 static void svwks_set_dma_mode(ide_drive_t
*drive
, const u8 speed
)
150 static const u8 udma_modes
[] = { 0x00, 0x01, 0x02, 0x03, 0x04, 0x05 };
151 static const u8 dma_modes
[] = { 0x77, 0x21, 0x20 };
152 static const u8 drive_pci2
[] = { 0x45, 0x44, 0x47, 0x46 };
154 ide_hwif_t
*hwif
= HWIF(drive
);
155 struct pci_dev
*dev
= hwif
->pci_dev
;
156 u8 unit
= (drive
->select
.b
.unit
& 0x01);
158 u8 ultra_enable
= 0, ultra_timing
= 0, dma_timing
= 0;
160 /* If we are about to put a disk into UDMA mode we screwed up.
161 Our code assumes we never _ever_ do this on an OSB4 */
163 if(dev
->device
== PCI_DEVICE_ID_SERVERWORKS_OSB4
&&
164 drive
->media
== ide_disk
&& speed
>= XFER_UDMA_0
)
167 pci_read_config_byte(dev
, (0x56|hwif
->channel
), &ultra_timing
);
168 pci_read_config_byte(dev
, 0x54, &ultra_enable
);
170 ultra_timing
&= ~(0x0F << (4*unit
));
171 ultra_enable
&= ~(0x01 << drive
->dn
);
177 dma_timing
|= dma_modes
[speed
- XFER_MW_DMA_0
];
186 dma_timing
|= dma_modes
[2];
187 ultra_timing
|= ((udma_modes
[speed
- XFER_UDMA_0
]) << (4*unit
));
188 ultra_enable
|= (0x01 << drive
->dn
);
193 pci_write_config_byte(dev
, drive_pci2
[drive
->dn
], dma_timing
);
194 pci_write_config_byte(dev
, (0x56|hwif
->channel
), ultra_timing
);
195 pci_write_config_byte(dev
, 0x54, ultra_enable
);
198 static int svwks_config_drive_xfer_rate (ide_drive_t
*drive
)
200 drive
->init_speed
= 0;
202 if (ide_tune_dma(drive
))
205 if (ide_use_fast_pio(drive
))
206 ide_set_max_pio(drive
);
211 static unsigned int __devinit
init_chipset_svwks (struct pci_dev
*dev
, const char *name
)
216 /* force Master Latency Timer value to 64 PCICLKs */
217 pci_write_config_byte(dev
, PCI_LATENCY_TIMER
, 0x40);
219 /* OSB4 : South Bridge and IDE */
220 if (dev
->device
== PCI_DEVICE_ID_SERVERWORKS_OSB4IDE
) {
221 isa_dev
= pci_get_device(PCI_VENDOR_ID_SERVERWORKS
,
222 PCI_DEVICE_ID_SERVERWORKS_OSB4
, NULL
);
224 pci_read_config_dword(isa_dev
, 0x64, ®
);
225 reg
&= ~0x00002000; /* disable 600ns interrupt mask */
226 if(!(reg
& 0x00004000))
227 printk(KERN_DEBUG
"%s: UDMA not BIOS enabled.\n", name
);
228 reg
|= 0x00004000; /* enable UDMA/33 support */
229 pci_write_config_dword(isa_dev
, 0x64, reg
);
233 /* setup CSB5/CSB6 : South Bridge and IDE option RAID */
234 else if ((dev
->device
== PCI_DEVICE_ID_SERVERWORKS_CSB5IDE
) ||
235 (dev
->device
== PCI_DEVICE_ID_SERVERWORKS_CSB6IDE
) ||
236 (dev
->device
== PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2
)) {
238 /* Third Channel Test */
239 if (!(PCI_FUNC(dev
->devfn
) & 1)) {
240 struct pci_dev
* findev
= NULL
;
242 findev
= pci_get_device(PCI_VENDOR_ID_SERVERWORKS
,
243 PCI_DEVICE_ID_SERVERWORKS_CSB5
, NULL
);
245 pci_read_config_dword(findev
, 0x4C, ®4c
);
246 reg4c
&= ~0x000007FF;
249 pci_write_config_dword(findev
, 0x4C, reg4c
);
252 outb_p(0x06, 0x0c00);
253 dev
->irq
= inb_p(0x0c01);
255 struct pci_dev
* findev
= NULL
;
258 findev
= pci_get_device(PCI_VENDOR_ID_SERVERWORKS
,
259 PCI_DEVICE_ID_SERVERWORKS_CSB6
, NULL
);
261 pci_read_config_byte(findev
, 0x41, ®41
);
263 pci_write_config_byte(findev
, 0x41, reg41
);
267 * This is a device pin issue on CSB6.
268 * Since there will be a future raid mode,
269 * early versions of the chipset require the
270 * interrupt pin to be set, and it is a compatibility
273 if ((dev
->class >> 8) == PCI_CLASS_STORAGE_IDE
)
276 // pci_read_config_dword(dev, 0x40, &pioreg)
277 // pci_write_config_dword(dev, 0x40, 0x99999999);
278 // pci_read_config_dword(dev, 0x44, &dmareg);
279 // pci_write_config_dword(dev, 0x44, 0xFFFFFFFF);
280 /* setup the UDMA Control register
282 * 1. clear bit 6 to enable DMA
283 * 2. enable DMA modes with bits 0-1
287 * 11 : udma2/udma4/udma5
289 pci_read_config_byte(dev
, 0x5A, &btr
);
291 if (!(PCI_FUNC(dev
->devfn
) & 1))
294 btr
|= (dev
->revision
>= SVWKS_CSB5_REVISION_NEW
) ? 0x3 : 0x2;
295 pci_write_config_byte(dev
, 0x5A, btr
);
297 /* Setup HT1000 SouthBridge Controller - Single Channel Only */
298 else if (dev
->device
== PCI_DEVICE_ID_SERVERWORKS_HT1000IDE
) {
299 pci_read_config_byte(dev
, 0x5A, &btr
);
302 pci_write_config_byte(dev
, 0x5A, btr
);
308 static u8 __devinit
ata66_svwks_svwks(ide_hwif_t
*hwif
)
310 return ATA_CBL_PATA80
;
313 /* On Dell PowerEdge servers with a CSB5/CSB6, the top two bits
314 * of the subsystem device ID indicate presence of an 80-pin cable.
315 * Bit 15 clear = secondary IDE channel does not have 80-pin cable.
316 * Bit 15 set = secondary IDE channel has 80-pin cable.
317 * Bit 14 clear = primary IDE channel does not have 80-pin cable.
318 * Bit 14 set = primary IDE channel has 80-pin cable.
320 static u8 __devinit
ata66_svwks_dell(ide_hwif_t
*hwif
)
322 struct pci_dev
*dev
= hwif
->pci_dev
;
323 if (dev
->subsystem_vendor
== PCI_VENDOR_ID_DELL
&&
324 dev
->vendor
== PCI_VENDOR_ID_SERVERWORKS
&&
325 (dev
->device
== PCI_DEVICE_ID_SERVERWORKS_CSB5IDE
||
326 dev
->device
== PCI_DEVICE_ID_SERVERWORKS_CSB6IDE
))
327 return ((1 << (hwif
->channel
+ 14)) &
328 dev
->subsystem_device
) ? ATA_CBL_PATA80
: ATA_CBL_PATA40
;
329 return ATA_CBL_PATA40
;
332 /* Sun Cobalt Alpine hardware avoids the 80-pin cable
333 * detect issue by attaching the drives directly to the board.
334 * This check follows the Dell precedent (how scary is that?!)
336 * WARNING: this only works on Alpine hardware!
338 static u8 __devinit
ata66_svwks_cobalt(ide_hwif_t
*hwif
)
340 struct pci_dev
*dev
= hwif
->pci_dev
;
341 if (dev
->subsystem_vendor
== PCI_VENDOR_ID_SUN
&&
342 dev
->vendor
== PCI_VENDOR_ID_SERVERWORKS
&&
343 dev
->device
== PCI_DEVICE_ID_SERVERWORKS_CSB5IDE
)
344 return ((1 << (hwif
->channel
+ 14)) &
345 dev
->subsystem_device
) ? ATA_CBL_PATA80
: ATA_CBL_PATA40
;
346 return ATA_CBL_PATA40
;
349 static u8 __devinit
ata66_svwks(ide_hwif_t
*hwif
)
351 struct pci_dev
*dev
= hwif
->pci_dev
;
354 if (dev
->subsystem_vendor
== PCI_VENDOR_ID_SERVERWORKS
)
355 return ata66_svwks_svwks (hwif
);
358 if (dev
->subsystem_vendor
== PCI_VENDOR_ID_DELL
)
359 return ata66_svwks_dell (hwif
);
362 if (dev
->subsystem_vendor
== PCI_VENDOR_ID_SUN
)
363 return ata66_svwks_cobalt (hwif
);
365 /* Per Specified Design by OEM, and ASIC Architect */
366 if ((dev
->device
== PCI_DEVICE_ID_SERVERWORKS_CSB6IDE
) ||
367 (dev
->device
== PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2
))
368 return ATA_CBL_PATA80
;
370 return ATA_CBL_PATA40
;
373 static void __devinit
init_hwif_svwks (ide_hwif_t
*hwif
)
376 hwif
->irq
= hwif
->channel
? 15 : 14;
378 hwif
->set_pio_mode
= &svwks_set_pio_mode
;
379 hwif
->set_dma_mode
= &svwks_set_dma_mode
;
380 hwif
->udma_filter
= &svwks_udma_filter
;
384 if (hwif
->pci_dev
->device
!= PCI_DEVICE_ID_SERVERWORKS_OSB4IDE
)
385 hwif
->ultra_mask
= 0x3f;
387 hwif
->mwdma_mask
= 0x07;
391 hwif
->drives
[0].autotune
= 1;
392 hwif
->drives
[1].autotune
= 1;
397 hwif
->ide_dma_check
= &svwks_config_drive_xfer_rate
;
398 if (hwif
->pci_dev
->device
!= PCI_DEVICE_ID_SERVERWORKS_OSB4IDE
) {
399 if (hwif
->cbl
!= ATA_CBL_PATA40_SHORT
)
400 hwif
->cbl
= ata66_svwks(hwif
);
405 hwif
->drives
[0].autodma
= hwif
->drives
[1].autodma
= 1;
408 static int __devinit
init_setup_svwks (struct pci_dev
*dev
, ide_pci_device_t
*d
)
410 return ide_setup_pci_device(dev
, d
);
413 static int __devinit
init_setup_csb6 (struct pci_dev
*dev
, ide_pci_device_t
*d
)
415 if (!(PCI_FUNC(dev
->devfn
) & 1)) {
416 d
->bootable
= NEVER_BOARD
;
417 if (dev
->resource
[0].start
== 0x01f1)
418 d
->bootable
= ON_BOARD
;
421 if ((dev
->device
== PCI_DEVICE_ID_SERVERWORKS_CSB6IDE
||
422 dev
->device
== PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2
) &&
423 (!(PCI_FUNC(dev
->devfn
) & 1)))
424 d
->host_flags
|= IDE_HFLAG_SINGLE
;
426 d
->host_flags
&= ~IDE_HFLAG_SINGLE
;
428 return ide_setup_pci_device(dev
, d
);
431 static ide_pci_device_t serverworks_chipsets
[] __devinitdata
= {
433 .name
= "SvrWks OSB4",
434 .init_setup
= init_setup_svwks
,
435 .init_chipset
= init_chipset_svwks
,
436 .init_hwif
= init_hwif_svwks
,
438 .bootable
= ON_BOARD
,
439 .pio_mask
= ATA_PIO4
,
441 .name
= "SvrWks CSB5",
442 .init_setup
= init_setup_svwks
,
443 .init_chipset
= init_chipset_svwks
,
444 .init_hwif
= init_hwif_svwks
,
446 .bootable
= ON_BOARD
,
447 .pio_mask
= ATA_PIO4
,
449 .name
= "SvrWks CSB6",
450 .init_setup
= init_setup_csb6
,
451 .init_chipset
= init_chipset_svwks
,
452 .init_hwif
= init_hwif_svwks
,
454 .bootable
= ON_BOARD
,
455 .pio_mask
= ATA_PIO4
,
457 .name
= "SvrWks CSB6",
458 .init_setup
= init_setup_csb6
,
459 .init_chipset
= init_chipset_svwks
,
460 .init_hwif
= init_hwif_svwks
,
462 .bootable
= ON_BOARD
,
463 .host_flags
= IDE_HFLAG_SINGLE
,
464 .pio_mask
= ATA_PIO4
,
466 .name
= "SvrWks HT1000",
467 .init_setup
= init_setup_svwks
,
468 .init_chipset
= init_chipset_svwks
,
469 .init_hwif
= init_hwif_svwks
,
471 .bootable
= ON_BOARD
,
472 .host_flags
= IDE_HFLAG_SINGLE
,
473 .pio_mask
= ATA_PIO4
,
478 * svwks_init_one - called when a OSB/CSB is found
479 * @dev: the svwks device
480 * @id: the matching pci id
482 * Called when the PCI registration layer (or the IDE initialization)
483 * finds a device matching our IDE device tables.
486 static int __devinit
svwks_init_one(struct pci_dev
*dev
, const struct pci_device_id
*id
)
488 ide_pci_device_t
*d
= &serverworks_chipsets
[id
->driver_data
];
490 return d
->init_setup(dev
, d
);
493 static struct pci_device_id svwks_pci_tbl
[] = {
494 { PCI_VENDOR_ID_SERVERWORKS
, PCI_DEVICE_ID_SERVERWORKS_OSB4IDE
, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0},
495 { PCI_VENDOR_ID_SERVERWORKS
, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE
, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 1},
496 { PCI_VENDOR_ID_SERVERWORKS
, PCI_DEVICE_ID_SERVERWORKS_CSB6IDE
, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 2},
497 { PCI_VENDOR_ID_SERVERWORKS
, PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2
, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 3},
498 { PCI_VENDOR_ID_SERVERWORKS
, PCI_DEVICE_ID_SERVERWORKS_HT1000IDE
, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 4},
501 MODULE_DEVICE_TABLE(pci
, svwks_pci_tbl
);
503 static struct pci_driver driver
= {
504 .name
= "Serverworks_IDE",
505 .id_table
= svwks_pci_tbl
,
506 .probe
= svwks_init_one
,
509 static int __init
svwks_ide_init(void)
511 return ide_pci_register_driver(&driver
);
514 module_init(svwks_ide_init
);
516 MODULE_AUTHOR("Michael Aubry. Andrzej Krzysztofowicz, Andre Hedrick");
517 MODULE_DESCRIPTION("PCI driver module for Serverworks OSB4/CSB5/CSB6 IDE");
518 MODULE_LICENSE("GPL");