2 * linux/drivers/ide/pci/serverworks.c Version 0.22 Jun 27 2007
4 * Copyright (C) 1998-2000 Michel Aubry
5 * Copyright (C) 1998-2000 Andrzej Krzysztofowicz
6 * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
7 * Copyright (C) 2007 Bartlomiej Zolnierkiewicz
8 * Portions copyright (c) 2001 Sun Microsystems
11 * RCC/ServerWorks IDE driver for Linux
13 * OSB4: `Open South Bridge' IDE Interface (fn 1)
14 * supports UDMA mode 2 (33 MB/s)
16 * CSB5: `Champion South Bridge' IDE Interface (fn 1)
17 * all revisions support UDMA mode 4 (66 MB/s)
18 * revision A2.0 and up support UDMA mode 5 (100 MB/s)
20 * *** The CSB5 does not provide ANY register ***
21 * *** to detect 80-conductor cable presence. ***
23 * CSB6: `Champion South Bridge' IDE Interface (optional: third channel)
25 * HT1000: AKA BCM5785 - Hypertransport Southbridge for Opteron systems. IDE
26 * controller same as the CSB6. Single channel ATA100 only.
29 * Available under NDA only. Errata info very hard to get.
33 #include <linux/types.h>
34 #include <linux/module.h>
35 #include <linux/kernel.h>
36 #include <linux/ioport.h>
37 #include <linux/pci.h>
38 #include <linux/hdreg.h>
39 #include <linux/ide.h>
40 #include <linux/init.h>
41 #include <linux/delay.h>
45 #define SVWKS_CSB5_REVISION_NEW 0x92 /* min PCI_REVISION_ID for UDMA5 (A2.0) */
46 #define SVWKS_CSB6_REVISION 0xa0 /* min PCI_REVISION_ID for UDMA4 (A1.0) */
48 /* Seagate Barracuda ATA IV Family drives in UDMA mode 5
49 * can overrun their FIFOs when used with the CSB5 */
50 static const char *svwks_bad_ata100
[] = {
58 static struct pci_dev
*isa_dev
;
60 static int check_in_drive_lists (ide_drive_t
*drive
, const char **list
)
63 if (!strcmp(*list
++, drive
->id
->model
))
68 static u8
svwks_udma_filter(ide_drive_t
*drive
)
70 struct pci_dev
*dev
= HWIF(drive
)->pci_dev
;
73 if (dev
->device
== PCI_DEVICE_ID_SERVERWORKS_HT1000IDE
)
75 if (dev
->device
== PCI_DEVICE_ID_SERVERWORKS_OSB4IDE
) {
78 pci_read_config_dword(isa_dev
, 0x64, ®
);
81 * Don't enable UDMA on disk devices for the moment
83 if(drive
->media
== ide_disk
)
85 /* Check the OSB4 DMA33 enable bit */
86 return ((reg
& 0x00004000) == 0x00004000) ? 0x07 : 0;
87 } else if (dev
->revision
< SVWKS_CSB5_REVISION_NEW
) {
89 } else if (dev
->revision
>= SVWKS_CSB5_REVISION_NEW
) {
91 pci_read_config_byte(dev
, 0x5A, &btr
);
94 /* If someone decides to do UDMA133 on CSB5 the same
95 issue will bite so be inclusive */
96 if (mode
> 2 && check_in_drive_lists(drive
, svwks_bad_ata100
))
100 case 2: mask
= 0x1f; break;
101 case 1: mask
= 0x07; break;
102 default: mask
= 0x00; break;
105 if (((dev
->device
== PCI_DEVICE_ID_SERVERWORKS_CSB6IDE
) ||
106 (dev
->device
== PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2
)) &&
107 (!(PCI_FUNC(dev
->devfn
) & 1)))
113 static u8
svwks_csb_check (struct pci_dev
*dev
)
115 switch (dev
->device
) {
116 case PCI_DEVICE_ID_SERVERWORKS_CSB5IDE
:
117 case PCI_DEVICE_ID_SERVERWORKS_CSB6IDE
:
118 case PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2
:
119 case PCI_DEVICE_ID_SERVERWORKS_HT1000IDE
:
127 static void svwks_tune_pio(ide_drive_t
*drive
, const u8 pio
)
129 static const u8 pio_modes
[] = { 0x5d, 0x47, 0x34, 0x22, 0x20 };
130 static const u8 drive_pci
[] = { 0x41, 0x40, 0x43, 0x42 };
132 struct pci_dev
*dev
= drive
->hwif
->pci_dev
;
134 pci_write_config_byte(dev
, drive_pci
[drive
->dn
], pio_modes
[pio
]);
136 if (svwks_csb_check(dev
)) {
139 pci_read_config_word(dev
, 0x4a, &csb_pio
);
141 csb_pio
&= ~(0x0f << (4 * drive
->dn
));
142 csb_pio
|= (pio
<< (4 * drive
->dn
));
144 pci_write_config_word(dev
, 0x4a, csb_pio
);
148 static int svwks_tune_chipset (ide_drive_t
*drive
, u8 xferspeed
)
150 static const u8 udma_modes
[] = { 0x00, 0x01, 0x02, 0x03, 0x04, 0x05 };
151 static const u8 dma_modes
[] = { 0x77, 0x21, 0x20 };
152 static const u8 drive_pci2
[] = { 0x45, 0x44, 0x47, 0x46 };
154 ide_hwif_t
*hwif
= HWIF(drive
);
155 struct pci_dev
*dev
= hwif
->pci_dev
;
156 u8 speed
= ide_rate_filter(drive
, xferspeed
);
157 u8 unit
= (drive
->select
.b
.unit
& 0x01);
159 u8 ultra_enable
= 0, ultra_timing
= 0, dma_timing
= 0;
161 if (speed
>= XFER_PIO_0
&& speed
<= XFER_PIO_4
) {
162 svwks_tune_pio(drive
, speed
- XFER_PIO_0
);
163 return ide_config_drive_speed(drive
, speed
);
166 /* If we are about to put a disk into UDMA mode we screwed up.
167 Our code assumes we never _ever_ do this on an OSB4 */
169 if(dev
->device
== PCI_DEVICE_ID_SERVERWORKS_OSB4
&&
170 drive
->media
== ide_disk
&& speed
>= XFER_UDMA_0
)
173 pci_read_config_byte(dev
, (0x56|hwif
->channel
), &ultra_timing
);
174 pci_read_config_byte(dev
, 0x54, &ultra_enable
);
176 ultra_timing
&= ~(0x0F << (4*unit
));
177 ultra_enable
&= ~(0x01 << drive
->dn
);
183 dma_timing
|= dma_modes
[speed
- XFER_MW_DMA_0
];
192 dma_timing
|= dma_modes
[2];
193 ultra_timing
|= ((udma_modes
[speed
- XFER_UDMA_0
]) << (4*unit
));
194 ultra_enable
|= (0x01 << drive
->dn
);
199 pci_write_config_byte(dev
, drive_pci2
[drive
->dn
], dma_timing
);
200 pci_write_config_byte(dev
, (0x56|hwif
->channel
), ultra_timing
);
201 pci_write_config_byte(dev
, 0x54, ultra_enable
);
203 return (ide_config_drive_speed(drive
, speed
));
206 static void svwks_tune_drive (ide_drive_t
*drive
, u8 pio
)
208 pio
= ide_get_best_pio_mode(drive
, pio
, 4);
209 svwks_tune_pio(drive
, pio
);
210 (void)ide_config_drive_speed(drive
, XFER_PIO_0
+ pio
);
213 static int svwks_config_drive_xfer_rate (ide_drive_t
*drive
)
215 drive
->init_speed
= 0;
217 if (ide_tune_dma(drive
))
220 if (ide_use_fast_pio(drive
))
221 svwks_tune_drive(drive
, 255);
226 static unsigned int __devinit
init_chipset_svwks (struct pci_dev
*dev
, const char *name
)
231 /* force Master Latency Timer value to 64 PCICLKs */
232 pci_write_config_byte(dev
, PCI_LATENCY_TIMER
, 0x40);
234 /* OSB4 : South Bridge and IDE */
235 if (dev
->device
== PCI_DEVICE_ID_SERVERWORKS_OSB4IDE
) {
236 isa_dev
= pci_get_device(PCI_VENDOR_ID_SERVERWORKS
,
237 PCI_DEVICE_ID_SERVERWORKS_OSB4
, NULL
);
239 pci_read_config_dword(isa_dev
, 0x64, ®
);
240 reg
&= ~0x00002000; /* disable 600ns interrupt mask */
241 if(!(reg
& 0x00004000))
242 printk(KERN_DEBUG
"%s: UDMA not BIOS enabled.\n", name
);
243 reg
|= 0x00004000; /* enable UDMA/33 support */
244 pci_write_config_dword(isa_dev
, 0x64, reg
);
248 /* setup CSB5/CSB6 : South Bridge and IDE option RAID */
249 else if ((dev
->device
== PCI_DEVICE_ID_SERVERWORKS_CSB5IDE
) ||
250 (dev
->device
== PCI_DEVICE_ID_SERVERWORKS_CSB6IDE
) ||
251 (dev
->device
== PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2
)) {
253 /* Third Channel Test */
254 if (!(PCI_FUNC(dev
->devfn
) & 1)) {
255 struct pci_dev
* findev
= NULL
;
257 findev
= pci_get_device(PCI_VENDOR_ID_SERVERWORKS
,
258 PCI_DEVICE_ID_SERVERWORKS_CSB5
, NULL
);
260 pci_read_config_dword(findev
, 0x4C, ®4c
);
261 reg4c
&= ~0x000007FF;
264 pci_write_config_dword(findev
, 0x4C, reg4c
);
267 outb_p(0x06, 0x0c00);
268 dev
->irq
= inb_p(0x0c01);
270 struct pci_dev
* findev
= NULL
;
273 findev
= pci_get_device(PCI_VENDOR_ID_SERVERWORKS
,
274 PCI_DEVICE_ID_SERVERWORKS_CSB6
, NULL
);
276 pci_read_config_byte(findev
, 0x41, ®41
);
278 pci_write_config_byte(findev
, 0x41, reg41
);
282 * This is a device pin issue on CSB6.
283 * Since there will be a future raid mode,
284 * early versions of the chipset require the
285 * interrupt pin to be set, and it is a compatibility
288 if ((dev
->class >> 8) == PCI_CLASS_STORAGE_IDE
)
291 // pci_read_config_dword(dev, 0x40, &pioreg)
292 // pci_write_config_dword(dev, 0x40, 0x99999999);
293 // pci_read_config_dword(dev, 0x44, &dmareg);
294 // pci_write_config_dword(dev, 0x44, 0xFFFFFFFF);
295 /* setup the UDMA Control register
297 * 1. clear bit 6 to enable DMA
298 * 2. enable DMA modes with bits 0-1
302 * 11 : udma2/udma4/udma5
304 pci_read_config_byte(dev
, 0x5A, &btr
);
306 if (!(PCI_FUNC(dev
->devfn
) & 1))
309 btr
|= (dev
->revision
>= SVWKS_CSB5_REVISION_NEW
) ? 0x3 : 0x2;
310 pci_write_config_byte(dev
, 0x5A, btr
);
312 /* Setup HT1000 SouthBridge Controller - Single Channel Only */
313 else if (dev
->device
== PCI_DEVICE_ID_SERVERWORKS_HT1000IDE
) {
314 pci_read_config_byte(dev
, 0x5A, &btr
);
317 pci_write_config_byte(dev
, 0x5A, btr
);
323 static u8 __devinit
ata66_svwks_svwks(ide_hwif_t
*hwif
)
325 return ATA_CBL_PATA80
;
328 /* On Dell PowerEdge servers with a CSB5/CSB6, the top two bits
329 * of the subsystem device ID indicate presence of an 80-pin cable.
330 * Bit 15 clear = secondary IDE channel does not have 80-pin cable.
331 * Bit 15 set = secondary IDE channel has 80-pin cable.
332 * Bit 14 clear = primary IDE channel does not have 80-pin cable.
333 * Bit 14 set = primary IDE channel has 80-pin cable.
335 static u8 __devinit
ata66_svwks_dell(ide_hwif_t
*hwif
)
337 struct pci_dev
*dev
= hwif
->pci_dev
;
338 if (dev
->subsystem_vendor
== PCI_VENDOR_ID_DELL
&&
339 dev
->vendor
== PCI_VENDOR_ID_SERVERWORKS
&&
340 (dev
->device
== PCI_DEVICE_ID_SERVERWORKS_CSB5IDE
||
341 dev
->device
== PCI_DEVICE_ID_SERVERWORKS_CSB6IDE
))
342 return ((1 << (hwif
->channel
+ 14)) &
343 dev
->subsystem_device
) ? ATA_CBL_PATA80
: ATA_CBL_PATA40
;
344 return ATA_CBL_PATA40
;
347 /* Sun Cobalt Alpine hardware avoids the 80-pin cable
348 * detect issue by attaching the drives directly to the board.
349 * This check follows the Dell precedent (how scary is that?!)
351 * WARNING: this only works on Alpine hardware!
353 static u8 __devinit
ata66_svwks_cobalt(ide_hwif_t
*hwif
)
355 struct pci_dev
*dev
= hwif
->pci_dev
;
356 if (dev
->subsystem_vendor
== PCI_VENDOR_ID_SUN
&&
357 dev
->vendor
== PCI_VENDOR_ID_SERVERWORKS
&&
358 dev
->device
== PCI_DEVICE_ID_SERVERWORKS_CSB5IDE
)
359 return ((1 << (hwif
->channel
+ 14)) &
360 dev
->subsystem_device
) ? ATA_CBL_PATA80
: ATA_CBL_PATA40
;
361 return ATA_CBL_PATA40
;
364 static u8 __devinit
ata66_svwks(ide_hwif_t
*hwif
)
366 struct pci_dev
*dev
= hwif
->pci_dev
;
369 if (dev
->subsystem_vendor
== PCI_VENDOR_ID_SERVERWORKS
)
370 return ata66_svwks_svwks (hwif
);
373 if (dev
->subsystem_vendor
== PCI_VENDOR_ID_DELL
)
374 return ata66_svwks_dell (hwif
);
377 if (dev
->subsystem_vendor
== PCI_VENDOR_ID_SUN
)
378 return ata66_svwks_cobalt (hwif
);
380 /* Per Specified Design by OEM, and ASIC Architect */
381 if ((dev
->device
== PCI_DEVICE_ID_SERVERWORKS_CSB6IDE
) ||
382 (dev
->device
== PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2
))
383 return ATA_CBL_PATA80
;
385 return ATA_CBL_PATA40
;
388 static void __devinit
init_hwif_svwks (ide_hwif_t
*hwif
)
391 hwif
->irq
= hwif
->channel
? 15 : 14;
393 hwif
->tuneproc
= &svwks_tune_drive
;
394 hwif
->speedproc
= &svwks_tune_chipset
;
395 hwif
->udma_filter
= &svwks_udma_filter
;
399 if (hwif
->pci_dev
->device
!= PCI_DEVICE_ID_SERVERWORKS_OSB4IDE
)
400 hwif
->ultra_mask
= 0x3f;
402 hwif
->mwdma_mask
= 0x07;
406 hwif
->drives
[0].autotune
= 1;
407 hwif
->drives
[1].autotune
= 1;
412 hwif
->ide_dma_check
= &svwks_config_drive_xfer_rate
;
413 if (hwif
->pci_dev
->device
!= PCI_DEVICE_ID_SERVERWORKS_OSB4IDE
) {
414 if (hwif
->cbl
!= ATA_CBL_PATA40_SHORT
)
415 hwif
->cbl
= ata66_svwks(hwif
);
420 hwif
->drives
[0].autodma
= hwif
->drives
[1].autodma
= 1;
423 static int __devinit
init_setup_svwks (struct pci_dev
*dev
, ide_pci_device_t
*d
)
425 return ide_setup_pci_device(dev
, d
);
428 static int __devinit
init_setup_csb6 (struct pci_dev
*dev
, ide_pci_device_t
*d
)
430 if (!(PCI_FUNC(dev
->devfn
) & 1)) {
431 d
->bootable
= NEVER_BOARD
;
432 if (dev
->resource
[0].start
== 0x01f1)
433 d
->bootable
= ON_BOARD
;
436 if ((dev
->device
== PCI_DEVICE_ID_SERVERWORKS_CSB6IDE
||
437 dev
->device
== PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2
) &&
438 (!(PCI_FUNC(dev
->devfn
) & 1)))
439 d
->host_flags
|= IDE_HFLAG_SINGLE
;
441 d
->host_flags
&= ~IDE_HFLAG_SINGLE
;
443 return ide_setup_pci_device(dev
, d
);
446 static ide_pci_device_t serverworks_chipsets
[] __devinitdata
= {
448 .name
= "SvrWks OSB4",
449 .init_setup
= init_setup_svwks
,
450 .init_chipset
= init_chipset_svwks
,
451 .init_hwif
= init_hwif_svwks
,
453 .bootable
= ON_BOARD
,
454 .pio_mask
= ATA_PIO4
,
456 .name
= "SvrWks CSB5",
457 .init_setup
= init_setup_svwks
,
458 .init_chipset
= init_chipset_svwks
,
459 .init_hwif
= init_hwif_svwks
,
461 .bootable
= ON_BOARD
,
462 .pio_mask
= ATA_PIO4
,
464 .name
= "SvrWks CSB6",
465 .init_setup
= init_setup_csb6
,
466 .init_chipset
= init_chipset_svwks
,
467 .init_hwif
= init_hwif_svwks
,
469 .bootable
= ON_BOARD
,
470 .pio_mask
= ATA_PIO4
,
472 .name
= "SvrWks CSB6",
473 .init_setup
= init_setup_csb6
,
474 .init_chipset
= init_chipset_svwks
,
475 .init_hwif
= init_hwif_svwks
,
477 .bootable
= ON_BOARD
,
478 .host_flags
= IDE_HFLAG_SINGLE
,
479 .pio_mask
= ATA_PIO4
,
481 .name
= "SvrWks HT1000",
482 .init_setup
= init_setup_svwks
,
483 .init_chipset
= init_chipset_svwks
,
484 .init_hwif
= init_hwif_svwks
,
486 .bootable
= ON_BOARD
,
487 .host_flags
= IDE_HFLAG_SINGLE
,
488 .pio_mask
= ATA_PIO4
,
493 * svwks_init_one - called when a OSB/CSB is found
494 * @dev: the svwks device
495 * @id: the matching pci id
497 * Called when the PCI registration layer (or the IDE initialization)
498 * finds a device matching our IDE device tables.
501 static int __devinit
svwks_init_one(struct pci_dev
*dev
, const struct pci_device_id
*id
)
503 ide_pci_device_t
*d
= &serverworks_chipsets
[id
->driver_data
];
505 return d
->init_setup(dev
, d
);
508 static struct pci_device_id svwks_pci_tbl
[] = {
509 { PCI_VENDOR_ID_SERVERWORKS
, PCI_DEVICE_ID_SERVERWORKS_OSB4IDE
, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0},
510 { PCI_VENDOR_ID_SERVERWORKS
, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE
, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 1},
511 { PCI_VENDOR_ID_SERVERWORKS
, PCI_DEVICE_ID_SERVERWORKS_CSB6IDE
, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 2},
512 { PCI_VENDOR_ID_SERVERWORKS
, PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2
, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 3},
513 { PCI_VENDOR_ID_SERVERWORKS
, PCI_DEVICE_ID_SERVERWORKS_HT1000IDE
, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 4},
516 MODULE_DEVICE_TABLE(pci
, svwks_pci_tbl
);
518 static struct pci_driver driver
= {
519 .name
= "Serverworks_IDE",
520 .id_table
= svwks_pci_tbl
,
521 .probe
= svwks_init_one
,
524 static int __init
svwks_ide_init(void)
526 return ide_pci_register_driver(&driver
);
529 module_init(svwks_ide_init
);
531 MODULE_AUTHOR("Michael Aubry. Andrzej Krzysztofowicz, Andre Hedrick");
532 MODULE_DESCRIPTION("PCI driver module for Serverworks OSB4/CSB5/CSB6 IDE");
533 MODULE_LICENSE("GPL");