2 * linux/drivers/ide/pci/siimage.c Version 1.07 Nov 30, 2003
4 * Copyright (C) 2001-2002 Andre Hedrick <andre@linux-ide.org>
5 * Copyright (C) 2003 Red Hat <alan@redhat.com>
7 * May be copied or modified under the terms of the GNU General Public License
9 * Documentation for CMD680:
10 * http://gkernel.sourceforge.net/specs/sii/sii-0680a-v1.31.pdf.bz2
12 * Documentation for SiI 3112:
13 * http://gkernel.sourceforge.net/specs/sii/3112A_SiI-DS-0095-B2.pdf.bz2
15 * Errata and other documentation only available under NDA.
19 * If you are using Marvell SATA-IDE adapters with Maxtor drives
20 * ensure the system is set up for ATA100/UDMA5 not UDMA6.
22 * If you are using WD drives with SATA bridges you must set the
23 * drive to "Single". "Master" will hang
25 * If you have strange problems with nVidia chipset systems please
26 * see the SI support documentation and update your system BIOS
30 #include <linux/types.h>
31 #include <linux/module.h>
32 #include <linux/pci.h>
33 #include <linux/delay.h>
34 #include <linux/hdreg.h>
35 #include <linux/ide.h>
36 #include <linux/init.h>
41 * pdev_is_sata - check if device is SATA
42 * @pdev: PCI device to check
44 * Returns true if this is a SATA controller
47 static int pdev_is_sata(struct pci_dev
*pdev
)
51 case PCI_DEVICE_ID_SII_3112
:
52 case PCI_DEVICE_ID_SII_1210SA
:
54 case PCI_DEVICE_ID_SII_680
:
62 * is_sata - check if hwif is SATA
63 * @hwif: interface to check
65 * Returns true if this is a SATA controller
68 static inline int is_sata(ide_hwif_t
*hwif
)
70 return pdev_is_sata(hwif
->pci_dev
);
74 * siimage_selreg - return register base
78 * Turn a config register offset into the right address in either
79 * PCI space or MMIO space to access the control register in question
80 * Thankfully this is a configuration operation so isnt performance
84 static unsigned long siimage_selreg(ide_hwif_t
*hwif
, int r
)
86 unsigned long base
= (unsigned long)hwif
->hwif_data
;
89 base
+= (hwif
->channel
<< 6);
91 base
+= (hwif
->channel
<< 4);
96 * siimage_seldev - return register base
100 * Turn a config register offset into the right address in either
101 * PCI space or MMIO space to access the control register in question
102 * including accounting for the unit shift.
105 static inline unsigned long siimage_seldev(ide_drive_t
*drive
, int r
)
107 ide_hwif_t
*hwif
= HWIF(drive
);
108 unsigned long base
= (unsigned long)hwif
->hwif_data
;
111 base
+= (hwif
->channel
<< 6);
113 base
+= (hwif
->channel
<< 4);
114 base
|= drive
->select
.b
.unit
<< drive
->select
.b
.unit
;
119 * siimage_ratemask - Compute available modes
122 * Compute the available speeds for the devices on the interface.
123 * For the CMD680 this depends on the clocking mode (scsc), for the
124 * SI3312 SATA controller life is a bit simpler. Enforce UDMA33
125 * as a limit if there is no 80pin cable present.
128 static byte
siimage_ratemask (ide_drive_t
*drive
)
130 ide_hwif_t
*hwif
= HWIF(drive
);
131 u8 mode
= 0, scsc
= 0;
132 unsigned long base
= (unsigned long) hwif
->hwif_data
;
135 scsc
= hwif
->INB(base
+ 0x4A);
137 pci_read_config_byte(hwif
->pci_dev
, 0x8A, &scsc
);
141 if(strstr(drive
->id
->model
, "Maxtor"))
146 if ((scsc
& 0x30) == 0x10) /* 133 */
148 else if ((scsc
& 0x30) == 0x20) /* 2xPCI */
150 else if ((scsc
& 0x30) == 0x00) /* 100 */
152 else /* Disabled ? */
155 if (!eighty_ninty_three(drive
))
156 mode
= min(mode
, (u8
)1);
161 * siimage_taskfile_timing - turn timing data to a mode
162 * @hwif: interface to query
164 * Read the timing data for the interface and return the
165 * mode that is being used.
168 static byte
siimage_taskfile_timing (ide_hwif_t
*hwif
)
171 unsigned long addr
= siimage_selreg(hwif
, 2);
174 timing
= hwif
->INW(addr
);
176 pci_read_config_word(hwif
->pci_dev
, addr
, &timing
);
179 case 0x10c1: return 4;
180 case 0x10c3: return 3;
182 case 0x1281: return 2;
183 case 0x2283: return 1;
190 * simmage_tuneproc - tune a drive
191 * @drive: drive to tune
192 * @mode_wanted: the target operating mode
194 * Load the timing settings for this device mode into the
195 * controller. If we are in PIO mode 3 or 4 turn on IORDY
196 * monitoring (bit 9). The TF timing is bits 31:16
199 static void siimage_tuneproc (ide_drive_t
*drive
, byte mode_wanted
)
201 ide_hwif_t
*hwif
= HWIF(drive
);
204 unsigned long addr
= siimage_seldev(drive
, 0x04);
205 unsigned long tfaddr
= siimage_selreg(hwif
, 0x02);
207 /* cheat for now and use the docs */
208 switch(mode_wanted
) {
233 hwif
->OUTW(speedt
, addr
);
234 hwif
->OUTW(speedp
, tfaddr
);
235 /* Now set up IORDY */
236 if(mode_wanted
== 3 || mode_wanted
== 4)
237 hwif
->OUTW(hwif
->INW(tfaddr
-2)|0x200, tfaddr
-2);
239 hwif
->OUTW(hwif
->INW(tfaddr
-2)&~0x200, tfaddr
-2);
243 pci_write_config_word(hwif
->pci_dev
, addr
, speedp
);
244 pci_write_config_word(hwif
->pci_dev
, tfaddr
, speedt
);
245 pci_read_config_word(hwif
->pci_dev
, tfaddr
-2, &speedp
);
247 /* Set IORDY for mode 3 or 4 */
248 if(mode_wanted
== 3 || mode_wanted
== 4)
250 pci_write_config_word(hwif
->pci_dev
, tfaddr
-2, speedp
);
255 * config_siimage_chipset_for_pio - set drive timings
256 * @drive: drive to tune
259 * Compute the best pio mode we can for a given device. Also honour
260 * the timings for the driver when dealing with mixed devices. Some
261 * of this is ugly but its all wrapped up here
263 * The SI680 can also do VDMA - we need to start using that
265 * FIXME: we use the BIOS channel timings to avoid driving the task
266 * files too fast at the disk. We need to compute the master/slave
267 * drive PIO mode properly so that we can up the speed on a hotplug
271 static void config_siimage_chipset_for_pio (ide_drive_t
*drive
, byte set_speed
)
273 u8 channel_timings
= siimage_taskfile_timing(HWIF(drive
));
274 u8 speed
= 0, set_pio
= ide_get_best_pio_mode(drive
, 4, 5, NULL
);
276 /* WARNING PIO timing mess is going to happen b/w devices, argh */
277 if ((channel_timings
!= set_pio
) && (set_pio
> channel_timings
))
278 set_pio
= channel_timings
;
280 siimage_tuneproc(drive
, set_pio
);
281 speed
= XFER_PIO_0
+ set_pio
;
283 (void) ide_config_drive_speed(drive
, speed
);
286 static void config_chipset_for_pio (ide_drive_t
*drive
, byte set_speed
)
288 config_siimage_chipset_for_pio(drive
, set_speed
);
292 * siimage_tune_chipset - set controller timings
293 * @drive: Drive to set up
294 * @xferspeed: speed we want to achieve
296 * Tune the SII chipset for the desired mode. If we can't achieve
297 * the desired mode then tune for a lower one, but ultimately
298 * make the thing work.
301 static int siimage_tune_chipset (ide_drive_t
*drive
, byte xferspeed
)
303 u8 ultra6
[] = { 0x0F, 0x0B, 0x07, 0x05, 0x03, 0x02, 0x01 };
304 u8 ultra5
[] = { 0x0C, 0x07, 0x05, 0x04, 0x02, 0x01 };
305 u16 dma
[] = { 0x2208, 0x10C2, 0x10C1 };
307 ide_hwif_t
*hwif
= HWIF(drive
);
308 u16 ultra
= 0, multi
= 0;
309 u8 mode
= 0, unit
= drive
->select
.b
.unit
;
310 u8 speed
= ide_rate_filter(siimage_ratemask(drive
), xferspeed
);
311 unsigned long base
= (unsigned long)hwif
->hwif_data
;
312 u8 scsc
= 0, addr_mask
= ((hwif
->channel
) ?
313 ((hwif
->mmio
) ? 0xF4 : 0x84) :
314 ((hwif
->mmio
) ? 0xB4 : 0x80));
316 unsigned long ma
= siimage_seldev(drive
, 0x08);
317 unsigned long ua
= siimage_seldev(drive
, 0x0C);
320 scsc
= hwif
->INB(base
+ 0x4A);
321 mode
= hwif
->INB(base
+ addr_mask
);
322 multi
= hwif
->INW(ma
);
323 ultra
= hwif
->INW(ua
);
325 pci_read_config_byte(hwif
->pci_dev
, 0x8A, &scsc
);
326 pci_read_config_byte(hwif
->pci_dev
, addr_mask
, &mode
);
327 pci_read_config_word(hwif
->pci_dev
, ma
, &multi
);
328 pci_read_config_word(hwif
->pci_dev
, ua
, &ultra
);
331 mode
&= ~((unit
) ? 0x30 : 0x03);
333 scsc
= ((scsc
& 0x30) == 0x00) ? 0 : 1;
335 scsc
= is_sata(hwif
) ? 1 : scsc
;
343 siimage_tuneproc(drive
, (speed
- XFER_PIO_0
));
344 mode
|= ((unit
) ? 0x10 : 0x01);
349 multi
= dma
[speed
- XFER_MW_DMA_0
];
350 mode
|= ((unit
) ? 0x20 : 0x02);
351 config_siimage_chipset_for_pio(drive
, 0);
361 ultra
|= ((scsc
) ? (ultra6
[speed
- XFER_UDMA_0
]) :
362 (ultra5
[speed
- XFER_UDMA_0
]));
363 mode
|= ((unit
) ? 0x30 : 0x03);
364 config_siimage_chipset_for_pio(drive
, 0);
371 hwif
->OUTB(mode
, base
+ addr_mask
);
372 hwif
->OUTW(multi
, ma
);
373 hwif
->OUTW(ultra
, ua
);
375 pci_write_config_byte(hwif
->pci_dev
, addr_mask
, mode
);
376 pci_write_config_word(hwif
->pci_dev
, ma
, multi
);
377 pci_write_config_word(hwif
->pci_dev
, ua
, ultra
);
379 return (ide_config_drive_speed(drive
, speed
));
383 * config_chipset_for_dma - configure for DMA
384 * @drive: drive to configure
386 * Called by the IDE layer when it wants the timings set up.
387 * For the CMD680 we also need to set up the PIO timings and
391 static int config_chipset_for_dma (ide_drive_t
*drive
)
393 u8 speed
= ide_dma_speed(drive
, siimage_ratemask(drive
));
395 config_chipset_for_pio(drive
, !speed
);
400 if (ide_set_xfer_rate(drive
, speed
))
403 if (!drive
->init_speed
)
404 drive
->init_speed
= speed
;
406 return ide_dma_enable(drive
);
410 * siimage_configure_drive_for_dma - set up for DMA transfers
411 * @drive: drive we are going to set up
413 * Set up the drive for DMA, tune the controller and drive as
414 * required. If the drive isn't suitable for DMA or we hit
415 * other problems then we will drop down to PIO and set up
419 static int siimage_config_drive_for_dma (ide_drive_t
*drive
)
421 ide_hwif_t
*hwif
= HWIF(drive
);
422 struct hd_driveid
*id
= drive
->id
;
424 if ((id
->capability
& 1) != 0 && drive
->autodma
) {
426 if (ide_use_dma(drive
)) {
427 if (config_chipset_for_dma(drive
))
428 return hwif
->ide_dma_on(drive
);
433 } else if ((id
->capability
& 8) || (id
->field_valid
& 2)) {
435 config_chipset_for_pio(drive
, 1);
436 return hwif
->ide_dma_off_quietly(drive
);
438 /* IORDY not supported */
442 /* returns 1 if dma irq issued, 0 otherwise */
443 static int siimage_io_ide_dma_test_irq (ide_drive_t
*drive
)
445 ide_hwif_t
*hwif
= HWIF(drive
);
447 unsigned long addr
= siimage_selreg(hwif
, 1);
449 /* return 1 if INTR asserted */
450 if ((hwif
->INB(hwif
->dma_status
) & 4) == 4)
453 /* return 1 if Device INTR asserted */
454 pci_read_config_byte(hwif
->pci_dev
, addr
, &dma_altstat
);
456 return 0; //return 1;
461 * siimage_mmio_ide_dma_test_irq - check we caused an IRQ
462 * @drive: drive we are testing
464 * Check if we caused an IDE DMA interrupt. We may also have caused
465 * SATA status interrupts, if so we clean them up and continue.
468 static int siimage_mmio_ide_dma_test_irq (ide_drive_t
*drive
)
470 ide_hwif_t
*hwif
= HWIF(drive
);
471 unsigned long base
= (unsigned long)hwif
->hwif_data
;
472 unsigned long addr
= siimage_selreg(hwif
, 0x1);
474 if (SATA_ERROR_REG
) {
475 u32 ext_stat
= hwif
->INL(base
+ 0x10);
477 if (ext_stat
& ((hwif
->channel
) ? 0x40 : 0x10)) {
478 u32 sata_error
= hwif
->INL(SATA_ERROR_REG
);
479 hwif
->OUTL(sata_error
, SATA_ERROR_REG
);
480 watchdog
= (sata_error
& 0x00680000) ? 1 : 0;
481 printk(KERN_WARNING
"%s: sata_error = 0x%08x, "
482 "watchdog = %d, %s\n",
483 drive
->name
, sata_error
, watchdog
,
487 watchdog
= (ext_stat
& 0x8000) ? 1 : 0;
491 if (!(ext_stat
& 0x0404) && !watchdog
)
495 /* return 1 if INTR asserted */
496 if ((hwif
->INB(hwif
->dma_status
) & 0x04) == 0x04)
499 /* return 1 if Device INTR asserted */
500 if ((hwif
->INB(addr
) & 8) == 8)
501 return 0; //return 1;
507 * siimage_busproc - bus isolation ioctl
508 * @drive: drive to isolate/restore
509 * @state: bus state to set
511 * Used by the SII3112 to handle bus isolation. As this is a
512 * SATA controller the work required is quite limited, we
513 * just have to clean up the statistics
516 static int siimage_busproc (ide_drive_t
* drive
, int state
)
518 ide_hwif_t
*hwif
= HWIF(drive
);
520 unsigned long addr
= siimage_selreg(hwif
, 0);
523 stat_config
= hwif
->INL(addr
);
525 pci_read_config_dword(hwif
->pci_dev
, addr
, &stat_config
);
529 hwif
->drives
[0].failures
= 0;
530 hwif
->drives
[1].failures
= 0;
533 hwif
->drives
[0].failures
= hwif
->drives
[0].max_failures
+ 1;
534 hwif
->drives
[1].failures
= hwif
->drives
[1].max_failures
+ 1;
536 case BUSSTATE_TRISTATE
:
537 hwif
->drives
[0].failures
= hwif
->drives
[0].max_failures
+ 1;
538 hwif
->drives
[1].failures
= hwif
->drives
[1].max_failures
+ 1;
543 hwif
->bus_state
= state
;
548 * siimage_reset_poll - wait for sata reset
549 * @drive: drive we are resetting
551 * Poll the SATA phy and see whether it has come back from the dead
555 static int siimage_reset_poll (ide_drive_t
*drive
)
557 if (SATA_STATUS_REG
) {
558 ide_hwif_t
*hwif
= HWIF(drive
);
560 if ((hwif
->INL(SATA_STATUS_REG
) & 0x03) != 0x03) {
561 printk(KERN_WARNING
"%s: reset phy dead, status=0x%08x\n",
562 hwif
->name
, hwif
->INL(SATA_STATUS_REG
));
563 HWGROUP(drive
)->polling
= 0;
573 * siimage_pre_reset - reset hook
574 * @drive: IDE device being reset
576 * For the SATA devices we need to handle recalibration/geometry
580 static void siimage_pre_reset (ide_drive_t
*drive
)
582 if (drive
->media
!= ide_disk
)
585 if (is_sata(HWIF(drive
)))
587 drive
->special
.b
.set_geometry
= 0;
588 drive
->special
.b
.recalibrate
= 0;
593 * siimage_reset - reset a device on an siimage controller
594 * @drive: drive to reset
596 * Perform a controller level reset fo the device. For
597 * SATA we must also check the PHY.
600 static void siimage_reset (ide_drive_t
*drive
)
602 ide_hwif_t
*hwif
= HWIF(drive
);
604 unsigned long addr
= siimage_selreg(hwif
, 0);
607 reset
= hwif
->INB(addr
);
608 hwif
->OUTB((reset
|0x03), addr
);
611 hwif
->OUTB(reset
, addr
);
612 (void) hwif
->INB(addr
);
614 pci_read_config_byte(hwif
->pci_dev
, addr
, &reset
);
615 pci_write_config_byte(hwif
->pci_dev
, addr
, reset
|0x03);
617 pci_write_config_byte(hwif
->pci_dev
, addr
, reset
);
618 pci_read_config_byte(hwif
->pci_dev
, addr
, &reset
);
621 if (SATA_STATUS_REG
) {
622 u32 sata_stat
= hwif
->INL(SATA_STATUS_REG
);
623 printk(KERN_WARNING
"%s: reset phy, status=0x%08x, %s\n",
624 hwif
->name
, sata_stat
, __FUNCTION__
);
626 printk(KERN_WARNING
"%s: reset phy dead, status=0x%08x\n",
627 hwif
->name
, sata_stat
);
635 * proc_reports_siimage - add siimage controller to proc
637 * @clocking: SCSC value
638 * @name: controller name
640 * Report the clocking mode of the controller and add it to
641 * the /proc interface layer
644 static void proc_reports_siimage (struct pci_dev
*dev
, u8 clocking
, const char *name
)
646 if (!pdev_is_sata(dev
)) {
647 printk(KERN_INFO
"%s: BASE CLOCK ", name
);
650 case 0x03: printk("DISABLED!\n"); break;
651 case 0x02: printk("== 2X PCI\n"); break;
652 case 0x01: printk("== 133\n"); break;
653 case 0x00: printk("== 100\n"); break;
659 * setup_mmio_siimage - switch an SI controller into MMIO
660 * @dev: PCI device we are configuring
663 * Attempt to put the device into mmio mode. There are some slight
664 * complications here with certain systems where the mmio bar isnt
665 * mapped so we have to be sure we can fall back to I/O.
668 static unsigned int setup_mmio_siimage (struct pci_dev
*dev
, const char *name
)
670 unsigned long bar5
= pci_resource_start(dev
, 5);
671 unsigned long barsize
= pci_resource_len(dev
, 5);
673 void __iomem
*ioaddr
;
677 * Drop back to PIO if we can't map the mmio. Some
678 * systems seem to get terminally confused in the PCI
682 if(!request_mem_region(bar5
, barsize
, name
))
684 printk(KERN_WARNING
"siimage: IDE controller MMIO ports not available.\n");
688 ioaddr
= ioremap(bar5
, barsize
);
692 release_mem_region(bar5
, barsize
);
697 pci_set_drvdata(dev
, (void *) ioaddr
);
699 if (pdev_is_sata(dev
)) {
700 /* make sure IDE0/1 interrupts are not masked */
701 irq_mask
= (1 << 22) | (1 << 23);
702 tmp
= readl(ioaddr
+ 0x48);
703 if (tmp
& irq_mask
) {
705 writel(tmp
, ioaddr
+ 0x48);
706 readl(ioaddr
+ 0x48); /* flush */
708 writel(0, ioaddr
+ 0x148);
709 writel(0, ioaddr
+ 0x1C8);
712 writeb(0, ioaddr
+ 0xB4);
713 writeb(0, ioaddr
+ 0xF4);
714 tmpbyte
= readb(ioaddr
+ 0x4A);
716 switch(tmpbyte
& 0x30) {
718 /* In 100 MHz clocking, try and switch to 133 */
719 writeb(tmpbyte
|0x10, ioaddr
+ 0x4A);
722 /* On 133Mhz clocking */
725 /* On PCIx2 clocking */
728 /* Clocking is disabled */
729 /* 133 clock attempt to force it on */
730 writeb(tmpbyte
& ~0x20, ioaddr
+ 0x4A);
734 writeb( 0x72, ioaddr
+ 0xA1);
735 writew( 0x328A, ioaddr
+ 0xA2);
736 writel(0x62DD62DD, ioaddr
+ 0xA4);
737 writel(0x43924392, ioaddr
+ 0xA8);
738 writel(0x40094009, ioaddr
+ 0xAC);
739 writeb( 0x72, ioaddr
+ 0xE1);
740 writew( 0x328A, ioaddr
+ 0xE2);
741 writel(0x62DD62DD, ioaddr
+ 0xE4);
742 writel(0x43924392, ioaddr
+ 0xE8);
743 writel(0x40094009, ioaddr
+ 0xEC);
745 if (pdev_is_sata(dev
)) {
746 writel(0xFFFF0000, ioaddr
+ 0x108);
747 writel(0xFFFF0000, ioaddr
+ 0x188);
748 writel(0x00680000, ioaddr
+ 0x148);
749 writel(0x00680000, ioaddr
+ 0x1C8);
752 tmpbyte
= readb(ioaddr
+ 0x4A);
754 proc_reports_siimage(dev
, (tmpbyte
>>4), name
);
759 * init_chipset_siimage - set up an SI device
763 * Perform the initial PCI set up for this device. Attempt to switch
764 * to 133MHz clocking if the system isn't already set up to do it.
767 static unsigned int __devinit
init_chipset_siimage(struct pci_dev
*dev
, const char *name
)
773 pci_read_config_dword(dev
, PCI_CLASS_REVISION
, &class_rev
);
775 pci_write_config_byte(dev
, PCI_CACHE_LINE_SIZE
, (class_rev
) ? 1 : 255);
777 pci_read_config_byte(dev
, 0x8A, &BA5_EN
);
778 if ((BA5_EN
& 0x01) || (pci_resource_start(dev
, 5))) {
779 if (setup_mmio_siimage(dev
, name
)) {
784 pci_write_config_byte(dev
, 0x80, 0x00);
785 pci_write_config_byte(dev
, 0x84, 0x00);
786 pci_read_config_byte(dev
, 0x8A, &tmpbyte
);
787 switch(tmpbyte
& 0x30) {
789 /* 133 clock attempt to force it on */
790 pci_write_config_byte(dev
, 0x8A, tmpbyte
|0x10);
792 /* if clocking is disabled */
793 /* 133 clock attempt to force it on */
794 pci_write_config_byte(dev
, 0x8A, tmpbyte
& ~0x20);
799 /* BIOS set PCI x2 clocking */
803 pci_read_config_byte(dev
, 0x8A, &tmpbyte
);
805 pci_write_config_byte(dev
, 0xA1, 0x72);
806 pci_write_config_word(dev
, 0xA2, 0x328A);
807 pci_write_config_dword(dev
, 0xA4, 0x62DD62DD);
808 pci_write_config_dword(dev
, 0xA8, 0x43924392);
809 pci_write_config_dword(dev
, 0xAC, 0x40094009);
810 pci_write_config_byte(dev
, 0xB1, 0x72);
811 pci_write_config_word(dev
, 0xB2, 0x328A);
812 pci_write_config_dword(dev
, 0xB4, 0x62DD62DD);
813 pci_write_config_dword(dev
, 0xB8, 0x43924392);
814 pci_write_config_dword(dev
, 0xBC, 0x40094009);
816 proc_reports_siimage(dev
, (tmpbyte
>>4), name
);
821 * init_mmio_iops_siimage - set up the iops for MMIO
822 * @hwif: interface to set up
824 * The basic setup here is fairly simple, we can use standard MMIO
825 * operations. However we do have to set the taskfile register offsets
826 * by hand as there isnt a standard defined layout for them this
829 * The hardware supports buffered taskfiles and also some rather nice
830 * extended PRD tables. For better SI3112 support use the libata driver
833 static void __devinit
init_mmio_iops_siimage(ide_hwif_t
*hwif
)
835 struct pci_dev
*dev
= hwif
->pci_dev
;
836 void *addr
= pci_get_drvdata(dev
);
837 u8 ch
= hwif
->channel
;
842 * Fill in the basic HWIF bits
845 default_hwif_mmiops(hwif
);
846 hwif
->hwif_data
= addr
;
849 * Now set up the hw. We have to do this ourselves as
850 * the MMIO layout isnt the same as the the standard port
854 memset(&hw
, 0, sizeof(hw_regs_t
));
856 base
= (unsigned long)addr
;
863 * The buffered task file doesn't have status/control
864 * so we can't currently use it sanely since we want to
867 hw
.io_ports
[IDE_DATA_OFFSET
] = base
;
868 hw
.io_ports
[IDE_ERROR_OFFSET
] = base
+ 1;
869 hw
.io_ports
[IDE_NSECTOR_OFFSET
] = base
+ 2;
870 hw
.io_ports
[IDE_SECTOR_OFFSET
] = base
+ 3;
871 hw
.io_ports
[IDE_LCYL_OFFSET
] = base
+ 4;
872 hw
.io_ports
[IDE_HCYL_OFFSET
] = base
+ 5;
873 hw
.io_ports
[IDE_SELECT_OFFSET
] = base
+ 6;
874 hw
.io_ports
[IDE_STATUS_OFFSET
] = base
+ 7;
875 hw
.io_ports
[IDE_CONTROL_OFFSET
] = base
+ 10;
877 hw
.io_ports
[IDE_IRQ_OFFSET
] = 0;
879 if (pdev_is_sata(dev
)) {
880 base
= (unsigned long)addr
;
883 hwif
->sata_scr
[SATA_STATUS_OFFSET
] = base
+ 0x104;
884 hwif
->sata_scr
[SATA_ERROR_OFFSET
] = base
+ 0x108;
885 hwif
->sata_scr
[SATA_CONTROL_OFFSET
] = base
+ 0x100;
886 hwif
->sata_misc
[SATA_MISC_OFFSET
] = base
+ 0x140;
887 hwif
->sata_misc
[SATA_PHY_OFFSET
] = base
+ 0x144;
888 hwif
->sata_misc
[SATA_IEN_OFFSET
] = base
+ 0x148;
891 hw
.irq
= hwif
->pci_dev
->irq
;
893 memcpy(&hwif
->hw
, &hw
, sizeof(hw
));
894 memcpy(hwif
->io_ports
, hwif
->hw
.io_ports
, sizeof(hwif
->hw
.io_ports
));
898 base
= (unsigned long) addr
;
900 hwif
->dma_base
= base
+ (ch
? 0x08 : 0x00);
901 hwif
->dma_base2
= base
+ (ch
? 0x18 : 0x10);
905 static int is_dev_seagate_sata(ide_drive_t
*drive
)
907 const char *s
= &drive
->id
->model
[0];
913 len
= strnlen(s
, sizeof(drive
->id
->model
));
915 if ((len
> 4) && (!memcmp(s
, "ST", 2))) {
916 if ((!memcmp(s
+ len
- 2, "AS", 2)) ||
917 (!memcmp(s
+ len
- 3, "ASL", 3))) {
918 printk(KERN_INFO
"%s: applying pessimistic Seagate "
919 "errata fix\n", drive
->name
);
927 * siimage_fixup - post probe fixups
928 * @hwif: interface to fix up
930 * Called after drive probe we use this to decide whether the
931 * Seagate fixup must be applied. This used to be in init_iops but
932 * that can occur before we know what drives are present.
935 static void __devinit
siimage_fixup(ide_hwif_t
*hwif
)
937 /* Try and raise the rqsize */
938 if (!is_sata(hwif
) || !is_dev_seagate_sata(&hwif
->drives
[0]))
943 * init_iops_siimage - set up iops
944 * @hwif: interface to set up
946 * Do the basic setup for the SIIMAGE hardware interface
947 * and then do the MMIO setup if we can. This is the first
948 * look in we get for setting up the hwif so that we
949 * can get the iops right before using them.
952 static void __devinit
init_iops_siimage(ide_hwif_t
*hwif
)
954 struct pci_dev
*dev
= hwif
->pci_dev
;
957 pci_read_config_dword(dev
, PCI_CLASS_REVISION
, &class_rev
);
960 hwif
->hwif_data
= NULL
;
962 /* Pessimal until we finish probing */
965 if (pci_get_drvdata(dev
) == NULL
)
967 init_mmio_iops_siimage(hwif
);
971 * ata66_siimage - check for 80 pin cable
972 * @hwif: interface to check
974 * Check for the presence of an ATA66 capable cable on the
978 static unsigned int __devinit
ata66_siimage(ide_hwif_t
*hwif
)
980 unsigned long addr
= siimage_selreg(hwif
, 0);
981 if (pci_get_drvdata(hwif
->pci_dev
) == NULL
) {
983 pci_read_config_byte(hwif
->pci_dev
, addr
, &ata66
);
984 return (ata66
& 0x01) ? 1 : 0;
987 return (hwif
->INB(addr
) & 0x01) ? 1 : 0;
991 * init_hwif_siimage - set up hwif structs
992 * @hwif: interface to set up
994 * We do the basic set up of the interface structure. The SIIMAGE
995 * requires several custom handlers so we override the default
996 * ide DMA handlers appropriately
999 static void __devinit
init_hwif_siimage(ide_hwif_t
*hwif
)
1003 hwif
->resetproc
= &siimage_reset
;
1004 hwif
->speedproc
= &siimage_tune_chipset
;
1005 hwif
->tuneproc
= &siimage_tuneproc
;
1006 hwif
->reset_poll
= &siimage_reset_poll
;
1007 hwif
->pre_reset
= &siimage_pre_reset
;
1010 static int first
= 1;
1012 hwif
->busproc
= &siimage_busproc
;
1015 printk(KERN_INFO
"siimage: For full SATA support you should use the libata sata_sil module.\n");
1019 if (!hwif
->dma_base
) {
1020 hwif
->drives
[0].autotune
= 1;
1021 hwif
->drives
[1].autotune
= 1;
1025 hwif
->ultra_mask
= 0x7f;
1026 hwif
->mwdma_mask
= 0x07;
1027 hwif
->swdma_mask
= 0x07;
1030 hwif
->atapi_dma
= 1;
1032 hwif
->ide_dma_check
= &siimage_config_drive_for_dma
;
1033 if (!(hwif
->udma_four
))
1034 hwif
->udma_four
= ata66_siimage(hwif
);
1037 hwif
->ide_dma_test_irq
= &siimage_mmio_ide_dma_test_irq
;
1039 hwif
->ide_dma_test_irq
= & siimage_io_ide_dma_test_irq
;
1043 * The BIOS often doesn't set up DMA on this controller
1044 * so we always do it.
1048 hwif
->drives
[0].autodma
= hwif
->autodma
;
1049 hwif
->drives
[1].autodma
= hwif
->autodma
;
1052 #define DECLARE_SII_DEV(name_str) \
1055 .init_chipset = init_chipset_siimage, \
1056 .init_iops = init_iops_siimage, \
1057 .init_hwif = init_hwif_siimage, \
1058 .fixup = siimage_fixup, \
1060 .autodma = AUTODMA, \
1061 .bootable = ON_BOARD, \
1064 static ide_pci_device_t siimage_chipsets
[] __devinitdata
= {
1065 /* 0 */ DECLARE_SII_DEV("SiI680"),
1066 /* 1 */ DECLARE_SII_DEV("SiI3112 Serial ATA"),
1067 /* 2 */ DECLARE_SII_DEV("Adaptec AAR-1210SA")
1071 * siimage_init_one - pci layer discovery entry
1073 * @id: ident table entry
1075 * Called by the PCI code when it finds an SI680 or SI3112 controller.
1076 * We then use the IDE PCI generic helper to do most of the work.
1079 static int __devinit
siimage_init_one(struct pci_dev
*dev
, const struct pci_device_id
*id
)
1081 return ide_setup_pci_device(dev
, &siimage_chipsets
[id
->driver_data
]);
1084 static struct pci_device_id siimage_pci_tbl
[] = {
1085 { PCI_VENDOR_ID_CMD
, PCI_DEVICE_ID_SII_680
, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0},
1086 #ifdef CONFIG_BLK_DEV_IDE_SATA
1087 { PCI_VENDOR_ID_CMD
, PCI_DEVICE_ID_SII_3112
, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 1},
1088 { PCI_VENDOR_ID_CMD
, PCI_DEVICE_ID_SII_1210SA
, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 2},
1092 MODULE_DEVICE_TABLE(pci
, siimage_pci_tbl
);
1094 static struct pci_driver driver
= {
1096 .id_table
= siimage_pci_tbl
,
1097 .probe
= siimage_init_one
,
1100 static int siimage_ide_init(void)
1102 return ide_pci_register_driver(&driver
);
1105 module_init(siimage_ide_init
);
1107 MODULE_AUTHOR("Andre Hedrick, Alan Cox");
1108 MODULE_DESCRIPTION("PCI driver module for SiI IDE");
1109 MODULE_LICENSE("GPL");