2 * Copyright (C) 2001-2002 Andre Hedrick <andre@linux-ide.org>
3 * Copyright (C) 2003 Red Hat <alan@redhat.com>
4 * Copyright (C) 2007-2008 MontaVista Software, Inc.
5 * Copyright (C) 2007-2008 Bartlomiej Zolnierkiewicz
7 * May be copied or modified under the terms of the GNU General Public License
9 * Documentation for CMD680:
10 * http://gkernel.sourceforge.net/specs/sii/sii-0680a-v1.31.pdf.bz2
12 * Documentation for SiI 3112:
13 * http://gkernel.sourceforge.net/specs/sii/3112A_SiI-DS-0095-B2.pdf.bz2
15 * Errata and other documentation only available under NDA.
19 * If you are using Marvell SATA-IDE adapters with Maxtor drives
20 * ensure the system is set up for ATA100/UDMA5, not UDMA6.
22 * If you are using WD drives with SATA bridges you must set the
23 * drive to "Single". "Master" will hang.
25 * If you have strange problems with nVidia chipset systems please
26 * see the SI support documentation and update your system BIOS
29 * The Dell DRAC4 has some interesting features including effectively hot
30 * unplugging/replugging the virtual CD interface when the DRAC is reset.
31 * This often causes drivers/ide/siimage to panic but is ok with the rather
32 * smarter code in libata.
39 #include <linux/types.h>
40 #include <linux/module.h>
41 #include <linux/pci.h>
42 #include <linux/hdreg.h>
43 #include <linux/ide.h>
44 #include <linux/init.h>
48 * pdev_is_sata - check if device is SATA
49 * @pdev: PCI device to check
51 * Returns true if this is a SATA controller
54 static int pdev_is_sata(struct pci_dev
*pdev
)
56 #ifdef CONFIG_BLK_DEV_IDE_SATA
57 switch (pdev
->device
) {
58 case PCI_DEVICE_ID_SII_3112
:
59 case PCI_DEVICE_ID_SII_1210SA
:
61 case PCI_DEVICE_ID_SII_680
:
70 * is_sata - check if hwif is SATA
71 * @hwif: interface to check
73 * Returns true if this is a SATA controller
76 static inline int is_sata(ide_hwif_t
*hwif
)
78 return pdev_is_sata(to_pci_dev(hwif
->dev
));
82 * siimage_selreg - return register base
86 * Turn a config register offset into the right address in either
87 * PCI space or MMIO space to access the control register in question
88 * Thankfully this is a configuration operation, so isn't performance
92 static unsigned long siimage_selreg(ide_hwif_t
*hwif
, int r
)
94 unsigned long base
= (unsigned long)hwif
->hwif_data
;
97 if (hwif
->host_flags
& IDE_HFLAG_MMIO
)
98 base
+= hwif
->channel
<< 6;
100 base
+= hwif
->channel
<< 4;
105 * siimage_seldev - return register base
109 * Turn a config register offset into the right address in either
110 * PCI space or MMIO space to access the control register in question
111 * including accounting for the unit shift.
114 static inline unsigned long siimage_seldev(ide_drive_t
*drive
, int r
)
116 ide_hwif_t
*hwif
= HWIF(drive
);
117 unsigned long base
= (unsigned long)hwif
->hwif_data
;
120 if (hwif
->host_flags
& IDE_HFLAG_MMIO
)
121 base
+= hwif
->channel
<< 6;
123 base
+= hwif
->channel
<< 4;
124 base
|= drive
->select
.b
.unit
<< drive
->select
.b
.unit
;
128 static u8
sil_ioread8(struct pci_dev
*dev
, unsigned long addr
)
132 if (pci_get_drvdata(dev
))
133 tmp
= readb((void __iomem
*)addr
);
135 pci_read_config_byte(dev
, addr
, &tmp
);
140 static u16
sil_ioread16(struct pci_dev
*dev
, unsigned long addr
)
144 if (pci_get_drvdata(dev
))
145 tmp
= readw((void __iomem
*)addr
);
147 pci_read_config_word(dev
, addr
, &tmp
);
152 static void sil_iowrite8(struct pci_dev
*dev
, u8 val
, unsigned long addr
)
154 if (pci_get_drvdata(dev
))
155 writeb(val
, (void __iomem
*)addr
);
157 pci_write_config_byte(dev
, addr
, val
);
160 static void sil_iowrite16(struct pci_dev
*dev
, u16 val
, unsigned long addr
)
162 if (pci_get_drvdata(dev
))
163 writew(val
, (void __iomem
*)addr
);
165 pci_write_config_word(dev
, addr
, val
);
168 static void sil_iowrite32(struct pci_dev
*dev
, u32 val
, unsigned long addr
)
170 if (pci_get_drvdata(dev
))
171 writel(val
, (void __iomem
*)addr
);
173 pci_write_config_dword(dev
, addr
, val
);
177 * sil_udma_filter - compute UDMA mask
180 * Compute the available UDMA speeds for the device on the interface.
182 * For the CMD680 this depends on the clocking mode (scsc), for the
183 * SI3112 SATA controller life is a bit simpler.
186 static u8
sil_pata_udma_filter(ide_drive_t
*drive
)
188 ide_hwif_t
*hwif
= drive
->hwif
;
189 struct pci_dev
*dev
= to_pci_dev(hwif
->dev
);
190 unsigned long base
= (unsigned long)hwif
->hwif_data
;
193 base
+= (hwif
->host_flags
& IDE_HFLAG_MMIO
) ? 0x4A : 0x8A;
195 scsc
= sil_ioread8(dev
, base
);
197 switch (scsc
& 0x30) {
201 case 0x20: /* 2xPCI */
207 default: /* Disabled ? */
214 static u8
sil_sata_udma_filter(ide_drive_t
*drive
)
216 return strstr(drive
->id
->model
, "Maxtor") ? ATA_UDMA5
: ATA_UDMA6
;
220 * sil_set_pio_mode - set host controller for PIO mode
222 * @pio: PIO mode number
224 * Load the timing settings for this device mode into the
225 * controller. If we are in PIO mode 3 or 4 turn on IORDY
226 * monitoring (bit 9). The TF timing is bits 31:16
229 static void sil_set_pio_mode(ide_drive_t
*drive
, u8 pio
)
231 static const u16 tf_speed
[] = { 0x328a, 0x2283, 0x1281, 0x10c3, 0x10c1 };
232 static const u16 data_speed
[] = { 0x328a, 0x2283, 0x1104, 0x10c3, 0x10c1 };
234 ide_hwif_t
*hwif
= HWIF(drive
);
235 struct pci_dev
*dev
= to_pci_dev(hwif
->dev
);
236 ide_drive_t
*pair
= ide_get_paired_drive(drive
);
239 unsigned long addr
= siimage_seldev(drive
, 0x04);
240 unsigned long tfaddr
= siimage_selreg(hwif
, 0x02);
241 unsigned long base
= (unsigned long)hwif
->hwif_data
;
243 u8 mmio
= (hwif
->host_flags
& IDE_HFLAG_MMIO
) ? 1 : 0;
244 u8 addr_mask
= hwif
->channel
? (mmio
? 0xF4 : 0x84)
245 : (mmio
? 0xB4 : 0x80);
247 u8 unit
= drive
->select
.b
.unit
;
249 /* trim *taskfile* PIO to the slowest of the master/slave */
251 u8 pair_pio
= ide_get_best_pio_mode(pair
, 255, 4);
253 if (pair_pio
< tf_pio
)
257 /* cheat for now and use the docs */
258 speedp
= data_speed
[pio
];
259 speedt
= tf_speed
[tf_pio
];
261 sil_iowrite16(dev
, speedp
, addr
);
262 sil_iowrite16(dev
, speedt
, tfaddr
);
264 /* now set up IORDY */
265 speedp
= sil_ioread16(dev
, tfaddr
- 2);
269 sil_iowrite16(dev
, speedp
, tfaddr
- 2);
271 mode
= sil_ioread8(dev
, base
+ addr_mask
);
272 mode
&= ~(unit
? 0x30 : 0x03);
273 mode
|= unit
? 0x10 : 0x01;
274 sil_iowrite8(dev
, mode
, base
+ addr_mask
);
278 * sil_set_dma_mode - set host controller for DMA mode
282 * Tune the SiI chipset for the desired DMA mode.
285 static void sil_set_dma_mode(ide_drive_t
*drive
, const u8 speed
)
287 static const u8 ultra6
[] = { 0x0F, 0x0B, 0x07, 0x05, 0x03, 0x02, 0x01 };
288 static const u8 ultra5
[] = { 0x0C, 0x07, 0x05, 0x04, 0x02, 0x01 };
289 static const u16 dma
[] = { 0x2208, 0x10C2, 0x10C1 };
291 ide_hwif_t
*hwif
= HWIF(drive
);
292 struct pci_dev
*dev
= to_pci_dev(hwif
->dev
);
293 u16 ultra
= 0, multi
= 0;
294 u8 mode
= 0, unit
= drive
->select
.b
.unit
;
295 unsigned long base
= (unsigned long)hwif
->hwif_data
;
296 u8 mmio
= (hwif
->host_flags
& IDE_HFLAG_MMIO
) ? 1 : 0;
297 u8 scsc
= 0, addr_mask
= hwif
->channel
? (mmio
? 0xF4 : 0x84)
298 : (mmio
? 0xB4 : 0x80);
299 unsigned long ma
= siimage_seldev(drive
, 0x08);
300 unsigned long ua
= siimage_seldev(drive
, 0x0C);
302 scsc
= sil_ioread8 (dev
, base
+ (mmio
? 0x4A : 0x8A));
303 mode
= sil_ioread8 (dev
, base
+ addr_mask
);
304 multi
= sil_ioread16(dev
, ma
);
305 ultra
= sil_ioread16(dev
, ua
);
307 mode
&= ~(unit
? 0x30 : 0x03);
309 scsc
= ((scsc
& 0x30) == 0x00) ? 0 : 1;
311 scsc
= is_sata(hwif
) ? 1 : scsc
;
313 if (speed
>= XFER_UDMA_0
) {
315 ultra
|= scsc
? ultra6
[speed
- XFER_UDMA_0
] :
316 ultra5
[speed
- XFER_UDMA_0
];
317 mode
|= unit
? 0x30 : 0x03;
319 multi
= dma
[speed
- XFER_MW_DMA_0
];
320 mode
|= unit
? 0x20 : 0x02;
323 sil_iowrite8 (dev
, mode
, base
+ addr_mask
);
324 sil_iowrite16(dev
, multi
, ma
);
325 sil_iowrite16(dev
, ultra
, ua
);
328 /* returns 1 if dma irq issued, 0 otherwise */
329 static int siimage_io_dma_test_irq(ide_drive_t
*drive
)
331 ide_hwif_t
*hwif
= HWIF(drive
);
332 struct pci_dev
*dev
= to_pci_dev(hwif
->dev
);
334 unsigned long addr
= siimage_selreg(hwif
, 1);
336 /* return 1 if INTR asserted */
337 if (hwif
->INB(hwif
->dma_status
) & 4)
340 /* return 1 if Device INTR asserted */
341 pci_read_config_byte(dev
, addr
, &dma_altstat
);
343 return 0; /* return 1; */
349 * siimage_mmio_dma_test_irq - check we caused an IRQ
350 * @drive: drive we are testing
352 * Check if we caused an IDE DMA interrupt. We may also have caused
353 * SATA status interrupts, if so we clean them up and continue.
356 static int siimage_mmio_dma_test_irq(ide_drive_t
*drive
)
358 ide_hwif_t
*hwif
= HWIF(drive
);
359 unsigned long addr
= siimage_selreg(hwif
, 0x1);
360 void __iomem
*sata_error_addr
361 = (void __iomem
*)hwif
->sata_scr
[SATA_ERROR_OFFSET
];
363 if (sata_error_addr
) {
364 unsigned long base
= (unsigned long)hwif
->hwif_data
;
365 u32 ext_stat
= readl((void __iomem
*)(base
+ 0x10));
368 if (ext_stat
& ((hwif
->channel
) ? 0x40 : 0x10)) {
369 u32 sata_error
= readl(sata_error_addr
);
371 writel(sata_error
, sata_error_addr
);
372 watchdog
= (sata_error
& 0x00680000) ? 1 : 0;
373 printk(KERN_WARNING
"%s: sata_error = 0x%08x, "
374 "watchdog = %d, %s\n",
375 drive
->name
, sata_error
, watchdog
, __func__
);
377 watchdog
= (ext_stat
& 0x8000) ? 1 : 0;
380 if (!(ext_stat
& 0x0404) && !watchdog
)
384 /* return 1 if INTR asserted */
385 if (readb((void __iomem
*)hwif
->dma_status
) & 0x04)
388 /* return 1 if Device INTR asserted */
389 if (readb((void __iomem
*)addr
) & 8)
390 return 0; /* return 1; */
395 static int siimage_dma_test_irq(ide_drive_t
*drive
)
397 if (drive
->hwif
->host_flags
& IDE_HFLAG_MMIO
)
398 return siimage_mmio_dma_test_irq(drive
);
400 return siimage_io_dma_test_irq(drive
);
404 * sil_sata_reset_poll - wait for SATA reset
405 * @drive: drive we are resetting
407 * Poll the SATA phy and see whether it has come back from the dead
411 static int sil_sata_reset_poll(ide_drive_t
*drive
)
413 ide_hwif_t
*hwif
= drive
->hwif
;
414 void __iomem
*sata_status_addr
415 = (void __iomem
*)hwif
->sata_scr
[SATA_STATUS_OFFSET
];
417 if (sata_status_addr
) {
418 /* SATA Status is available only when in MMIO mode */
419 u32 sata_stat
= readl(sata_status_addr
);
421 if ((sata_stat
& 0x03) != 0x03) {
422 printk(KERN_WARNING
"%s: reset phy dead, status=0x%08x\n",
423 hwif
->name
, sata_stat
);
432 * sil_sata_pre_reset - reset hook
433 * @drive: IDE device being reset
435 * For the SATA devices we need to handle recalibration/geometry
439 static void sil_sata_pre_reset(ide_drive_t
*drive
)
441 if (drive
->media
== ide_disk
) {
442 drive
->special
.b
.set_geometry
= 0;
443 drive
->special
.b
.recalibrate
= 0;
448 * setup_mmio_siimage - switch controller into MMIO mode
449 * @dev: PCI device we are configuring
452 * Attempt to put the device into MMIO mode. There are some slight
453 * complications here with certain systems where the MMIO BAR isn't
454 * mapped, so we have to be sure that we can fall back to I/O.
457 static unsigned int setup_mmio_siimage(struct pci_dev
*dev
, const char *name
)
459 resource_size_t bar5
= pci_resource_start(dev
, 5);
460 unsigned long barsize
= pci_resource_len(dev
, 5);
461 void __iomem
*ioaddr
;
464 * Drop back to PIO if we can't map the MMIO. Some systems
465 * seem to get terminally confused in the PCI spaces.
467 if (!request_mem_region(bar5
, barsize
, name
)) {
468 printk(KERN_WARNING
"siimage: IDE controller MMIO ports not "
473 ioaddr
= ioremap(bar5
, barsize
);
474 if (ioaddr
== NULL
) {
475 release_mem_region(bar5
, barsize
);
480 pci_set_drvdata(dev
, (void *) ioaddr
);
486 * init_chipset_siimage - set up an SI device
490 * Perform the initial PCI set up for this device. Attempt to switch
491 * to 133 MHz clocking if the system isn't already set up to do it.
494 static unsigned int __devinit
init_chipset_siimage(struct pci_dev
*dev
,
497 unsigned long base
, scsc_addr
;
498 void __iomem
*ioaddr
= NULL
;
499 u8 rev
= dev
->revision
, tmp
, BA5_EN
;
501 pci_write_config_byte(dev
, PCI_CACHE_LINE_SIZE
, rev
? 1 : 255);
503 pci_read_config_byte(dev
, 0x8A, &BA5_EN
);
505 if ((BA5_EN
& 0x01) || pci_resource_start(dev
, 5))
506 if (setup_mmio_siimage(dev
, name
))
507 ioaddr
= pci_get_drvdata(dev
);
509 base
= (unsigned long)ioaddr
;
511 if (ioaddr
&& pdev_is_sata(dev
)) {
514 /* make sure IDE0/1 interrupts are not masked */
515 irq_mask
= (1 << 22) | (1 << 23);
516 tmp32
= readl(ioaddr
+ 0x48);
517 if (tmp32
& irq_mask
) {
519 writel(tmp32
, ioaddr
+ 0x48);
520 readl(ioaddr
+ 0x48); /* flush */
522 writel(0, ioaddr
+ 0x148);
523 writel(0, ioaddr
+ 0x1C8);
526 sil_iowrite8(dev
, 0, base
? (base
+ 0xB4) : 0x80);
527 sil_iowrite8(dev
, 0, base
? (base
+ 0xF4) : 0x84);
529 scsc_addr
= base
? (base
+ 0x4A) : 0x8A;
530 tmp
= sil_ioread8(dev
, scsc_addr
);
532 switch (tmp
& 0x30) {
534 /* On 100 MHz clocking, try and switch to 133 MHz */
535 sil_iowrite8(dev
, tmp
| 0x10, scsc_addr
);
538 /* Clocking is disabled, attempt to force 133MHz clocking. */
539 sil_iowrite8(dev
, tmp
& ~0x20, scsc_addr
);
541 /* On 133Mhz clocking. */
544 /* On PCIx2 clocking. */
548 tmp
= sil_ioread8(dev
, scsc_addr
);
550 sil_iowrite8 (dev
, 0x72, base
+ 0xA1);
551 sil_iowrite16(dev
, 0x328A, base
+ 0xA2);
552 sil_iowrite32(dev
, 0x62DD62DD, base
+ 0xA4);
553 sil_iowrite32(dev
, 0x43924392, base
+ 0xA8);
554 sil_iowrite32(dev
, 0x40094009, base
+ 0xAC);
555 sil_iowrite8 (dev
, 0x72, base
? (base
+ 0xE1) : 0xB1);
556 sil_iowrite16(dev
, 0x328A, base
? (base
+ 0xE2) : 0xB2);
557 sil_iowrite32(dev
, 0x62DD62DD, base
? (base
+ 0xE4) : 0xB4);
558 sil_iowrite32(dev
, 0x43924392, base
? (base
+ 0xE8) : 0xB8);
559 sil_iowrite32(dev
, 0x40094009, base
? (base
+ 0xEC) : 0xBC);
561 if (base
&& pdev_is_sata(dev
)) {
562 writel(0xFFFF0000, ioaddr
+ 0x108);
563 writel(0xFFFF0000, ioaddr
+ 0x188);
564 writel(0x00680000, ioaddr
+ 0x148);
565 writel(0x00680000, ioaddr
+ 0x1C8);
568 /* report the clocking mode of the controller */
569 if (!pdev_is_sata(dev
)) {
570 static const char *clk_str
[] =
571 { "== 100", "== 133", "== 2X PCI", "DISABLED!" };
574 printk(KERN_INFO
"%s: BASE CLOCK %s\n", name
, clk_str
[tmp
& 3]);
581 * init_mmio_iops_siimage - set up the iops for MMIO
582 * @hwif: interface to set up
584 * The basic setup here is fairly simple, we can use standard MMIO
585 * operations. However we do have to set the taskfile register offsets
586 * by hand as there isn't a standard defined layout for them this time.
588 * The hardware supports buffered taskfiles and also some rather nice
589 * extended PRD tables. For better SI3112 support use the libata driver
592 static void __devinit
init_mmio_iops_siimage(ide_hwif_t
*hwif
)
594 struct pci_dev
*dev
= to_pci_dev(hwif
->dev
);
595 void *addr
= pci_get_drvdata(dev
);
596 u8 ch
= hwif
->channel
;
597 struct ide_io_ports
*io_ports
= &hwif
->io_ports
;
601 * Fill in the basic hwif bits
603 hwif
->host_flags
|= IDE_HFLAG_MMIO
;
604 default_hwif_mmiops(hwif
);
605 hwif
->hwif_data
= addr
;
608 * Now set up the hw. We have to do this ourselves as the
609 * MMIO layout isn't the same as the standard port based I/O.
611 memset(io_ports
, 0, sizeof(*io_ports
));
613 base
= (unsigned long)addr
;
620 * The buffered task file doesn't have status/control, so we
621 * can't currently use it sanely since we want to use LBA48 mode.
623 io_ports
->data_addr
= base
;
624 io_ports
->error_addr
= base
+ 1;
625 io_ports
->nsect_addr
= base
+ 2;
626 io_ports
->lbal_addr
= base
+ 3;
627 io_ports
->lbam_addr
= base
+ 4;
628 io_ports
->lbah_addr
= base
+ 5;
629 io_ports
->device_addr
= base
+ 6;
630 io_ports
->status_addr
= base
+ 7;
631 io_ports
->ctl_addr
= base
+ 10;
633 if (pdev_is_sata(dev
)) {
634 base
= (unsigned long)addr
;
637 hwif
->sata_scr
[SATA_STATUS_OFFSET
] = base
+ 0x104;
638 hwif
->sata_scr
[SATA_ERROR_OFFSET
] = base
+ 0x108;
639 hwif
->sata_scr
[SATA_CONTROL_OFFSET
] = base
+ 0x100;
642 hwif
->irq
= dev
->irq
;
644 hwif
->dma_base
= (unsigned long)addr
+ (ch
? 0x08 : 0x00);
647 static int is_dev_seagate_sata(ide_drive_t
*drive
)
649 const char *s
= &drive
->id
->model
[0];
650 unsigned len
= strnlen(s
, sizeof(drive
->id
->model
));
652 if ((len
> 4) && (!memcmp(s
, "ST", 2)))
653 if ((!memcmp(s
+ len
- 2, "AS", 2)) ||
654 (!memcmp(s
+ len
- 3, "ASL", 3))) {
655 printk(KERN_INFO
"%s: applying pessimistic Seagate "
656 "errata fix\n", drive
->name
);
664 * sil_quirkproc - post probe fixups
667 * Called after drive probe we use this to decide whether the
668 * Seagate fixup must be applied. This used to be in init_iops but
669 * that can occur before we know what drives are present.
672 static void __devinit
sil_quirkproc(ide_drive_t
*drive
)
674 ide_hwif_t
*hwif
= drive
->hwif
;
676 /* Try and rise the rqsize */
677 if (!is_sata(hwif
) || !is_dev_seagate_sata(drive
))
682 * init_iops_siimage - set up iops
683 * @hwif: interface to set up
685 * Do the basic setup for the SIIMAGE hardware interface
686 * and then do the MMIO setup if we can. This is the first
687 * look in we get for setting up the hwif so that we
688 * can get the iops right before using them.
691 static void __devinit
init_iops_siimage(ide_hwif_t
*hwif
)
693 struct pci_dev
*dev
= to_pci_dev(hwif
->dev
);
695 hwif
->hwif_data
= NULL
;
697 /* Pessimal until we finish probing */
700 if (pci_get_drvdata(dev
) == NULL
)
703 init_mmio_iops_siimage(hwif
);
707 * sil_cable_detect - cable detection
708 * @hwif: interface to check
710 * Check for the presence of an ATA66 capable cable on the interface.
713 static u8 __devinit
sil_cable_detect(ide_hwif_t
*hwif
)
715 struct pci_dev
*dev
= to_pci_dev(hwif
->dev
);
716 unsigned long addr
= siimage_selreg(hwif
, 0);
717 u8 ata66
= sil_ioread8(dev
, addr
);
719 return (ata66
& 0x01) ? ATA_CBL_PATA80
: ATA_CBL_PATA40
;
722 static const struct ide_port_ops sil_pata_port_ops
= {
723 .set_pio_mode
= sil_set_pio_mode
,
724 .set_dma_mode
= sil_set_dma_mode
,
725 .quirkproc
= sil_quirkproc
,
726 .udma_filter
= sil_pata_udma_filter
,
727 .cable_detect
= sil_cable_detect
,
730 static const struct ide_port_ops sil_sata_port_ops
= {
731 .set_pio_mode
= sil_set_pio_mode
,
732 .set_dma_mode
= sil_set_dma_mode
,
733 .reset_poll
= sil_sata_reset_poll
,
734 .pre_reset
= sil_sata_pre_reset
,
735 .quirkproc
= sil_quirkproc
,
736 .udma_filter
= sil_sata_udma_filter
,
737 .cable_detect
= sil_cable_detect
,
740 static const struct ide_dma_ops sil_dma_ops
= {
741 .dma_host_set
= ide_dma_host_set
,
742 .dma_setup
= ide_dma_setup
,
743 .dma_exec_cmd
= ide_dma_exec_cmd
,
744 .dma_start
= ide_dma_start
,
745 .dma_end
= __ide_dma_end
,
746 .dma_test_irq
= siimage_dma_test_irq
,
747 .dma_timeout
= ide_dma_timeout
,
748 .dma_lost_irq
= ide_dma_lost_irq
,
751 #define DECLARE_SII_DEV(name_str, p_ops) \
754 .init_chipset = init_chipset_siimage, \
755 .init_iops = init_iops_siimage, \
757 .dma_ops = &sil_dma_ops, \
758 .pio_mask = ATA_PIO4, \
759 .mwdma_mask = ATA_MWDMA2, \
760 .udma_mask = ATA_UDMA6, \
763 static const struct ide_port_info siimage_chipsets
[] __devinitdata
= {
764 /* 0 */ DECLARE_SII_DEV("SiI680", &sil_pata_port_ops
),
765 /* 1 */ DECLARE_SII_DEV("SiI3112 Serial ATA", &sil_sata_port_ops
),
766 /* 2 */ DECLARE_SII_DEV("Adaptec AAR-1210SA", &sil_sata_port_ops
)
770 * siimage_init_one - PCI layer discovery entry
772 * @id: ident table entry
774 * Called by the PCI code when it finds an SiI680 or SiI3112 controller.
775 * We then use the IDE PCI generic helper to do most of the work.
778 static int __devinit
siimage_init_one(struct pci_dev
*dev
,
779 const struct pci_device_id
*id
)
781 struct ide_port_info d
;
782 u8 idx
= id
->driver_data
;
784 d
= siimage_chipsets
[idx
];
787 static int first
= 1;
790 printk(KERN_INFO
"siimage: For full SATA support you "
791 "should use the libata sata_sil module.\n");
795 d
.host_flags
|= IDE_HFLAG_NO_ATAPI_DMA
;
798 return ide_setup_pci_device(dev
, &d
);
801 static const struct pci_device_id siimage_pci_tbl
[] = {
802 { PCI_VDEVICE(CMD
, PCI_DEVICE_ID_SII_680
), 0 },
803 #ifdef CONFIG_BLK_DEV_IDE_SATA
804 { PCI_VDEVICE(CMD
, PCI_DEVICE_ID_SII_3112
), 1 },
805 { PCI_VDEVICE(CMD
, PCI_DEVICE_ID_SII_1210SA
), 2 },
809 MODULE_DEVICE_TABLE(pci
, siimage_pci_tbl
);
811 static struct pci_driver driver
= {
813 .id_table
= siimage_pci_tbl
,
814 .probe
= siimage_init_one
,
817 static int __init
siimage_ide_init(void)
819 return ide_pci_register_driver(&driver
);
822 module_init(siimage_ide_init
);
824 MODULE_AUTHOR("Andre Hedrick, Alan Cox");
825 MODULE_DESCRIPTION("PCI driver module for SiI IDE");
826 MODULE_LICENSE("GPL");