2 * linux/drivers/ide/pci/sis5513.c Version 0.30 Aug 9, 2007
4 * Copyright (C) 1999-2000 Andre Hedrick <andre@linux-ide.org>
5 * Copyright (C) 2002 Lionel Bouton <Lionel.Bouton@inet6.fr>, Maintainer
6 * Copyright (C) 2003 Vojtech Pavlik <vojtech@suse.cz>
7 * Copyright (C) 2007 Bartlomiej Zolnierkiewicz
9 * May be copied or modified under the terms of the GNU General Public License
14 * SiS Taiwan : for direct support and hardware.
15 * Daniela Engert : for initial ATA100 advices and numerous others.
16 * John Fremlin, Manfred Spraul, Dave Morgan, Peter Kjellerstedt :
17 * for checking code correctness, providing patches.
20 * Original tests and design on the SiS620 chipset.
21 * ATA100 tests and design on the SiS735 chipset.
22 * ATA16/33 support from specs
23 * ATA133 support for SiS961/962 by L.C. Chang <lcchang@sis.com.tw>
24 * ATA133 961/962/963 fixes by Vojtech Pavlik <vojtech@suse.cz>
27 * SiS chipset documentation available under NDA to companies only
28 * (not to individuals).
32 * The original SiS5513 comes from a SiS5511/55112/5513 chipset. The original
33 * SiS5513 was also used in the SiS5596/5513 chipset. Thus if we see a SiS5511
34 * or SiS5596, we can assume we see the first MWDMA-16 capable SiS5513 chip.
36 * Later SiS chipsets integrated the 5513 functionality into the NorthBridge,
37 * starting with SiS5571 and up to SiS745. The PCI ID didn't change, though. We
38 * can figure out that we have a more modern and more capable 5513 by looking
39 * for the respective NorthBridge IDs.
41 * Even later (96x family) SiS chipsets use the MuTIOL link and place the 5513
42 * into the SouthBrige. Here we cannot rely on looking up the NorthBridge PCI
43 * ID, while the now ATA-133 capable 5513 still has the same PCI ID.
44 * Fortunately the 5513 can be 'unmasked' by fiddling with some config space
45 * bits, changing its device id to the true one - 5517 for 961 and 5518 for
49 #include <linux/types.h>
50 #include <linux/module.h>
51 #include <linux/kernel.h>
52 #include <linux/delay.h>
53 #include <linux/timer.h>
55 #include <linux/ioport.h>
56 #include <linux/blkdev.h>
57 #include <linux/hdreg.h>
59 #include <linux/interrupt.h>
60 #include <linux/pci.h>
61 #include <linux/init.h>
62 #include <linux/ide.h>
66 #include "ide-timing.h"
68 #define DISPLAY_SIS_TIMINGS
70 /* registers layout and init values are chipset family dependant */
75 #define ATA_100a 0x04 // SiS730/SiS550 is ATA100 with ATA66 layout
77 #define ATA_133a 0x06 // SiS961b with 133 support
78 #define ATA_133 0x07 // SiS962/963
80 static u8 chipset_family
;
90 } SiSHostChipInfo
[] = {
91 { "SiS968", PCI_DEVICE_ID_SI_968
, ATA_133
},
92 { "SiS966", PCI_DEVICE_ID_SI_966
, ATA_133
},
93 { "SiS965", PCI_DEVICE_ID_SI_965
, ATA_133
},
94 { "SiS745", PCI_DEVICE_ID_SI_745
, ATA_100
},
95 { "SiS735", PCI_DEVICE_ID_SI_735
, ATA_100
},
96 { "SiS733", PCI_DEVICE_ID_SI_733
, ATA_100
},
97 { "SiS635", PCI_DEVICE_ID_SI_635
, ATA_100
},
98 { "SiS633", PCI_DEVICE_ID_SI_633
, ATA_100
},
100 { "SiS730", PCI_DEVICE_ID_SI_730
, ATA_100a
},
101 { "SiS550", PCI_DEVICE_ID_SI_550
, ATA_100a
},
103 { "SiS640", PCI_DEVICE_ID_SI_640
, ATA_66
},
104 { "SiS630", PCI_DEVICE_ID_SI_630
, ATA_66
},
105 { "SiS620", PCI_DEVICE_ID_SI_620
, ATA_66
},
106 { "SiS540", PCI_DEVICE_ID_SI_540
, ATA_66
},
107 { "SiS530", PCI_DEVICE_ID_SI_530
, ATA_66
},
109 { "SiS5600", PCI_DEVICE_ID_SI_5600
, ATA_33
},
110 { "SiS5598", PCI_DEVICE_ID_SI_5598
, ATA_33
},
111 { "SiS5597", PCI_DEVICE_ID_SI_5597
, ATA_33
},
112 { "SiS5591/2", PCI_DEVICE_ID_SI_5591
, ATA_33
},
113 { "SiS5582", PCI_DEVICE_ID_SI_5582
, ATA_33
},
114 { "SiS5581", PCI_DEVICE_ID_SI_5581
, ATA_33
},
116 { "SiS5596", PCI_DEVICE_ID_SI_5596
, ATA_16
},
117 { "SiS5571", PCI_DEVICE_ID_SI_5571
, ATA_16
},
118 { "SiS5517", PCI_DEVICE_ID_SI_5517
, ATA_16
},
119 { "SiS551x", PCI_DEVICE_ID_SI_5511
, ATA_16
},
122 /* Cycle time bits and values vary across chip dma capabilities
123 These three arrays hold the register layout and the values to set.
124 Indexed by chipset_family and (dma_mode - XFER_UDMA_0) */
126 /* {0, ATA_16, ATA_33, ATA_66, ATA_100a, ATA_100, ATA_133} */
127 static u8 cycle_time_offset
[] = {0,0,5,4,4,0,0};
128 static u8 cycle_time_range
[] = {0,0,2,3,3,4,4};
129 static u8 cycle_time_value
[][XFER_UDMA_6
- XFER_UDMA_0
+ 1] = {
130 {0,0,0,0,0,0,0}, /* no udma */
131 {0,0,0,0,0,0,0}, /* no udma */
132 {3,2,1,0,0,0,0}, /* ATA_33 */
133 {7,5,3,2,1,0,0}, /* ATA_66 */
134 {7,5,3,2,1,0,0}, /* ATA_100a (730 specific), differences are on cycle_time range and offset */
135 {11,7,5,4,2,1,0}, /* ATA_100 */
136 {15,10,7,5,3,2,1}, /* ATA_133a (earliest 691 southbridges) */
137 {15,10,7,5,3,2,1}, /* ATA_133 */
139 /* CRC Valid Setup Time vary across IDE clock setting 33/66/100/133
140 See SiS962 data sheet for more detail */
141 static u8 cvs_time_value
[][XFER_UDMA_6
- XFER_UDMA_0
+ 1] = {
142 {0,0,0,0,0,0,0}, /* no udma */
143 {0,0,0,0,0,0,0}, /* no udma */
151 /* Initialize time, Active time, Recovery time vary across
152 IDE clock settings. These 3 arrays hold the register value
153 for PIO0/1/2/3/4 and DMA0/1/2 mode in order */
154 static u8 ini_time_value
[][8] = {
164 static u8 act_time_value
[][8] = {
168 {19,19,19,5,4,14,5,4},
169 {19,19,19,5,4,14,5,4},
170 {28,28,28,7,6,21,7,6},
171 {38,38,38,10,9,28,10,9},
172 {38,38,38,10,9,28,10,9},
174 static u8 rco_time_value
[][8] = {
181 {40,12,4,12,5,34,12,5},
182 {40,12,4,12,5,34,12,5},
186 * Printing configuration
188 /* Used for chipset type printing at boot time */
189 static char* chipset_capability
[] = {
192 "ATA 100 (1st gen)", "ATA 100 (2nd gen)",
193 "ATA 133 (1st gen)", "ATA 133 (2nd gen)"
196 #if defined(DISPLAY_SIS_TIMINGS) && defined(CONFIG_IDE_PROC_FS)
197 #include <linux/stat.h>
198 #include <linux/proc_fs.h>
200 static u8 sis_proc
= 0;
202 static struct pci_dev
*bmide_dev
;
204 static char* cable_type
[] = {
209 static char* recovery_time
[] ={
210 "12 PCICLK", "1 PCICLK",
211 "2 PCICLK", "3 PCICLK",
212 "4 PCICLK", "5 PCICLCK",
213 "6 PCICLK", "7 PCICLCK",
214 "8 PCICLK", "9 PCICLCK",
215 "10 PCICLK", "11 PCICLK",
216 "13 PCICLK", "14 PCICLK",
217 "15 PCICLK", "15 PCICLK"
220 static char* active_time
[] = {
221 "8 PCICLK", "1 PCICLCK",
222 "2 PCICLK", "3 PCICLK",
223 "4 PCICLK", "5 PCICLK",
224 "6 PCICLK", "12 PCICLK"
227 static char* cycle_time
[] = {
238 /* Generic add master or slave info function */
239 static char* get_drives_info (char *buffer
, u8 pos
)
241 u8 reg00
, reg01
, reg10
, reg11
; /* timing registers */
245 /* Postwrite/Prefetch */
246 if (chipset_family
< ATA_133
) {
247 pci_read_config_byte(bmide_dev
, 0x4b, ®00
);
248 p
+= sprintf(p
, "Drive %d: Postwrite %s \t \t Postwrite %s\n",
249 pos
, (reg00
& (0x10 << pos
)) ? "Enabled" : "Disabled",
250 (reg00
& (0x40 << pos
)) ? "Enabled" : "Disabled");
251 p
+= sprintf(p
, " Prefetch %s \t \t Prefetch %s\n",
252 (reg00
& (0x01 << pos
)) ? "Enabled" : "Disabled",
253 (reg00
& (0x04 << pos
)) ? "Enabled" : "Disabled");
254 pci_read_config_byte(bmide_dev
, 0x40+2*pos
, ®00
);
255 pci_read_config_byte(bmide_dev
, 0x41+2*pos
, ®01
);
256 pci_read_config_byte(bmide_dev
, 0x44+2*pos
, ®10
);
257 pci_read_config_byte(bmide_dev
, 0x45+2*pos
, ®11
);
261 pci_read_config_dword(bmide_dev
, 0x54, ®54h
);
262 if (reg54h
& 0x40000000) {
263 // Configuration space remapped to 0x70
266 pci_read_config_dword(bmide_dev
, (unsigned long)drive_pci
+4*pos
, ®dw0
);
267 pci_read_config_dword(bmide_dev
, (unsigned long)drive_pci
+4*pos
+8, ®dw1
);
269 p
+= sprintf(p
, "Drive %d:\n", pos
);
274 if (chipset_family
>= ATA_133
) {
275 p
+= sprintf(p
, " UDMA %s \t \t \t UDMA %s\n",
276 (regdw0
& 0x04) ? "Enabled" : "Disabled",
277 (regdw1
& 0x04) ? "Enabled" : "Disabled");
278 p
+= sprintf(p
, " UDMA Cycle Time %s \t UDMA Cycle Time %s\n",
279 cycle_time
[(regdw0
& 0xF0) >> 4],
280 cycle_time
[(regdw1
& 0xF0) >> 4]);
281 } else if (chipset_family
>= ATA_33
) {
282 p
+= sprintf(p
, " UDMA %s \t \t \t UDMA %s\n",
283 (reg01
& 0x80) ? "Enabled" : "Disabled",
284 (reg11
& 0x80) ? "Enabled" : "Disabled");
286 p
+= sprintf(p
, " UDMA Cycle Time ");
287 switch(chipset_family
) {
288 case ATA_33
: p
+= sprintf(p
, cycle_time
[(reg01
& 0x60) >> 5]); break;
290 case ATA_100a
: p
+= sprintf(p
, cycle_time
[(reg01
& 0x70) >> 4]); break;
292 case ATA_133a
: p
+= sprintf(p
, cycle_time
[reg01
& 0x0F]); break;
293 default: p
+= sprintf(p
, "?"); break;
295 p
+= sprintf(p
, " \t UDMA Cycle Time ");
296 switch(chipset_family
) {
297 case ATA_33
: p
+= sprintf(p
, cycle_time
[(reg11
& 0x60) >> 5]); break;
299 case ATA_100a
: p
+= sprintf(p
, cycle_time
[(reg11
& 0x70) >> 4]); break;
301 case ATA_133a
: p
+= sprintf(p
, cycle_time
[reg11
& 0x0F]); break;
302 default: p
+= sprintf(p
, "?"); break;
304 p
+= sprintf(p
, "\n");
308 if (chipset_family
< ATA_133
) { /* else case TODO */
311 p
+= sprintf(p
, " Data Active Time ");
312 switch(chipset_family
) {
313 case ATA_16
: /* confirmed */
316 case ATA_100a
: p
+= sprintf(p
, active_time
[reg01
& 0x07]); break;
318 case ATA_133a
: p
+= sprintf(p
, active_time
[(reg00
& 0x70) >> 4]); break;
319 default: p
+= sprintf(p
, "?"); break;
321 p
+= sprintf(p
, " \t Data Active Time ");
322 switch(chipset_family
) {
326 case ATA_100a
: p
+= sprintf(p
, active_time
[reg11
& 0x07]); break;
328 case ATA_133a
: p
+= sprintf(p
, active_time
[(reg10
& 0x70) >> 4]); break;
329 default: p
+= sprintf(p
, "?"); break;
331 p
+= sprintf(p
, "\n");
334 /* warning: may need (reg&0x07) for pre ATA66 chips */
335 p
+= sprintf(p
, " Data Recovery Time %s \t Data Recovery Time %s\n",
336 recovery_time
[reg00
& 0x0f], recovery_time
[reg10
& 0x0f]);
342 static char* get_masters_info(char* buffer
)
344 return get_drives_info(buffer
, 0);
347 static char* get_slaves_info(char* buffer
)
349 return get_drives_info(buffer
, 1);
352 /* Main get_info, called on /proc/ide/sis reads */
353 static int sis_get_info (char *buffer
, char **addr
, off_t offset
, int count
)
360 p
+= sprintf(p
, "\nSiS 5513 ");
361 switch(chipset_family
) {
362 case ATA_16
: p
+= sprintf(p
, "DMA 16"); break;
363 case ATA_33
: p
+= sprintf(p
, "Ultra 33"); break;
364 case ATA_66
: p
+= sprintf(p
, "Ultra 66"); break;
366 case ATA_100
: p
+= sprintf(p
, "Ultra 100"); break;
368 case ATA_133
: p
+= sprintf(p
, "Ultra 133"); break;
369 default: p
+= sprintf(p
, "Unknown???"); break;
371 p
+= sprintf(p
, " chipset\n");
372 p
+= sprintf(p
, "--------------- Primary Channel "
373 "---------------- Secondary Channel "
377 pci_read_config_byte(bmide_dev
, 0x4a, ®
);
378 if (chipset_family
== ATA_133
) {
379 pci_read_config_word(bmide_dev
, 0x50, ®2
);
380 pci_read_config_word(bmide_dev
, 0x52, ®3
);
382 p
+= sprintf(p
, "Channel Status: ");
383 if (chipset_family
< ATA_66
) {
384 p
+= sprintf(p
, "%s \t \t \t \t %s\n",
385 (reg
& 0x04) ? "On" : "Off",
386 (reg
& 0x02) ? "On" : "Off");
387 } else if (chipset_family
< ATA_133
) {
388 p
+= sprintf(p
, "%s \t \t \t \t %s \n",
389 (reg
& 0x02) ? "On" : "Off",
390 (reg
& 0x04) ? "On" : "Off");
391 } else { /* ATA_133 */
392 p
+= sprintf(p
, "%s \t \t \t \t %s \n",
393 (reg2
& 0x02) ? "On" : "Off",
394 (reg3
& 0x02) ? "On" : "Off");
398 pci_read_config_byte(bmide_dev
, 0x09, ®
);
399 p
+= sprintf(p
, "Operation Mode: %s \t \t \t %s \n",
400 (reg
& 0x01) ? "Native" : "Compatible",
401 (reg
& 0x04) ? "Native" : "Compatible");
404 if (chipset_family
>= ATA_133
) {
405 p
+= sprintf(p
, "Cable Type: %s \t \t \t %s\n",
406 (reg2
& 0x01) ? cable_type
[1] : cable_type
[0],
407 (reg3
& 0x01) ? cable_type
[1] : cable_type
[0]);
408 } else if (chipset_family
> ATA_33
) {
409 pci_read_config_byte(bmide_dev
, 0x48, ®
);
410 p
+= sprintf(p
, "Cable Type: %s \t \t \t %s\n",
411 (reg
& 0x10) ? cable_type
[1] : cable_type
[0],
412 (reg
& 0x20) ? cable_type
[1] : cable_type
[0]);
416 if (chipset_family
< ATA_133
) {
417 pci_read_config_word(bmide_dev
, 0x4c, ®2
);
418 pci_read_config_word(bmide_dev
, 0x4e, ®3
);
419 p
+= sprintf(p
, "Prefetch Count: %d \t \t \t \t %d\n",
423 p
= get_masters_info(p
);
424 p
= get_slaves_info(p
);
426 len
= (p
- buffer
) - offset
;
427 *addr
= buffer
+ offset
;
429 return len
> count
? count
: len
;
431 #endif /* defined(DISPLAY_SIS_TIMINGS) && defined(CONFIG_IDE_PROC_FS) */
434 * Configuration functions
437 static u8
sis_ata133_get_base(ide_drive_t
*drive
)
439 struct pci_dev
*dev
= drive
->hwif
->pci_dev
;
442 pci_read_config_dword(dev
, 0x54, ®54
);
444 return ((reg54
& 0x40000000) ? 0x70 : 0x40) + drive
->dn
* 4;
447 static void sis_ata16_program_timings(ide_drive_t
*drive
, const u8 mode
)
449 struct pci_dev
*dev
= drive
->hwif
->pci_dev
;
451 u8 drive_pci
= 0x40 + drive
->dn
* 2;
453 const u16 pio_timings
[] = { 0x000, 0x607, 0x404, 0x303, 0x301 };
454 const u16 mwdma_timings
[] = { 0x008, 0x302, 0x301 };
456 pci_read_config_word(dev
, drive_pci
, &t1
);
458 /* clear active/recovery timings */
460 if (mode
>= XFER_MW_DMA_0
) {
461 if (chipset_family
> ATA_16
)
462 t1
&= ~0x8000; /* disable UDMA */
463 t1
|= mwdma_timings
[mode
- XFER_MW_DMA_0
];
465 t1
|= pio_timings
[mode
- XFER_PIO_0
];
467 pci_write_config_word(dev
, drive_pci
, t1
);
470 static void sis_ata100_program_timings(ide_drive_t
*drive
, const u8 mode
)
472 struct pci_dev
*dev
= drive
->hwif
->pci_dev
;
473 u8 t1
, drive_pci
= 0x40 + drive
->dn
* 2;
475 /* timing bits: 7:4 active 3:0 recovery */
476 const u8 pio_timings
[] = { 0x00, 0x67, 0x44, 0x33, 0x31 };
477 const u8 mwdma_timings
[] = { 0x08, 0x32, 0x31 };
479 if (mode
>= XFER_MW_DMA_0
) {
482 pci_read_config_byte(dev
, drive_pci
, &t2
);
483 t2
&= ~0x80; /* disable UDMA */
484 pci_write_config_byte(dev
, drive_pci
, t2
);
486 t1
= mwdma_timings
[mode
- XFER_MW_DMA_0
];
488 t1
= pio_timings
[mode
- XFER_PIO_0
];
490 pci_write_config_byte(dev
, drive_pci
+ 1, t1
);
493 static void sis_ata133_program_timings(ide_drive_t
*drive
, const u8 mode
)
495 struct pci_dev
*dev
= drive
->hwif
->pci_dev
;
497 u8 drive_pci
= sis_ata133_get_base(drive
), clk
, idx
;
499 pci_read_config_dword(dev
, drive_pci
, &t1
);
502 clk
= (t1
& 0x08) ? ATA_133
: ATA_100
;
503 if (mode
>= XFER_MW_DMA_0
) {
504 t1
&= ~0x04; /* disable UDMA */
505 idx
= mode
- XFER_MW_DMA_0
+ 5;
507 idx
= mode
- XFER_PIO_0
;
508 t1
|= ini_time_value
[clk
][idx
] << 12;
509 t1
|= act_time_value
[clk
][idx
] << 16;
510 t1
|= rco_time_value
[clk
][idx
] << 24;
512 pci_write_config_dword(dev
, drive_pci
, t1
);
515 static void sis_program_timings(ide_drive_t
*drive
, const u8 mode
)
517 if (chipset_family
< ATA_100
) /* ATA_16/33/66/100a */
518 sis_ata16_program_timings(drive
, mode
);
519 else if (chipset_family
< ATA_133
) /* ATA_100/133a */
520 sis_ata100_program_timings(drive
, mode
);
522 sis_ata133_program_timings(drive
, mode
);
525 static void config_drive_art_rwp (ide_drive_t
*drive
)
527 ide_hwif_t
*hwif
= HWIF(drive
);
528 struct pci_dev
*dev
= hwif
->pci_dev
;
532 pci_read_config_byte(dev
, 0x4b, ®4bh
);
534 if (drive
->media
== ide_disk
)
535 rw_prefetch
= 0x11 << drive
->dn
;
537 if ((reg4bh
& (0x11 << drive
->dn
)) != rw_prefetch
)
538 pci_write_config_byte(dev
, 0x4b, reg4bh
|rw_prefetch
);
541 static void sis_set_pio_mode(ide_drive_t
*drive
, const u8 pio
)
543 config_drive_art_rwp(drive
);
544 sis_program_timings(drive
, XFER_PIO_0
+ pio
);
547 static void sis_set_dma_mode(ide_drive_t
*drive
, const u8 speed
)
549 ide_hwif_t
*hwif
= HWIF(drive
);
550 struct pci_dev
*dev
= hwif
->pci_dev
;
552 /* Config chip for mode */
561 if (chipset_family
>= ATA_133
) {
563 u8 drive_pci
= sis_ata133_get_base(drive
);
565 pci_read_config_dword(dev
, drive_pci
, ®dw
);
568 /* check if ATA133 enable */
570 regdw
|= (unsigned long)cycle_time_value
[ATA_133
][speed
-XFER_UDMA_0
] << 4;
571 regdw
|= (unsigned long)cvs_time_value
[ATA_133
][speed
-XFER_UDMA_0
] << 8;
573 regdw
|= (unsigned long)cycle_time_value
[ATA_100
][speed
-XFER_UDMA_0
] << 4;
574 regdw
|= (unsigned long)cvs_time_value
[ATA_100
][speed
-XFER_UDMA_0
] << 8;
576 pci_write_config_dword(dev
, (unsigned long)drive_pci
, regdw
);
578 u8 drive_pci
= 0x40 + drive
->dn
* 2, reg
= 0;
580 pci_read_config_byte(dev
, drive_pci
+1, ®
);
581 /* Force the UDMA bit on if we want to use UDMA */
583 /* clean reg cycle time bits */
584 reg
&= ~((0xFF >> (8 - cycle_time_range
[chipset_family
]))
585 << cycle_time_offset
[chipset_family
]);
586 /* set reg cycle time bits */
587 reg
|= cycle_time_value
[chipset_family
][speed
-XFER_UDMA_0
]
588 << cycle_time_offset
[chipset_family
];
589 pci_write_config_byte(dev
, drive_pci
+1, reg
);
595 sis_program_timings(drive
, speed
);
603 static u8
sis5513_ata133_udma_filter(ide_drive_t
*drive
)
605 struct pci_dev
*dev
= drive
->hwif
->pci_dev
;
607 u8 drive_pci
= sis_ata133_get_base(drive
);
609 pci_read_config_dword(dev
, drive_pci
, ®dw
);
611 /* if ATA133 disable, we should not set speed above UDMA5 */
612 return (regdw
& 0x08) ? ATA_UDMA6
: ATA_UDMA5
;
615 /* Chip detection and general config */
616 static unsigned int __devinit
init_chipset_sis5513 (struct pci_dev
*dev
, const char *name
)
618 struct pci_dev
*host
;
623 for (i
= 0; i
< ARRAY_SIZE(SiSHostChipInfo
) && !chipset_family
; i
++) {
625 host
= pci_get_device(PCI_VENDOR_ID_SI
, SiSHostChipInfo
[i
].host_id
, NULL
);
630 chipset_family
= SiSHostChipInfo
[i
].chipset_family
;
632 /* Special case for SiS630 : 630S/ET is ATA_100a */
633 if (SiSHostChipInfo
[i
].host_id
== PCI_DEVICE_ID_SI_630
) {
634 if (host
->revision
>= 0x30)
635 chipset_family
= ATA_100a
;
639 printk(KERN_INFO
"SIS5513: %s %s controller\n",
640 SiSHostChipInfo
[i
].name
, chipset_capability
[chipset_family
]);
643 if (!chipset_family
) { /* Belongs to pci-quirks */
648 /* Disable ID masking and register remapping */
649 pci_read_config_dword(dev
, 0x54, &idemisc
);
650 pci_write_config_dword(dev
, 0x54, (idemisc
& 0x7fffffff));
651 pci_read_config_word(dev
, PCI_DEVICE_ID
, &trueid
);
652 pci_write_config_dword(dev
, 0x54, idemisc
);
654 if (trueid
== 0x5518) {
655 printk(KERN_INFO
"SIS5513: SiS 962/963 MuTIOL IDE UDMA133 controller\n");
656 chipset_family
= ATA_133
;
658 /* Check for 5513 compability mapping
659 * We must use this, else the port enabled code will fail,
660 * as it expects the enablebits at 0x4a.
662 if ((idemisc
& 0x40000000) == 0) {
663 pci_write_config_dword(dev
, 0x54, idemisc
| 0x40000000);
664 printk(KERN_INFO
"SIS5513: Switching to 5513 register mapping\n");
669 if (!chipset_family
) { /* Belongs to pci-quirks */
671 struct pci_dev
*lpc_bridge
;
676 pci_read_config_byte(dev
, 0x4a, &idecfg
);
677 pci_write_config_byte(dev
, 0x4a, idecfg
| 0x10);
678 pci_read_config_word(dev
, PCI_DEVICE_ID
, &trueid
);
679 pci_write_config_byte(dev
, 0x4a, idecfg
);
681 if (trueid
== 0x5517) { /* SiS 961/961B */
683 lpc_bridge
= pci_get_slot(dev
->bus
, 0x10); /* Bus 0, Dev 2, Fn 0 */
684 pci_read_config_byte(dev
, 0x49, &prefctl
);
685 pci_dev_put(lpc_bridge
);
687 if (lpc_bridge
->revision
== 0x10 && (prefctl
& 0x80)) {
688 printk(KERN_INFO
"SIS5513: SiS 961B MuTIOL IDE UDMA133 controller\n");
689 chipset_family
= ATA_133a
;
691 printk(KERN_INFO
"SIS5513: SiS 961 MuTIOL IDE UDMA100 controller\n");
692 chipset_family
= ATA_100
;
700 /* Make general config ops here
701 1/ tell IDE channels to operate in Compatibility mode only
702 2/ tell old chips to allow per drive IDE timings */
708 switch(chipset_family
) {
710 /* SiS962 operation mode */
711 pci_read_config_word(dev
, 0x50, ®w
);
713 pci_write_config_word(dev
, 0x50, regw
&0xfff7);
714 pci_read_config_word(dev
, 0x52, ®w
);
716 pci_write_config_word(dev
, 0x52, regw
&0xfff7);
721 pci_write_config_byte(dev
, PCI_LATENCY_TIMER
, 0x80);
722 /* Set compatibility bit */
723 pci_read_config_byte(dev
, 0x49, ®
);
725 pci_write_config_byte(dev
, 0x49, reg
|0x01);
731 pci_write_config_byte(dev
, PCI_LATENCY_TIMER
, 0x10);
733 /* On ATA_66 chips the bit was elsewhere */
734 pci_read_config_byte(dev
, 0x52, ®
);
736 pci_write_config_byte(dev
, 0x52, reg
|0x04);
740 /* On ATA_33 we didn't have a single bit to set */
741 pci_read_config_byte(dev
, 0x09, ®
);
742 if ((reg
& 0x0f) != 0x00) {
743 pci_write_config_byte(dev
, 0x09, reg
&0xf0);
746 /* force per drive recovery and active timings
747 needed on ATA_33 and below chips */
748 pci_read_config_byte(dev
, 0x52, ®
);
750 pci_write_config_byte(dev
, 0x52, reg
|0x08);
755 #if defined(DISPLAY_SIS_TIMINGS) && defined(CONFIG_IDE_PROC_FS)
759 ide_pci_create_host_proc("sis", sis_get_info
);
773 static const struct sis_laptop sis_laptop
[] = {
774 /* devid, subvendor, subdev */
775 { 0x5513, 0x1043, 0x1107 }, /* ASUS A6K */
776 { 0x5513, 0x1734, 0x105f }, /* FSC Amilo A1630 */
781 static u8 __devinit
ata66_sis5513(ide_hwif_t
*hwif
)
783 struct pci_dev
*pdev
= hwif
->pci_dev
;
784 const struct sis_laptop
*lap
= &sis_laptop
[0];
787 while (lap
->device
) {
788 if (lap
->device
== pdev
->device
&&
789 lap
->subvendor
== pdev
->subsystem_vendor
&&
790 lap
->subdevice
== pdev
->subsystem_device
)
791 return ATA_CBL_PATA40_SHORT
;
795 if (chipset_family
>= ATA_133
) {
797 u16 reg_addr
= hwif
->channel
? 0x52: 0x50;
798 pci_read_config_word(hwif
->pci_dev
, reg_addr
, ®w
);
799 ata66
= (regw
& 0x8000) ? 0 : 1;
800 } else if (chipset_family
>= ATA_66
) {
802 u8 mask
= hwif
->channel
? 0x20 : 0x10;
803 pci_read_config_byte(hwif
->pci_dev
, 0x48, ®48h
);
804 ata66
= (reg48h
& mask
) ? 0 : 1;
807 return ata66
? ATA_CBL_PATA80
: ATA_CBL_PATA40
;
810 static void __devinit
init_hwif_sis5513 (ide_hwif_t
*hwif
)
812 u8 udma_rates
[] = { 0x00, 0x00, 0x07, 0x1f, 0x3f, 0x3f, 0x7f, 0x7f };
817 hwif
->irq
= hwif
->channel
? 15 : 14;
819 hwif
->set_pio_mode
= &sis_set_pio_mode
;
820 hwif
->set_dma_mode
= &sis_set_dma_mode
;
822 if (chipset_family
>= ATA_133
)
823 hwif
->udma_filter
= sis5513_ata133_udma_filter
;
825 hwif
->drives
[0].autotune
= 1;
826 hwif
->drives
[1].autotune
= 1;
828 if (hwif
->dma_base
== 0)
833 hwif
->ultra_mask
= udma_rates
[chipset_family
];
834 hwif
->mwdma_mask
= 0x07;
836 if (hwif
->cbl
!= ATA_CBL_PATA40_SHORT
)
837 hwif
->cbl
= ata66_sis5513(hwif
);
842 hwif
->drives
[0].autodma
= hwif
->autodma
;
843 hwif
->drives
[1].autodma
= hwif
->autodma
;
846 static ide_pci_device_t sis5513_chipset __devinitdata
= {
848 .init_chipset
= init_chipset_sis5513
,
849 .init_hwif
= init_hwif_sis5513
,
850 .autodma
= NOAUTODMA
,
851 .enablebits
= {{0x4a,0x02,0x02}, {0x4a,0x04,0x04}},
852 .bootable
= ON_BOARD
,
853 .pio_mask
= ATA_PIO4
,
856 static int __devinit
sis5513_init_one(struct pci_dev
*dev
, const struct pci_device_id
*id
)
858 return ide_setup_pci_device(dev
, &sis5513_chipset
);
861 static const struct pci_device_id sis5513_pci_tbl
[] = {
862 { PCI_VDEVICE(SI
, PCI_DEVICE_ID_SI_5513
), 0 },
863 { PCI_VDEVICE(SI
, PCI_DEVICE_ID_SI_5518
), 0 },
864 { PCI_VDEVICE(SI
, PCI_DEVICE_ID_SI_1180
), 0 },
867 MODULE_DEVICE_TABLE(pci
, sis5513_pci_tbl
);
869 static struct pci_driver driver
= {
871 .id_table
= sis5513_pci_tbl
,
872 .probe
= sis5513_init_one
,
875 static int __init
sis5513_ide_init(void)
877 return ide_pci_register_driver(&driver
);
880 module_init(sis5513_ide_init
);
882 MODULE_AUTHOR("Lionel Bouton, L C Chang, Andre Hedrick, Vojtech Pavlik");
883 MODULE_DESCRIPTION("PCI driver module for SIS IDE");
884 MODULE_LICENSE("GPL");
889 * - Use drivers/ide/ide-timing.h !
890 * - More checks in the config registers (force values instead of
891 * relying on the BIOS setting them correctly).
892 * - Further optimisations ?
893 * . for example ATA66+ regs 0x48 & 0x4A