2 * SL82C105/Winbond 553 IDE driver
6 * Drive tuning added from Rebel.com's kernel sources
7 * -- Russell King (15/11/98) linux@arm.linux.org.uk
9 * Merge in Russell's HW workarounds, fix various problems
10 * with the timing registers setup.
11 * -- Benjamin Herrenschmidt (01/11/03) benh@kernel.crashing.org
13 * Copyright (C) 2006-2007 MontaVista Software, Inc. <source@mvista.com>
14 * Copyright (C) 2007 Bartlomiej Zolnierkiewicz
17 #include <linux/types.h>
18 #include <linux/module.h>
19 #include <linux/kernel.h>
20 #include <linux/hdreg.h>
21 #include <linux/pci.h>
22 #include <linux/ide.h>
29 #define DBG(arg) printk arg
34 * SL82C105 PCI config register 0x40 bits.
36 #define CTRL_IDE_IRQB (1 << 30)
37 #define CTRL_IDE_IRQA (1 << 28)
38 #define CTRL_LEGIRQ (1 << 11)
39 #define CTRL_P1F16 (1 << 5)
40 #define CTRL_P1EN (1 << 4)
41 #define CTRL_P0F16 (1 << 1)
42 #define CTRL_P0EN (1 << 0)
45 * Convert a PIO mode and cycle time to the required on/off times
46 * for the interface. This has protection against runaway timings.
48 static unsigned int get_pio_timings(ide_drive_t
*drive
, u8 pio
)
50 struct ide_timing
*t
= ide_timing_find_mode(XFER_PIO_0
+ pio
);
51 unsigned int cmd_on
, cmd_off
;
54 cmd_on
= (t
->active
+ 29) / 30;
55 cmd_off
= (ide_pio_cycle_time(drive
, pio
) - 30 * cmd_on
+ 29) / 30;
63 if (pio
> 2 || ide_dev_has_iordy(drive
->id
))
66 return (cmd_on
- 1) << 8 | (cmd_off
- 1) | iordy
;
70 * Configure the chipset for PIO mode.
72 static void sl82c105_set_pio_mode(ide_drive_t
*drive
, const u8 pio
)
74 struct pci_dev
*dev
= to_pci_dev(drive
->hwif
->dev
);
75 int reg
= 0x44 + drive
->dn
* 4;
78 drv_ctrl
= get_pio_timings(drive
, pio
);
81 * Store the PIO timings so that we can restore them
82 * in case DMA will be turned off...
84 drive
->drive_data
&= 0xffff0000;
85 drive
->drive_data
|= drv_ctrl
;
87 pci_write_config_word(dev
, reg
, drv_ctrl
);
88 pci_read_config_word (dev
, reg
, &drv_ctrl
);
90 printk(KERN_DEBUG
"%s: selected %s (%dns) (%04X)\n", drive
->name
,
91 ide_xfer_verbose(pio
+ XFER_PIO_0
),
92 ide_pio_cycle_time(drive
, pio
), drv_ctrl
);
96 * Configure the chipset for DMA mode.
98 static void sl82c105_set_dma_mode(ide_drive_t
*drive
, const u8 speed
)
100 static u16 mwdma_timings
[] = {0x0707, 0x0201, 0x0200};
103 DBG(("sl82c105_tune_chipset(drive:%s, speed:%s)\n",
104 drive
->name
, ide_xfer_verbose(speed
)));
106 drv_ctrl
= mwdma_timings
[speed
- XFER_MW_DMA_0
];
109 * Store the DMA timings so that we can actually program
110 * them when DMA will be turned on...
112 drive
->drive_data
&= 0x0000ffff;
113 drive
->drive_data
|= (unsigned long)drv_ctrl
<< 16;
117 * The SL82C105 holds off all IDE interrupts while in DMA mode until
118 * all DMA activity is completed. Sometimes this causes problems (eg,
119 * when the drive wants to report an error condition).
121 * 0x7e is a "chip testing" register. Bit 2 resets the DMA controller
122 * state machine. We need to kick this to work around various bugs.
124 static inline void sl82c105_reset_host(struct pci_dev
*dev
)
128 pci_read_config_word(dev
, 0x7e, &val
);
129 pci_write_config_word(dev
, 0x7e, val
| (1 << 2));
130 pci_write_config_word(dev
, 0x7e, val
& ~(1 << 2));
134 * If we get an IRQ timeout, it might be that the DMA state machine
135 * got confused. Fix from Todd Inglett. Details from Winbond.
137 * This function is called when the IDE timer expires, the drive
138 * indicates that it is READY, and we were waiting for DMA to complete.
140 static void sl82c105_dma_lost_irq(ide_drive_t
*drive
)
142 ide_hwif_t
*hwif
= HWIF(drive
);
143 struct pci_dev
*dev
= to_pci_dev(hwif
->dev
);
144 u32 val
, mask
= hwif
->channel
? CTRL_IDE_IRQB
: CTRL_IDE_IRQA
;
147 printk("sl82c105: lost IRQ, resetting host\n");
150 * Check the raw interrupt from the drive.
152 pci_read_config_dword(dev
, 0x40, &val
);
154 printk("sl82c105: drive was requesting IRQ, but host lost it\n");
157 * Was DMA enabled? If so, disable it - we're resetting the
158 * host. The IDE layer will be handling the drive for us.
160 dma_cmd
= inb(hwif
->dma_command
);
162 outb(dma_cmd
& ~1, hwif
->dma_command
);
163 printk("sl82c105: DMA was enabled\n");
166 sl82c105_reset_host(dev
);
170 * ATAPI devices can cause the SL82C105 DMA state machine to go gaga.
171 * Winbond recommend that the DMA state machine is reset prior to
172 * setting the bus master DMA enable bit.
174 * The generic IDE core will have disabled the BMEN bit before this
175 * function is called.
177 static void sl82c105_dma_start(ide_drive_t
*drive
)
179 ide_hwif_t
*hwif
= HWIF(drive
);
180 struct pci_dev
*dev
= to_pci_dev(hwif
->dev
);
181 int reg
= 0x44 + drive
->dn
* 4;
183 DBG(("%s(drive:%s)\n", __func__
, drive
->name
));
185 pci_write_config_word(dev
, reg
, drive
->drive_data
>> 16);
187 sl82c105_reset_host(dev
);
188 ide_dma_start(drive
);
191 static void sl82c105_dma_timeout(ide_drive_t
*drive
)
193 struct pci_dev
*dev
= to_pci_dev(drive
->hwif
->dev
);
195 DBG(("sl82c105_dma_timeout(drive:%s)\n", drive
->name
));
197 sl82c105_reset_host(dev
);
198 ide_dma_timeout(drive
);
201 static int sl82c105_dma_end(ide_drive_t
*drive
)
203 struct pci_dev
*dev
= to_pci_dev(drive
->hwif
->dev
);
204 int reg
= 0x44 + drive
->dn
* 4;
207 DBG(("%s(drive:%s)\n", __func__
, drive
->name
));
209 ret
= __ide_dma_end(drive
);
211 pci_write_config_word(dev
, reg
, drive
->drive_data
);
217 * ATA reset will clear the 16 bits mode in the control
218 * register, we need to reprogram it
220 static void sl82c105_resetproc(ide_drive_t
*drive
)
222 struct pci_dev
*dev
= to_pci_dev(drive
->hwif
->dev
);
225 DBG(("sl82c105_resetproc(drive:%s)\n", drive
->name
));
227 pci_read_config_dword(dev
, 0x40, &val
);
228 val
|= (CTRL_P1F16
| CTRL_P0F16
);
229 pci_write_config_dword(dev
, 0x40, val
);
233 * Return the revision of the Winbond bridge
234 * which this function is part of.
236 static u8
sl82c105_bridge_revision(struct pci_dev
*dev
)
238 struct pci_dev
*bridge
;
241 * The bridge should be part of the same device, but function 0.
243 bridge
= pci_get_bus_and_slot(dev
->bus
->number
,
244 PCI_DEVFN(PCI_SLOT(dev
->devfn
), 0));
249 * Make sure it is a Winbond 553 and is an ISA bridge.
251 if (bridge
->vendor
!= PCI_VENDOR_ID_WINBOND
||
252 bridge
->device
!= PCI_DEVICE_ID_WINBOND_83C553
||
253 bridge
->class >> 8 != PCI_CLASS_BRIDGE_ISA
) {
258 * We need to find function 0's revision, not function 1
262 return bridge
->revision
;
266 * Enable the PCI device
268 * --BenH: It's arch fixup code that should enable channels that
269 * have not been enabled by firmware. I decided we can still enable
270 * channel 0 here at least, but channel 1 has to be enabled by
271 * firmware or arch code. We still set both to 16 bits mode.
273 static unsigned int __devinit
init_chipset_sl82c105(struct pci_dev
*dev
, const char *msg
)
277 DBG(("init_chipset_sl82c105()\n"));
279 pci_read_config_dword(dev
, 0x40, &val
);
280 val
|= CTRL_P0EN
| CTRL_P0F16
| CTRL_P1F16
;
281 pci_write_config_dword(dev
, 0x40, val
);
286 static const struct ide_port_ops sl82c105_port_ops
= {
287 .set_pio_mode
= sl82c105_set_pio_mode
,
288 .set_dma_mode
= sl82c105_set_dma_mode
,
289 .resetproc
= sl82c105_resetproc
,
292 static const struct ide_dma_ops sl82c105_dma_ops
= {
293 .dma_host_set
= ide_dma_host_set
,
294 .dma_setup
= ide_dma_setup
,
295 .dma_exec_cmd
= ide_dma_exec_cmd
,
296 .dma_start
= sl82c105_dma_start
,
297 .dma_end
= sl82c105_dma_end
,
298 .dma_test_irq
= ide_dma_test_irq
,
299 .dma_lost_irq
= sl82c105_dma_lost_irq
,
300 .dma_timeout
= sl82c105_dma_timeout
,
303 static const struct ide_port_info sl82c105_chipset __devinitdata
= {
305 .init_chipset
= init_chipset_sl82c105
,
306 .enablebits
= {{0x40,0x01,0x01}, {0x40,0x10,0x10}},
307 .port_ops
= &sl82c105_port_ops
,
308 .dma_ops
= &sl82c105_dma_ops
,
309 .host_flags
= IDE_HFLAG_IO_32BIT
|
310 IDE_HFLAG_UNMASK_IRQS
|
311 /* FIXME: check for Compatibility mode in generic IDE PCI code */
312 #if defined(CONFIG_LOPEC) || defined(CONFIG_SANDPOINT)
313 IDE_HFLAG_FORCE_LEGACY_IRQS
|
315 IDE_HFLAG_SERIALIZE_DMA
|
316 IDE_HFLAG_NO_AUTODMA
,
317 .pio_mask
= ATA_PIO5
,
318 .mwdma_mask
= ATA_MWDMA2
,
321 static int __devinit
sl82c105_init_one(struct pci_dev
*dev
, const struct pci_device_id
*id
)
323 struct ide_port_info d
= sl82c105_chipset
;
324 u8 rev
= sl82c105_bridge_revision(dev
);
328 * Never ever EVER under any circumstances enable
329 * DMA when the bridge is this old.
331 printk(KERN_INFO
"W82C105_IDE: Winbond W83C553 bridge "
332 "revision %d, BM-DMA disabled\n", rev
);
335 d
.host_flags
&= ~IDE_HFLAG_SERIALIZE_DMA
;
338 return ide_setup_pci_device(dev
, &d
);
341 static const struct pci_device_id sl82c105_pci_tbl
[] = {
342 { PCI_VDEVICE(WINBOND
, PCI_DEVICE_ID_WINBOND_82C105
), 0 },
345 MODULE_DEVICE_TABLE(pci
, sl82c105_pci_tbl
);
347 static struct pci_driver driver
= {
348 .name
= "W82C105_IDE",
349 .id_table
= sl82c105_pci_tbl
,
350 .probe
= sl82c105_init_one
,
353 static int __init
sl82c105_ide_init(void)
355 return ide_pci_register_driver(&driver
);
358 module_init(sl82c105_ide_init
);
360 MODULE_DESCRIPTION("PCI driver module for W82C105 IDE");
361 MODULE_LICENSE("GPL");